diff --git a/include/FastSIMD/ToolSet/ARM/128/i32x4.h b/include/FastSIMD/ToolSet/ARM/128/i32x4.h
index 27b3be6..de9c8d8 100644
--- a/include/FastSIMD/ToolSet/ARM/128/i32x4.h
+++ b/include/FastSIMD/ToolSet/ARM/128/i32x4.h
@@ -12,7 +12,7 @@ namespace FS
 
         using NativeType = int32x4_t;
         using ElementType = std::int32_t;
-        using MaskType = m32<ElementCount, true, SIMD>;
+        using MaskType = m32<ElementCount, false, SIMD>;
         using MaskTypeArg = m32<ElementCount, true, SIMD>;
 
         FS_FORCEINLINE Register() = default;
diff --git a/include/FastSIMD/ToolSet/ARM/128/m32x4.h b/include/FastSIMD/ToolSet/ARM/128/m32x4.h
index 239a618..2074f14 100644
--- a/include/FastSIMD/ToolSet/ARM/128/m32x4.h
+++ b/include/FastSIMD/ToolSet/ARM/128/m32x4.h
@@ -4,54 +4,56 @@
 
 namespace FS
 {
+    namespace impl
+    {
+        struct ArmMaskBase32x4
+        {
+            uint32x4_t native;
+        };
+    }
+
     template<FastSIMD::FeatureSet SIMD, bool OPTIMISE_FLOAT>
-    struct Register<Mask<32, OPTIMISE_FLOAT>, 4, SIMD, std::enable_if_t<SIMD & FastSIMD::FeatureFlag::NEON>>
+    struct Register<Mask<32, OPTIMISE_FLOAT>, 4, SIMD, std::enable_if_t<SIMD & FastSIMD::FeatureFlag::ARM>>
+        : std::conditional_t<OPTIMISE_FLOAT, impl::ArmMaskBase32x4, Register<Mask<32, true>, 4, SIMD>>
     {
         static constexpr size_t ElementCount = 4;
         static constexpr auto FeatureFlags = SIMD;
         
-        using NativeType = uint32x4_t;
+        using NativeType = decltype(ArmMaskBase32x4::native);
         using ElementType = Mask<32, OPTIMISE_FLOAT>;
         using MaskType = Register;
         using MaskTypeArg = Register;
 
         FS_FORCEINLINE Register() = default;
-
-        template<typename T = NativeType>
-        FS_FORCEINLINE Register( std::enable_if_t<OPTIMISE_FLOAT, T> v ) : native( v ) { }
-
-        template<typename T = Register<Mask<32, false>, 4, SIMD>>
-        FS_FORCEINLINE Register( const std::enable_if_t<OPTIMISE_FLOAT, T>& v ) : native( v.native ) { }
+        FS_FORCEINLINE Register( NativeType v ) { this->native = v; }
         
         FS_FORCEINLINE NativeType GetNative() const
         {
-            return native;
+            return this->native;
         }
 
         FS_FORCEINLINE Register& operator &=( const Register& rhs )
         {
-            native = vandq_u32( native, rhs.native );
+            this->native = vandq_u32( this->native, rhs.native );
             return *this;
         }
         
         FS_FORCEINLINE Register& operator |=( const Register& rhs )
         {
-            native = vorrq_u32( native, rhs.native );
+            this->native = vorrq_u32( this->native, rhs.native );
             return *this;
         }
         
         FS_FORCEINLINE Register& operator ^=( const Register& rhs )
         {
-            native = veorq_u32( native, rhs.native );
+            this->native = veorq_u32( this->native, rhs.native );
             return *this;
         }
         
         FS_FORCEINLINE Register operator ~() const
         {
-            return vmvnq_u32( native );        
+            return vmvnq_u32( this->native );        
         }
-
-        NativeType native;
     };
 
     template<FastSIMD::FeatureSet SIMD, bool B, typename = EnableIfNative<Register<Mask<32, B>, 4, SIMD>>>
diff --git a/include/FastSIMD/ToolSet/Generic/Scalar/mNx1.h b/include/FastSIMD/ToolSet/Generic/Scalar/mNx1.h
index e6355cc..afe3a3b 100644
--- a/include/FastSIMD/ToolSet/Generic/Scalar/mNx1.h
+++ b/include/FastSIMD/ToolSet/Generic/Scalar/mNx1.h
@@ -4,49 +4,56 @@
 
 namespace FS
 {
-    template<FastSIMD::FeatureSet SIMD, size_t N>
-    struct Register<Mask<N, true>, 1, SIMD>
+    namespace impl
+    {
+        struct GenericMaskBase
+        {
+            bool native;
+        };
+    }
+
+    template<FastSIMD::FeatureSet SIMD, std::size_t N, bool OPTIMISE_FLOAT>
+    struct Register<Mask<N, OPTIMISE_FLOAT>, 1, SIMD>
+        : std::conditional_t<OPTIMISE_FLOAT, impl::GenericMaskBase, Register<Mask<N, true>, 1, SIMD>>
     {
         static constexpr size_t ElementCount = 1;
         static constexpr auto FeatureFlags = SIMD;
         
         using NativeType = bool;
-        using ElementType = Mask<N, true>;
+        using ElementType = Mask<N, OPTIMISE_FLOAT>;
         using MaskType = Register;
         using MaskTypeArg = Register;
 
         FS_FORCEINLINE Register() = default;
-        FS_FORCEINLINE Register( NativeType v ) : native( v ) { }
+        FS_FORCEINLINE Register( NativeType v ) { this->native = v; }
         
         FS_FORCEINLINE NativeType GetNative() const
         {
-            return native;
+            return this->native;
         }
 
         FS_FORCEINLINE Register& operator &=( const Register& rhs )
         {
-            native = native && rhs.native;
+            this->native = this->native && rhs.native;
             return *this;
         }
         
         FS_FORCEINLINE Register& operator |=( const Register& rhs )
         {
-            native = native || rhs.native;
+            this->native = this->native || rhs.native;
             return *this;
         }
         
         FS_FORCEINLINE Register& operator ^=( const Register& rhs )
         {
-            native = native ^ rhs.native;
+            this->native = this->native ^ rhs.native;
             return *this;
         }
         
         FS_FORCEINLINE Register operator ~() const
         {
-            return !native;   
+            return !this->native;   
         }
-
-        NativeType native;
     };
 
     template<FastSIMD::FeatureSet SIMD, size_t N, bool B, typename = EnableIfNative<Register<Mask<N, B>, 1, SIMD>>>
@@ -66,24 +73,4 @@ namespace FS
     {
         return static_cast<BitStorage<1>>( a.native );
     }
-
-    template<FastSIMD::FeatureSet SIMD, size_t N>
-    struct Register<Mask<N, false>, 1, SIMD> : Register<Mask<N, true>, 1, SIMD>
-    {
-        static constexpr size_t ElementCount = 1;
-        static constexpr auto FeatureFlags = SIMD;
-        
-        using NativeType = bool;
-        using ElementType = Mask<32, false>;
-        using MaskType = Register;
-        using MaskTypeArg = Register<Mask<N, true>, 1, SIMD>;
-
-        FS_FORCEINLINE Register() = default;
-        FS_FORCEINLINE Register( NativeType v ) : Register<Mask<N, true>, 1, SIMD>( v ) { }
-        
-        FS_FORCEINLINE Register operator ~() const
-        {
-            return !this->native;   
-        }
-    };
 }
diff --git a/include/FastSIMD/ToolSet/WASM/128/i32x4.h b/include/FastSIMD/ToolSet/WASM/128/i32x4.h
index 6df5d00..f879354 100644
--- a/include/FastSIMD/ToolSet/WASM/128/i32x4.h
+++ b/include/FastSIMD/ToolSet/WASM/128/i32x4.h
@@ -12,7 +12,7 @@ namespace FS
 
         using NativeType = v128_t;
         using ElementType = std::int32_t;
-        using MaskType = m32<ElementCount, true, SIMD>;
+        using MaskType = m32<ElementCount, false, SIMD>;
         using MaskTypeArg = m32<ElementCount, true, SIMD>;
 
         FS_FORCEINLINE Register() = default;
diff --git a/include/FastSIMD/ToolSet/WASM/128/m32x4.h b/include/FastSIMD/ToolSet/WASM/128/m32x4.h
index 886760c..846bab6 100644
--- a/include/FastSIMD/ToolSet/WASM/128/m32x4.h
+++ b/include/FastSIMD/ToolSet/WASM/128/m32x4.h
@@ -4,54 +4,56 @@
 
 namespace FS
 {
+    namespace impl
+    {
+        struct WasmMaskBase32x4
+        {
+            v128_t native;
+        };
+    }
+
     template<FastSIMD::FeatureSet SIMD, bool OPTIMISE_FLOAT>
     struct Register<Mask<32, OPTIMISE_FLOAT>, 4, SIMD, std::enable_if_t<SIMD & FastSIMD::FeatureFlag::WASM>>
+        : std::conditional_t<OPTIMISE_FLOAT, impl::WasmMaskBase32x4, Register<Mask<32, true>, 4, SIMD>>
     {
         static constexpr size_t ElementCount = 4;
         static constexpr auto FeatureFlags = SIMD;
 
-        using NativeType = v128_t;
+        using NativeType = decltype(WasmMaskBase32x4::native);
         using ElementType = Mask<32, OPTIMISE_FLOAT>;
         using MaskType = Register;
         using MaskTypeArg = Register;
 
         FS_FORCEINLINE Register() = default;
-
-        template<typename T = NativeType>
-        FS_FORCEINLINE Register( std::enable_if_t<OPTIMISE_FLOAT, T> v ) : native( v ) { }
-
-        template<typename T = Register<Mask<32, false>, 4, SIMD>>
-        FS_FORCEINLINE Register( const std::enable_if_t<OPTIMISE_FLOAT, T>& v ) : native( v.native ) { }
+        FS_FORCEINLINE Register( NativeType v ) { this->native = v; }
 
         FS_FORCEINLINE NativeType GetNative() const
         {
-            return native;
+            return this->native;
         }
 
         FS_FORCEINLINE Register& operator &=( const Register& rhs )
         {
-            native = wasm_v128_and( native, rhs.native );
+            this->native = wasm_v128_and( this->native, rhs.native );
             return *this;
         }
 
         FS_FORCEINLINE Register& operator |=( const Register& rhs )
         {
-            native = wasm_v128_or( native, rhs.native );
+            this->native = wasm_v128_or( this->native, rhs.native );
             return *this;
         }
 
         FS_FORCEINLINE Register& operator ^=( const Register& rhs )
         {
-            native = wasm_v128_xor( native, rhs.native );
+            this->native = wasm_v128_xor( this->native, rhs.native );
             return *this;
         }
 
         FS_FORCEINLINE Register operator ~() const
         {
-            return wasm_v128_not( native );
+            return wasm_v128_not( this->native );
         }
-
-        NativeType native;
     };
 
     template<FastSIMD::FeatureSet SIMD, bool B, typename = EnableIfNative<Register<Mask<32, B>, 4, SIMD>>>
diff --git a/include/FastSIMD/ToolSet/x86/512/i32x16.h b/include/FastSIMD/ToolSet/x86/512/i32x16.h
index 2c8de8f..00c07d3 100644
--- a/include/FastSIMD/ToolSet/x86/512/i32x16.h
+++ b/include/FastSIMD/ToolSet/x86/512/i32x16.h
@@ -12,7 +12,7 @@ namespace FS
 
         using NativeType = __m512i;
         using ElementType = std::int32_t;
-        using MaskType = m32<ElementCount, true, SIMD>;
+        using MaskType = m32<ElementCount, false, SIMD>;
         using MaskTypeArg = m32<ElementCount, true, SIMD>;
 
         FS_FORCEINLINE Register() = default;
diff --git a/include/FastSIMD/ToolSet/x86/512/mNx16.h b/include/FastSIMD/ToolSet/x86/512/mNx16.h
index 9b36edb..70b2af9 100644
--- a/include/FastSIMD/ToolSet/x86/512/mNx16.h
+++ b/include/FastSIMD/ToolSet/x86/512/mNx16.h
@@ -4,55 +4,56 @@
 
 namespace FS
 {
+    namespace impl
+    {
+        struct AVX512MaskBase
+        {
+            __mmask16 native;
+        };
+    }
+
     template<FastSIMD::FeatureSet SIMD, std::size_t N, bool OPTIMISE_FLOAT>
     struct Register<Mask<N, OPTIMISE_FLOAT>, 16, SIMD, std::enable_if_t<SIMD & FastSIMD::FeatureFlag::AVX512_F>>
+        : std::conditional_t<OPTIMISE_FLOAT, impl::AVX512MaskBase, Register<Mask<N, true>, 16, SIMD>>
     {
         static constexpr size_t ElementCount = 16;
         static constexpr auto FeatureFlags = SIMD;
         
-        using NativeType = __mmask16;
-        using ElementType = Mask<32, OPTIMISE_FLOAT>;
+        using NativeType = decltype(AVX512MaskBase::native);
+        using ElementType = Mask<N, OPTIMISE_FLOAT>;
         using MaskType = Register;
         using MaskTypeArg = Register;
 
         FS_FORCEINLINE Register() = default;
-
-        template<typename T = NativeType>
-        FS_FORCEINLINE Register( std::enable_if_t<OPTIMISE_FLOAT, T> v ) : native( v ) { }
-
-        template<typename T = Register<Mask<N, false>, 16, SIMD>>
-        FS_FORCEINLINE Register( const std::enable_if_t<OPTIMISE_FLOAT, T>& v ) : native( v.native ) { }
-
+        FS_FORCEINLINE Register( NativeType v ) { this->native = v; }
         
         FS_FORCEINLINE NativeType GetNative() const
         {
-            return native;
+            return this->native;
         }
 
         FS_FORCEINLINE Register& operator &=( const Register& rhs )
         {
-            native = ( native & rhs.native );
+            this->native = ( this->native & rhs.native );
             return *this;
         }
         
         FS_FORCEINLINE Register& operator |=( const Register& rhs )
         {
-            native = ( native | rhs.native );
+            this->native = ( this->native | rhs.native );
             return *this;
         }
         
         FS_FORCEINLINE Register& operator ^=( const Register& rhs )
         {
-            native = ( native ^ rhs.native );
+            this->native = ( this->native ^ rhs.native );
             return *this;
         }
         
         FS_FORCEINLINE Register operator ~() const
         {
-            return ~native;      
+            return ~this->native;      
         }
-
-        NativeType native;
     };
     
     template<FastSIMD::FeatureSet SIMD, std::size_t N, bool B, typename = EnableIfNative<Register<Mask<N, B>, 16, SIMD>>>
diff --git a/tests/test.inl b/tests/test.inl
index fac0ffc..a4da5b8 100644
--- a/tests/test.inl
+++ b/tests/test.inl
@@ -201,7 +201,7 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
     struct GenArg<FS::Register<FS::Mask<MN, MB>, N, S>>
     {
         template<typename... ARGs>
-        static FS::Register<FS::Mask<MN, MB>, N, S> Load( size_t inIdx, size_t argIdx, float* rnd, ARGs... )
+        static FS::Register<FS::Mask<MN, MB>, N, S> Load( size_t inIdx, size_t argIdx, std::conditional_t<MB, float, int>* rnd, ARGs... )
         {
             return FS::Load<N>( rnd + inIdx + argIdx * N ) > FS::Load<N>( rnd + inIdx + argIdx * N + 1 );
         }
@@ -279,6 +279,7 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
         using TestRegi32 = TestReg<int32_t>;
         using TestRegf32 = TestReg<float>;
         using TestRegm32 = typename TestRegf32::MaskType;
+        using TestRegm32i = typename TestRegi32::MaskType;
 
 
         RegisterTest( tests, "m32 bit mask", []( TestRegm32 a ) { return a; } );
@@ -290,6 +291,15 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
         RegisterTest( tests, "m32 bit not operator", std::bit_not<TestRegm32>() );
         RegisterTest( tests, "m32 bit and not", []( TestRegm32 a, TestRegm32 b ) { return FS::BitwiseAndNot( a, b ); } );
 
+        RegisterTest( tests, "m32i bit mask", []( TestRegm32 a ) { return a; } );
+        RegisterTest( tests, "m32i any mask", []( TestRegm32 a ) { return FS::AnyMask( a ); } );
+
+        RegisterTest( tests, "m32i bit and operator", std::bit_and<TestRegm32i>() );
+        RegisterTest( tests, "m32i bit or operator", std::bit_or<TestRegm32i>() );
+        RegisterTest( tests, "m32i bit xor operator", std::bit_xor<TestRegm32i>() );
+        RegisterTest( tests, "m32i bit not operator", std::bit_not<TestRegm32i>() );
+        RegisterTest( tests, "m32i bit and not", []( TestRegm32i a, TestRegm32i b ) { return FS::BitwiseAndNot( a, b ); } );
+
         RegisterTest( tests, "i32 load store", []( TestRegi32 a ) { return a; } );
         RegisterTest( tests, "i32 load scalar", []( int32_t a ) { return TestRegi32( a ); } );
         RegisterTest( tests, "i32 splat", []( int32_t a ) { return FS::Splat<TestRegi32::ElementCount>( a ); } );
@@ -402,17 +412,27 @@ class FastSIMD::DispatchClass<TestFastSIMD<RegisterBytes, Relaxed>, SIMD> : publ
             return FS::Reciprocal( FS::Select( a > TestRegf32( 0 ), clamped, -clamped ) );
         } ).relaxedAccuracy = 8192;
 
-        RegisterTest( tests, "f32 cos", []( TestRegf32 a ) { return FS::Cos( a ); } ).relaxedAccuracy = 8192;
-        RegisterTest( tests, "f32 sin", []( TestRegf32 a ) { return FS::Sin( a ); } ).relaxedAccuracy = 8192;
-        RegisterTest( tests, "f32 exp", []( TestRegf32 a ) { return FS::Exp( a ); } ).relaxedAccuracy = 8192;
-        RegisterTest( tests, "f32 log", []( TestRegf32 a ) { return FS::Log( a ); } ).relaxedAccuracy = 8192;
+        RegisterTest( tests, "f32 cos", []( TestRegf32 a ) { return FS::Cos( FS::Min( FS::Max( a, TestRegf32( -1.e+16f ) ), TestRegf32( 1.e+16f ) ) ); } ).relaxedAccuracy = 8192;
+        RegisterTest( tests, "f32 sin", []( TestRegf32 a ) { return FS::Sin( FS::Min( FS::Max( a, TestRegf32( -1.e+16f ) ), TestRegf32( 1.e+16f ) ) ); } ).relaxedAccuracy = 8192;
+        RegisterTest( tests, "f32 exp", []( TestRegf32 a ) { return FS::Exp( FS::Min( FS::Max( a, TestRegf32( -1.e+16f ) ), TestRegf32( 1.e+16f ) ) ); } ).relaxedAccuracy = 8192;
+        RegisterTest( tests, "f32 log", []( TestRegf32 a ) { return FS::Log( FS::Min( FS::Max( a, TestRegf32( -1.e+16f ) ), TestRegf32( 1.e+16f ) ) ); } ).relaxedAccuracy = 8192;
         RegisterTest( tests, "f32 pow", []( TestRegf32 a, TestRegf32 b ) { return FS::Pow( a, b ); } ).relaxedAccuracy = 8192;
 
         RegisterTest( tests, "i32 convert to f32", []( TestRegi32 a ) { return FS::Convert<float>( a ); } );
-        RegisterTest( tests, "i32 cast to f32", []( TestRegi32 a ) { return FS::Cast<float>( a ); } );
         RegisterTest( tests, "f32 convert to i32", []( TestRegf32 a ) { return FS::Convert<int32_t>( FS::Min( FS::Max( a, TestRegf32( 2147483648 ) ), TestRegf32( 2147483520 ) ) ); } );
+
         RegisterTest( tests, "f32 cast to i32", []( TestRegf32 a ) { return FS::Cast<int32_t>( a ); } );
+        RegisterTest( tests, "i32 cast to f32", []( TestRegi32 a ) { return FS::Cast<float>( a ); } );
 
+        if constexpr( !( SIMD & FeatureFlag::AVX512_F ) )
+        {
+            RegisterTest( tests, "f32 cast to m32", []( TestRegf32 a ) { return FS_BIND_INTRINSIC( FS::Cast<FS::Mask<32>> )( a ); } );
+            RegisterTest( tests, "i32 cast to m32", []( TestRegi32 a ) { return FS_BIND_INTRINSIC( FS::Cast<FS::Mask<32>> )( a ); } );
+            RegisterTest( tests, "m32 cast to i32", []( TestRegm32 a ) { return FS_BIND_INTRINSIC( FS::Cast<int32_t> )( a ) ; } );
+            RegisterTest( tests, "m32 cast to f32", []( TestRegm32 a ) { return FS_BIND_INTRINSIC( FS::Cast<float> )( a ); } );
+            RegisterTest( tests, "m32i cast to i32", []( TestRegm32i a ) { return FS_BIND_INTRINSIC( FS::Cast<int32_t> )( a ); } );
+            RegisterTest( tests, "m32i cast to f32", []( TestRegm32i a ) { return FS_BIND_INTRINSIC( FS::Cast<float> )( a ); } );
+        }
         return tests;
     }
 };