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In my stats.txt:
ramulator.dram_cycles 400004732 # Number of DRAM cycles simulated
sim_seconds 0.666408 # Number of seconds simulated
For this case, I used DDR4_2400M_x8, which operates at a DRAM frequency of 1200 MHz. The ramulator.dram_cycles value in the stats.txt file is 400,004,732. Therefore, I calculated the DRAM simulation time as 400,004,732/1200 MHz=0.33 seconds. Meanwhile, the sim_tick value in stats.txt is 0.66 seconds. This suggests that the DRAM component accounts for approximately 0.33/0.66=50% of the total simulation time for the X86 system in SE Mode.
However, when I applied the formula, I found that the DRAM component consistently accounts for 50% of the total simulation time, regardless of the architecture or neural network model size, whether big or small. This seems odd and makes me suspect that there might be an issue with the formula or conclusion I previously mentioned.
The text was updated successfully, but these errors were encountered:
In my stats.txt:
ramulator.dram_cycles 400004732 # Number of DRAM cycles simulated
sim_seconds 0.666408 # Number of seconds simulated
For this case, I used DDR4_2400M_x8, which operates at a DRAM frequency of 1200 MHz. The ramulator.dram_cycles value in the stats.txt file is 400,004,732. Therefore, I calculated the DRAM simulation time as 400,004,732/1200 MHz=0.33 seconds. Meanwhile, the sim_tick value in stats.txt is 0.66 seconds. This suggests that the DRAM component accounts for approximately 0.33/0.66=50% of the total simulation time for the X86 system in SE Mode.
However, when I applied the formula, I found that the DRAM component consistently accounts for 50% of the total simulation time, regardless of the architecture or neural network model size, whether big or small. This seems odd and makes me suspect that there might be an issue with the formula or conclusion I previously mentioned.
The text was updated successfully, but these errors were encountered: