vivado_hls.log

INFO: [HLS 200-10] Running 'C:/Xilinx/Vivado/2018.3/bin/unwrapped/win64.o/vivado_hls.exe'
INFO: [HLS 200-10] For user 'pacel' on host 'pacel-windows' (Windows NT_amd64 version 6.2) on Tue Apr 10 18:52:56 -0500 2018
INFO: [HLS 200-10] In directory 'C:/Users/pacel/Documents/Spring_2024/ECE1155/hardware-encryption'
INFO: [HLS 200-10] Opening project 'C:/Users/pacel/Documents/Spring_2024/ECE1155/hardware-encryption/AES_HLS_ECE1155'.
INFO: [HLS 200-10] Opening solution 'C:/Users/pacel/Documents/Spring_2024/ECE1155/hardware-encryption/AES_HLS_ECE1155/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.25ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020clg400-1'
INFO: [XFORM 203-1172] Optimizing floating point zeros and discarding its signedness.
INFO: [XFORM 203-1172] Optimizing floating point zeros and discarding its signedness.
INFO: [XFORM 203-1173] Reordering floating point operations aggressively.
INFO: [XFORM 203-1176] Optimizing floating point comparison without checking NaN.
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: config_sdx -optimization_level=none
INFO: [HLS 200-435] Setting 'config_sdx -target' configuration: set_clock_uncertainty default
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Tue Apr 10 18:53:05 2018...