-
Notifications
You must be signed in to change notification settings - Fork 6
/
tt.core.universal.s
4037 lines (3685 loc) · 58.5 KB
/
tt.core.universal.s
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
# Torture test for instructions common in MIPS32 and MIPS64
# Based on SPIM torture test
#
# Copyright (c) 1990-2018, James R. Larus, Pavel Kryukov
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation and/or
# other materials provided with the distribution.
#
# Neither the name of the James R. Larus nor the names of its contributors may be
# used to endorse or promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.set noreorder
.set gp=32 # Do not generate 64 bit instructions
.data
saved_ret_pc: .word 0 #, Holds PC to return from main
m3: .asciiz "The next few lines should contain exception error messages\n"
m4: .asciiz "Done with exceptions\n\n"
m5: .asciiz "Expect an address error exception:\n "
m6: .asciiz "Expect two address error exceptions:\n"
.text
.globl main
main:
sw $31, saved_ret_pc
#
# The first thing to do is to test the exceptions:
#
li $v0, 4 # syscall 4 (print_str)
la $a0, m3
syscall
# Exception 1 (INT) -- Not implemented yet
# Exception 4 (ADEL)
li $t0, 0x400000
lw $3, 1($t0)
# Exception 5 (ADES)
sw $3, 1($t0)
# Exception 6 (IBUS) -- Can't test and continue
# Exception 7 (DBUS)
lw $3, 10000000($t0)
# Exception 8 (SYSCALL) -- Not implemented
# Exception 9 (BKPT)
break 0
# Exception 10 (RI) -- Not implemented (can't enter bad instructions)
# Exception 12 (overflow)
li $t0, 0x7fffffff
add $t0, $t0, $t0
li $v0, 4 # syscall 4 (print_str)
la $a0, m4
syscall
#
# Try modifying R0
#
add $0, $0, 1
bnez $0, fail
#
# Test the timer:
#
# .data
#timer_: .asciiz "Testing timer\n"
# .text
# li $v0, 4 # syscall 4 (print_str)
# la $a0, timer_
# syscall
#
# mtc0 $0, $9 # Clear count register
#timer1_:
# mfc0 $9, $9
# bne $9, 10, timer1_# Count up to 10
#
# Test .ASCIIZ
.data
asciiz_:.asciiz "Testing .asciiz\n"
str0: .asciiz ""
str1: .asciiz "a"
str2: .asciiz "bb"
str3: .asciiz "ccc"
str4: .asciiz "dddd"
str5: .asciiz "eeeee"
str06: .asciiz "", "a", "bb", "ccc", "dddd", "eeeee"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, asciiz_
syscall
la $a0, str0
li $a1, 6
jal ck_strings
la $a0, str06
li $a1, 6
jal ck_strings
j over_strlen
ck_strings:
move $s0, $a0
move $s1, $ra
li $s2, 0
l_asciiz1:
move $a0, $s0
jal strlen
bne $v0, $s2, fail
add $s0, $s0, $v0 # skip string
add $s0, $s0, 1 # skip null byte
add $s2, 1
blt $s2, $a1, l_asciiz1
move $ra, $s1
jal $ra
strlen:
li $v0, 0 # num chars
move $t0, $a0 # str pointer
l_strlen1:
lb $t1, 0($t0)
add $t0, 1
add $v0, 1
bnez $t1, l_strlen1
sub $v0, $v0, 1 # don't count null byte
jr $31
over_strlen:
#
# Now, test each instruction
#
.data
add_: .asciiz "Testing ADD\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, add_
break
syscall
li $2, 1
li $3, -1
add $4, $0, $0
bnez $4, fail
add $4, $0, $2
bne $4, 1, fail
add $4, $4, $3
bnez $4, fail
.data
addi_: .asciiz "Testing ADDI\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, addi_
syscall
addi $4, $0, 0
bnez $4, fail
addi $4, $0, 1
bne $4, 1, fail
addi $4, $4, -1
bnez $4, fail
.data
addu_: .asciiz "Testing ADDU\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, addu_
syscall
li $2, 1
li $3, -1
addu $4, $0, $0
bnez $4, fail
addu $4, $0, $2
bne $4, 1, fail
addu $4, $4, $3
bnez $4, fail
li $2, 0x7fffffff
addu $2, $2, $2 # should not trap
bne $2, -2, fail
.data
and_: .asciiz "Testing AND\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, and_
syscall
li $2, 1
li $3, -1
and $4, $0, $0
bnez $4, fail
and $4, $2, $2
beqz $4, fail
and $4, $2, $3
bne $4, 1, fail
.data
andi_: .asciiz "Testing ANDI\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, andi_
syscall
li $2, 1
li $3, -1
andi $4, $0, 0
bnez $4, fail
and $4, $2, 1
beqz $4, fail
and $4, $2, -1
bne $4, 1, fail
and $4, $3, -1
bne $4, $3, fail
.data
beq_: .asciiz "Testing BEQ\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, beq_
syscall
li $2, -1
li $3, 1
beq $0, $0, l1
j fail
l1: beq $2, $2, l2
j fail
l2: beq $3, $2, fail
beq $2, $2, far_away # Check long branch
j fail
come_back:
li $2, 3
l2_1: sub $2, $2, 1
bnez $2, l2_1
.data
bne_: .asciiz "Testing BNE\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, bne_
syscall
li $2, -1
li $3, 1
bne $0, $0, fail
bne $2, $2, fail
bne $3, $2, l16
l16:
.data
break_: .asciiz "Testing BREAK\nExpect a exception message:\n "
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, break_
syscall
break 3
# COPz is not checked
# .data
#ccp_: .asciiz "Testing move to/from coprocessor control 0/1\n"
# .text
# li $v0, 4 # syscall 4 (print_str)
# la $a0, ccp_
# syscall
#
# li $2, 0x7f7f
# ctc0 $2, $3
# cfc0 $4, $3
# bne $2, $4, fail
# li $2, 0x7f7f
# ctc1 $2, $3
# cfc1 $4, $3
# bne $2, $4, fail
.data
clo_: .asciiz "Testing CLO\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, clo_
syscall
li $2, 0
clo $3, $2
bne $3, 0, fail
li $2, 0xffffffff
clo $3, $2
bne $3, 32, fail
li $2, 0xf0000000
clo $3, $2
bne $3, 4, fail
.data
clz_: .asciiz "Testing CLZ\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, clz_
syscall
li $2, 0
clz $3, $2
bne $3, 32, fail
li $2, 0xffffffff
clz $3, $2
bne $3, 0, fail
li $2, 0x0fff0000
clz $3, $2
bne $3, 4, fail
.data
div_: .asciiz "Testing DIV\n"
div2_: .asciiz "Expect exception caused by divide by 0:\n "
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, div_
syscall
li $2, 4
li $3, 2
li $4, -2
div $5, $2, $3
bne $5, 2, fail
mfhi $5
bne $5, 0, fail
div $5, $2, $4
bne $5, -2, fail
mfhi $5
bne $5, 0, fail
li $2, 0x80000000
li $4, 0xffffffff
div $5, $2, $4 # Overflows, but should not cause overflow
li $2, 1
li $4, 0xffffffff
div $5, $2, $4
bne $5, -1, fail
mfhi $5
bne $5, 0, fail
li $v0, 4 # syscall 4 (print_str)
la $a0, div2_
syscall
div $5, $2, $0
.data
divu_: .asciiz "Testing DIVU\n"
divu2_: .asciiz "Expect exception caused by divide by 0:\n "
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, divu_
syscall
li $2, 4
li $3, 2
li $4, -2
divu $5, $2, $3
bne $5, 2, fail
mfhi $5
bne $5, 0, fail
divu $0, $2, $3
mflo $5
bne $5, 2, fail
mfhi $5
bne $5, 0, fail
divu $5, $2, $4
bne $5, 0, fail
mfhi $5
bne $5, 4, fail
li $2, 0x80000000
li $4, 0xffffffff
divu $5, $2, $4 # Overflows, but should not cause overflow
li $2, 1
li $4, 0xffffffff
divu $5, $2, $4
bne $5, 0, fail
mfhi $5
bne $5, 1, fail
li $v0, 4 # syscall 4 (print_str)
la $a0, divu2_
syscall
divu $5, $2, $0
.data
j_: .asciiz "Testing J\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, j_
syscall
j l17
j fail
l17:
.data
jal_: .asciiz "Testing JAL\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, jal_
syscall
jal l18
l19: j l20
l18: la $4, l19
bne $31, $4, fail
jr $31
l20:
.data
jalr_: .asciiz "Testing JALR\n"
jalr2_: .asciiz "Expect an non-word boundary exception:\n "
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, jalr_
syscall
la $2, l21
jalr $3, $2
l23: j l22
l21: la $4, l23
bne $3, $4, fail
jr $3
l22: la $2, l21a
jalr $2
l23a: j l22a
l21a: la $4, l23a
bne $31, $4, fail
jr $31
l22a: li $v0, 4 # syscall 4 (print_str)
la $a0, jalr2_
syscall
la $2, l24
add $2, $2, 2
l24: jalr $3, $2
.data
jr_: .asciiz "Testing JR\n"
jr2_: .asciiz "Expect an non-word boundary exception:\n "
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, jr_
syscall
la $2, l25
jr $2
j fail
l25: li $v0, 4 # syscall 4 (print_str)
la $a0, jr2_
syscall
la $2, l27
add $2, $2, 2
l27: jr $2
.data
la_: .asciiz "Testing LA\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, la_
syscall
# Simple, cases, already tested
li $4, 101
la $5, 10($4)
bne $5, 111, fail
.data
lhu_: .asciiz "Testing LHU\n"
lh2_: .asciiz "Expect two address error exceptions:\n"
lhd_: .half 1, -1, 0, 0x8000
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, lhu_
syscall
la $2, lhd_
lhu $3, 0($2)
bne $3, 1, fail
lhu $3, 2($2)
bne $3, 0xffff, fail
lhu $3, 4($2)
bne $3, 0, fail
lhu $3, 6($2)
bne $3, 0x8000, fail
li $v0, 4 # syscall 4 (print_str)
la $a0, lh2_
syscall
li $t5, 0x7fffffff
lhu $3, 1000($t5)
lhu $3, 1001($t5)
.data
ll_: .asciiz "Testing LL\n"
ll1: .word 10
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, ll_
syscall
ll $2, ll1
bne $2, 10, fail
add $2, $2, 1
sc $2, ll1
lw $3, ll1
bne $2, $3, fail
.data
lui_: .asciiz "Testing LUI\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, lui_
syscall
lui $2, 0
bne $2, $0, fail
lui $2, 1
srl $2, $2, 16
addiu $2, $2, -1 # Don't do compare directly since it uses LUI
bne $2, $0, fail
lui $2, 1
andi $2, $2, 0xffff
bne $2, $0, fail
lui $2, 0xffff
srl $2, $2, 16
addiu $2, $2, 1
andi $2, $2, 0xffff
bne $2, $0, fail
.data
madd_: .asciiz "Testing MADD\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, madd_
syscall
mthi $0
mtlo $0
madd $0, $0
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
mtlo $0
mthi $0
li $4, 1
madd $4, $4
mfhi $3
bnez $3, fail
mflo $3
bne $3, 1, fail
li $3, 1
mtlo $3
mthi $0
li $4, -1
madd $3, $4
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
mtlo $0
mthi $0
li $3, 1
li $4, -1
madd $3, $4
mfhi $3
bne $3, 0xffffffff, fail
mflo $3
bne $3, 0xffffffff, fail
li $t0, 1
mtlo $t0
mthi $0
li $t0, 2
li $t1, -1
madd $t0, $t1
mfhi $3
bne $3, 0xffffffff, fail
mflo $3
bne $3, 0xffffffff, fail
mtlo $0
mthi $0
li $4, 0x10000
madd $4, $4
mfhi $3
bne $3, 1, fail
mflo $3
bne $3, 0, fail
li $4, 0x10000
madd $4, $4
mfhi $3
bne $3, 2, fail
mflo $3
bne $3, 0, fail
.data
maddu_: .asciiz "Testing MADDU\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, maddu_
syscall
mthi $0
mtlo $0
maddu $0, $0
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
li $4, 1
maddu $4, $4
mfhi $3
bnez $3, fail
mflo $3
bne $3, 1, fail
li $4, -1
maddu $4, $4
mfhi $3
bne $3, 0xfffffffe, fail
mflo $3
bne $3, 2, fail
# .data
#mcp_: .asciiz "Testing move to/from coprocessor z\n"
# .text
# li $v0, 4 # syscall 4 (print_str)
# la $a0, mcp_
# syscall
#
# li $2, 0x7f7f
# mtc0 $2, $3
# mfc0 $4, $3
# bne $2, $4, fail
# li $2, 0x7f7f
# mtc1 $2, $3
# mfc1 $4, $f3
# bne $2, $4, fail
# li $2, 0x7f7f
# li $3, 0xf7f7
# mtc1.d $2, $4
# mfc1.d $6, $4
# bne $2, $6, fail
# bne $3, $7, fail
.data
hilo_: .asciiz "Testing move to/from HI/LO\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, hilo_
syscall
mthi $0
mfhi $2
bnez $2, fail
mtlo $0
mflo $2
bnez $2, fail
li $2, 1
mthi $2
mfhi $3
bne $3, $2, fail
li $2, 1
mtlo $2
mflo $3
bne $3, $2, fail
li $2, -1
mthi $2
mfhi $3
bne $3, $2, fail
li $2, -1
mtlo $2
mflo $3
bne $3, $2, fail
# .data
#movf_: .asciiz "Testing MOVF\n"
# .text
# li $v0, 4 # syscall 4 (print_str)
# la $a0, movf_
# syscall
#
# li $2, 0x70
# ctc1 $2, $25
# li $2, 1
# li $3, 0
# li $4, 2
# movf $3, $2, 1
# bne $3, 1, fail
# movf $3, $4, 6
# bne $3, 1, fail
#
#
.data
movn_: .asciiz "Testing MOVN\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, movn_
syscall
li $2, 2
li $3, 3
li $4, 4
movn $4, $3, $0
bne $4, 4, fail
movn $4, $3, $2
bne $4, 3, fail
#
#
# .data
#movt_: .asciiz "Testing MOVT\n"
# .text
# li $v0, 4 # syscall 4 (print_str)
# la $a0, movt_
# syscall
#
# li $2, 0x70
# ctc1 $2, $25
# li $2, 1
# li $3, 0
# li $4, 2
# movt $3, $2, 1
# bne $3, 0, fail
# movt $3, $4, 6
# bne $3, 2, fail
#
#
.data
movz_: .asciiz "Testing MOVZ\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, movz_
syscall
li $2, 2
li $3, 3
li $4, 4
movz $4, $3, $2
bne $4, 4, fail
movz $4, $3, $0
bne $4, 3, fail
.data
msub_: .asciiz "Testing MSUB\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, msub_
syscall
mthi $0
mtlo $0
msub $0, $0
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
mthi $0
mtlo $0
li $4, 1
msub $4, $4
mfhi $3
bne $3, 0xffffffff, fail
mflo $3
bne $3, 0xffffffff, fail
li $4, 1
msub $3, $4
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
mthi $0
mtlo $0
li $4, 0x10000
msub $4, $4
mfhi $3
bne $3, 0xffffffff, fail
mflo $3
bne $3, 0, fail
mtlo $0
mthi $0
li $4, 1
li $5, -1
msub $5, $4
mfhi $3
bne $3, 0, fail
mflo $3
bne $3, 1, fail
.data
msubu_: .asciiz "Testing MSUBU\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, msubu_
syscall
mthi $0
mtlo $0
msubu $0, $0
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
mthi $0
mtlo $0
li $4, 1
msubu $4, $4
mfhi $3
bne $3, 0xffffffff, fail
mflo $3
bne $3, 0xffffffff, fail
mtlo $0
mthi $0
li $4, 1
li $5, -1
msubu $5, $4
mfhi $3
bne $3, 0xffffffff, fail
mflo $3
bne $3, 1, fail
.data
mul_: .asciiz "Testing MUL\n"
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, mul_
syscall
li $2, 1
mul $3, $2, 0
bnez $3, fail
mul $3, $2, 1
bne $3, 1, fail
mul $3, $2, 10
bne $3, 10, fail
mult $0, $0
mfhi $3
bnez $3, fail
mflo $3
bnez $3, fail
li $4, 1
mult $4, $4
mfhi $3
bnez $3, fail
mflo $3
bne $3, 1, fail
li $4, -1
mult $4, $4
mfhi $3
bnez $3, fail
mflo $3
bne $3, 1, fail
li $4, -1
li $5, 1
mult $4, $5
mfhi $3
bne $3, -1, fail
mflo $3
bne $3, -1, fail
li $4, 0x10000
mult $4, $4
mfhi $3
bne $3, 1, fail
mflo $3
bne $3, 0, fail
li $4, 0x80000000
mult $4, $4
mfhi $3
bne $3, 0x40000000, fail
mflo $3
bne $3, 0, fail
.data
mulo_: .asciiz "Testing MULO\n"
mulo1_: .asciiz "Expect an exception:\n "
.text
li $v0, 4 # syscall 4 (print_str)
la $a0, mulo_
syscall
mulo $2, $0, $0
bne $2, 0, fail
li $4, 1
mulo $2, $4, $4
bne $2, 1, fail
li $4, -1
mulo $2, $4, $4
bne $2, 1, fail
li $4, -1
li $5, 1
mulo $2, $4, $5
bne $2, -1, fail
li $v0, 4 # syscall 4 (print_str)
la $a0, mulo1_
syscall
li $4, 0x10000
mulo $2, $4, $4
bne $2, 0, fail
.data