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my_core.tlv
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my_core.tlv
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\m4_TLV_version 1d: tl-x.org
\SV
// This code can be found in: https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/risc-v_shell.tlv
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/warp-v_includes/1d1023ccf8e7b0a8cf8e8fc4f0a823ebb61008e3/risc-v_defs.tlv'])
m4_include_lib(['https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/risc-v_shell_lib.tlv'])
m4_test_prog()
\SV
m4_makerchip_module // (Expanded in Nav-TLV pane.)
/* verilator lint_on WIDTH */
\TLV
// https://riscv.org/technical/specifications/ - unprivilleged
$reset = *reset;
// addr is byte offset (32 bit instruction: 4 bytes) - do all in 1 clock cycle
$next_pc[31:0] = $reset ? 0 :
$taken_br ? $br_tgt_pc :
$pc + 4;
$pc[31:0] = >>1$next_pc;
`READONLY_MEM($pc, $$instr[31:0])
// determine instruction type
$is_i_instr = $instr[6:2] ==? 5'b0000x ||
$instr[6:2] ==? 5'b001x0 ||
$instr[6:2] ==? 5'b11001;
$is_u_instr = $instr[6:2] ==? 5'b0x101;
$is_s_instr = $instr[6:2] ==? 5'b0100x; // store (to memory) instructions
$is_r_instr = $instr[6:2] ==? 5'b01011 ||
$instr[6:2] ==? 5'b011x0 ||
$instr[6:2] ==? 5'b10100;
$is_j_instr = $instr[6:2] ==? 5'b11011;
$is_b_instr = $instr[6:2] ==? 5'b11000;
// extract instruction parameters
//register input indices
$opcode[6:0] = $instr[6:0];
$rs1[4:0] = $instr[19:15];
$rs2[4:0] = $instr[24:20];
//register result index
$rd[4:0] = $instr[11:7];
//function codes - 3 and 7 bits
$funct3[2:0] = $instr[14:12];
$funct7[6:0] = $instr[31:25];
//which parameter are relevant for the current instruction/opcode?
$rs1_valid = $is_r_instr || $is_i_instr || $is_s_instr ||
$is_b_instr;
$rs2_valid = $is_r_instr || $is_s_instr || $is_b_instr;
$rd_valid = $is_r_instr || $is_i_instr || $is_u_instr ||
$is_j_instr;
$funct3_valid = $is_r_instr || $is_i_instr || $is_s_instr ||
$is_b_instr;
$funct7_valid = $is_r_instr;
$imm_valid = ! $is_r_instr;
$imm[31:0] = $is_i_instr ? {{21{$instr[31]}}, $instr[30:20]} :
$is_s_instr ? {{21{$instr[31]}}, $instr[30:25], $instr[11:8], $instr[7]} :
$is_b_instr ? {{20{$instr[31]}}, $instr[7], $instr[30:25], $instr[11:8], 1'b0} :
$is_u_instr ? {$instr[31], $instr[30:20], $instr[19:12], 12'b0} :
$is_j_instr ? {{12{$instr[31]}}, $instr[19:12], $instr[20], $instr[30:25], $instr[24:21], 1'b0} :
32'b0; // Default
// determine specific instruction
$dec_bits[10:0] = {$instr[30],$funct3,$opcode};
$is_beq = $dec_bits ==? 11'bx_000_1100011;
$is_bne = $dec_bits ==? 11'bx_001_1100011;
$is_blt = $dec_bits ==? 11'bx_100_1100011;
$is_bge = $dec_bits ==? 11'bx_101_1100011;
$is_bltu = $dec_bits ==? 11'bx_110_1100011;
$is_bgeu = $dec_bits ==? 11'bx_111_1100011;
$is_addi = $dec_bits ==? 11'bx_000_0010011;
$is_add = $dec_bits ==? 11'b0_000_0110011;
$is_sub = $dec_bits ==? 11'b1_000_0110011;
$is_sll = $dec_bits ==? 11'b0_001_0110011;
$is_slli = $dec_bits ==? 11'b0_001_0010011;
$is_slt = $dec_bits ==? 11'b0_010_0110011;
$is_slti = $dec_bits ==? 11'bx_010_0010011;
$is_sltu = $dec_bits ==? 11'b0_011_0110011;
$is_sltiu = $dec_bits ==? 11'bx_011_0010011;
$is_lui = $dec_bits ==? 11'bx_xxx_0110111;
$is_auipc = $dec_bits ==? 11'bx_xxx_0010111;
$is_jal = $dec_bits ==? 11'bx_xxx_1101111;
$is_jalr = $dec_bits ==? 11'bx_000_1100111;
$is_or = $dec_bits ==? 11'b0_110_0110011;
$is_and = $dec_bits ==? 11'b0_111_0110011;
$is_xor = $dec_bits ==? 11'b0_100_0110011;
$is_xori = $dec_bits ==? 11'bx_100_0010011;
$is_ori = $dec_bits ==? 11'bx_110_0010011;
$is_andi = $dec_bits ==? 11'bx_111_0010011;
$is_srl = $dec_bits ==? 11'b0_101_0110011;
$is_srli = $dec_bits ==? 11'b0_101_0010011;
$is_sra = $dec_bits ==? 11'b1_101_0110011;
$is_srai = $dec_bits ==? 11'b1_101_0010011;
// load-store operations with limitation of naturally aligned (word) addresses (addr %4==0)
$is_load = $dec_bits ==? 11'bx_xxx_0000011; // load (to memory)
// The address computation, rs1 + imm, is the same computation performed by ADDI.
// Since load/store instructions do not otherwise require the ALU, we will utilize the ALU for this computation.
// load (i-instruction): from memory into destination register
// $mem_addr = $rs1 + $imm
// store (sw, sh, sb): operand rs2 ($src_value2) into memory address
// $mem_addr = $rs1 + $imm
$mem_addr_temp[31:0] = $result >> 2; // byte address, memory indexed by 32 bit words
$mem_addr[4:0] = $mem_addr_temp[4:0];
$mem_wr_en = $is_s_instr;
$mem_wr_data[31:0] = $src2_value;
$mem_rd_en = $is_load;
// memory register read/write. update parameters depending on situation
// read
$rd1_index[4:0] = $rs1;
$rd1_en = $is_r_instr || $is_i_instr || $is_s_instr || $is_b_instr || $is_load;
$rd2_index[4:0] = $rs2;
$rd2_en = $is_r_instr || $is_s_instr || $is_b_instr;
// write - data depends on instruction
// register index 0 may never be written to (always init value of zero)
$wr_en = ($is_r_instr || $is_i_instr || $is_u_instr || $is_j_instr || $is_load) && $wr_index != 5'b0;
$wr_index[4:0] = $rd;
$wr_data[31:0] = $is_load ? $ld_data : $result;
// implement alu - https://inst.eecs.berkeley.edu//~cs61c/fa17/img/riscvcard.pdf
//SLTU, SLTI (set if less than, unsigned):
$sltu_rslt[31:0] = {31'b0, $src1_value < $src2_value}; // boolean: 0 or 1
$sltiu_rslt[31:0] = {31'b0, $src1_value < $imm}; // boolean: 0 or 1
// SRA, SRAI (shift right, arithmetic):
// sign-extended src1 (shift). Probably could use ">>>", which does the same as below.
$sext_src1[63:0] = {{32{$src1_value[31]}}, $src1_value};
// 64-bit sign extended results, to be truncated
$sra_rslt[63:0] = $sext_src1 >> $src2_value[4:0]; // 32-bit max shift
$srai_rslt[63:0] = $sext_src1 >> $imm[4:0]; // 32-bit max shift
$result[31:0] = $is_addi ? $src1_value + $imm :
$is_add ? $src1_value + $src2_value :
$is_andi ? $src1_value & $imm :
$is_ori ? $src1_value | $imm :
$is_xori ? $src1_value ^ $imm :
$is_addi ? $src1_value + $imm :
$is_sll ? $src1_value << $src2_value[4:0] : // padded with zero
$is_srl ? $src1_value >> $src2_value[4:0] :
$is_slli ? $src1_value << $imm[5:0] :
$is_srli ? $src1_value >> $imm[5:0] :
$is_and ? $src1_value & $src2_value :
$is_or ? $src1_value | $src2_value :
$is_xor ? $src1_value ^ $src2_value :
$is_sub ? $src1_value - $src2_value :
$is_sltu ? $sltu_rslt :
$is_sltiu ? $sltiu_rslt :
$is_lui ? {$imm[31:12], 12'b0} :
$is_auipc ? $pc + $imm :
$is_jal ? $pc + 32'd4 : // store normally next location in register (e.g. function return address)
$is_jalr ? $pc + 32'd4 : // store normally next location in register (e.g. function return address)
$is_slt ? ( ($src1_value[31] == $src2_value[31]) ?
$sltu_rslt :
{31'b0, $src1_value[31]} ) : // if different sign, just look at sign for < comparison (1 is negative - "overflow")
$is_slti ? ( ($src1_value[31] == $imm[31]) ?
$sltiu_rslt :
{31'b0, $src1_value[31]} ) :
$is_sra ? $sra_rslt[31:0] :
$is_srai ? $srai_rslt[31:0] :
($is_load || $is_s_instr) ? $src1_value + $imm : // calculate load/store memory address
32'b0; // Default
// implement conditional branch instructions
// should branch?
$taken_br = $is_beq ? $src1_value == $src2_value :
$is_bne ? $src1_value != $src2_value :
$is_blt ? ($src1_value < $src2_value) ^ ($src1_value[31] != $src2_value[31]) :
$is_bge ? ($src1_value >= $src2_value) ^ ($src1_value[31] != $src2_value[31]) :
$is_bltu ? $src1_value < $src2_value :
$is_bgeu ? $src1_value >= $src2_value :
$is_jal ? 1 :
$is_jalr ? 1 :
0;
//jal instruction
$jalr_tgt_pc[31:0] = $src1_value + $imm;
// target pc is relative (imm) to current pc
// e.g. jal instruction
$br_tgt_pc[31:0] = $is_jalr ? $jalr_tgt_pc :
$pc + $imm;
// remove log clutter
`BOGUS_USE($rs1 $rs1_valid $rs2 $rs2_valid $rd $rd_valid $funct3 $funct3_valid
$funct7 $funct7_valid $imm_valid $opcode $imm $is_beq $is_bne $is_blt
$is_bge $is_bltu $is_bgeu $is_addi $is_add)
// Assert these to end simulation (before Makerchip cycle limit).
// assert register 30 becomes 1 - test case (next_pc==pc stops the loop)
m4+tb()
*failed = *cyc_cnt > M4_MAX_CYC;
m4+rf(32, 32, $reset, $wr_en, $wr_index, $wr_data, $rd1_en, $rd1_index, $src1_value, $rd2_en, $rd2_index, $src2_value)
m4+dmem(32, 32, $reset, $mem_addr, $mem_wr_en, $mem_wr_data, $mem_rd_en, $ld_data)
m4+cpu_viz()
\SV
endmodule