feat(ECC): add ECC for coupledL2

[Ma-YX]

add optional ECC for tag & data

1. ECC SRAM
   1.1 merge tag/data SRAM with corresponding ECC SRAM
   1.2 For data ECC, currently one cache line(512 bits) is separate into 4 parts to encode/decode, under the request of data-split of data SRAM, which might be changed later

2. ECC error
   2.1 ECC error in L2 will report to beu; and will set corrupt/deny or RespErr correspondingly to L1/L3 (TL or CHI)
   2.2 error from L1/L3 will be kept in L2 directory(meta), no error reporting

3. Data Check & Poison
   3.1 Data Check is only apply to data currently, using odd parity check
   3.2 Poison is simply applied: only data poison & over poison based on ECC

Hint: l2-beu error report datapath might be changed as optional