From 51b7c5f32297b497057ac72f19c4dfa6c775270f Mon Sep 17 00:00:00 2001 From: Tang Haojin Date: Thu, 17 Aug 2023 10:27:38 +0800 Subject: [PATCH] utility: use unified `MemReqSource` (#139) --- Utility | 2 +- src/main/scala/huancun/Common.scala | 19 +------------------ .../scala/huancun/HCCacheParameters.scala | 3 +-- src/main/scala/huancun/SinkA.scala | 1 + src/main/scala/huancun/SinkB.scala | 1 + src/main/scala/huancun/SourceA.scala | 1 + src/main/scala/huancun/SourceC.scala | 2 +- src/main/scala/huancun/TopDownMonitor.scala | 1 + .../scala/huancun/noninclusive/MSHR.scala | 2 +- .../huancun/noninclusive/ProbeHelper.scala | 3 ++- .../scala/huancun/noninclusive/SinkC.scala | 1 + .../huancun/noninclusive/SliceCtrl.scala | 2 +- 12 files changed, 13 insertions(+), 25 deletions(-) diff --git a/Utility b/Utility index 4623edb9..6f49b934 160000 --- a/Utility +++ b/Utility @@ -1 +1 @@ -Subproject commit 4623edb96d03d734f5f93da7796df6654c01413c +Subproject commit 6f49b934d3b51e1a75f406dff0e191f24c952e1b diff --git a/src/main/scala/huancun/Common.scala b/src/main/scala/huancun/Common.scala index a5184793..21ba9137 100644 --- a/src/main/scala/huancun/Common.scala +++ b/src/main/scala/huancun/Common.scala @@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3._ import chisel3.util._ import freechips.rocketchip.util.{BundleMap, UIntToOH1} +import utility.MemReqSource abstract class InnerTask(implicit p: Parameters) extends HuanCunBundle { val sourceId = UInt(sourceIdBits.W) @@ -235,21 +236,3 @@ class PrefetchRecv extends Bundle { val addr_valid = Bool() val l2_pf_en = Bool() } - -// indicates where the memory access request comes from -// a dupliacte of this is in Xiangshan.package and CoupledL2.common -object MemReqSource extends Enumeration { - val NoWhere = Value("NoWhere") - - val CPUInst = Value("CPUInst") - val CPULoadData = Value("CPULoadData") - val CPUStoreData = Value("CPUStoreData") - val CPUAtomicData = Value("CPUAtomicData") - val L1InstPrefetch = Value("L1InstPrefetch") - val L1DataPrefetch = Value("L1DataPrefetch") - val PTW = Value("PTW") - val L2Prefetch = Value("L2Prefetch") - val ReqSourceCount = Value("ReqSourceCount") - - val reqSourceBits = log2Ceil(ReqSourceCount.id) -} diff --git a/src/main/scala/huancun/HCCacheParameters.scala b/src/main/scala/huancun/HCCacheParameters.scala index 3e74bae8..cc80c7a6 100644 --- a/src/main/scala/huancun/HCCacheParameters.scala +++ b/src/main/scala/huancun/HCCacheParameters.scala @@ -26,8 +26,7 @@ import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{TLBufferParams, TLChannelBeatBytes, TLEdgeIn, TLEdgeOut} import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase, ControlKey} import huancun.prefetch.PrefetchParameters -import MemReqSource._ -import utility.ReqSourceKey +import utility.{MemReqSource, ReqSourceKey} case object HCCacheParamsKey extends Field[HCCacheParameters](HCCacheParameters()) diff --git a/src/main/scala/huancun/SinkA.scala b/src/main/scala/huancun/SinkA.scala index d65ec635..5a0857b8 100644 --- a/src/main/scala/huancun/SinkA.scala +++ b/src/main/scala/huancun/SinkA.scala @@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ +import utility.MemReqSource class SinkA(implicit p: Parameters) extends HuanCunModule { val io = IO(new Bundle() { diff --git a/src/main/scala/huancun/SinkB.scala b/src/main/scala/huancun/SinkB.scala index da755b8c..110f806f 100644 --- a/src/main/scala/huancun/SinkB.scala +++ b/src/main/scala/huancun/SinkB.scala @@ -23,6 +23,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ +import utility.MemReqSource class SinkB(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule { val io = IO(new Bundle() { diff --git a/src/main/scala/huancun/SourceA.scala b/src/main/scala/huancun/SourceA.scala index d8d1a2ef..a312292f 100644 --- a/src/main/scala/huancun/SourceA.scala +++ b/src/main/scala/huancun/SourceA.scala @@ -25,6 +25,7 @@ import chisel3.util._ import freechips.rocketchip.tilelink.TLMessages._ import freechips.rocketchip.tilelink._ import huancun.utils.HoldUnless +import utility.MemReqSource class SourceA(edge: TLEdgeOut)(implicit p: Parameters) extends HuanCunModule { val io = IO(new Bundle() { diff --git a/src/main/scala/huancun/SourceC.scala b/src/main/scala/huancun/SourceC.scala index 5acedb96..0ef59d9e 100644 --- a/src/main/scala/huancun/SourceC.scala +++ b/src/main/scala/huancun/SourceC.scala @@ -23,7 +23,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ -import utility.ReqSourceKey +import utility.{MemReqSource, ReqSourceKey} class SourceCPipe(implicit p: Parameters) extends HuanCunBundle { val task = new SourceCReq diff --git a/src/main/scala/huancun/TopDownMonitor.scala b/src/main/scala/huancun/TopDownMonitor.scala index abed9e2f..8bdfee91 100644 --- a/src/main/scala/huancun/TopDownMonitor.scala +++ b/src/main/scala/huancun/TopDownMonitor.scala @@ -5,6 +5,7 @@ import chisel3._ import chisel3.util._ import huancun.noninclusive.DirResult import huancun.utils.{XSPerfAccumulate, XSPerfHistogram} +import utility.MemReqSource class TopDownMonitor()(implicit p: Parameters) extends HuanCunModule { val banks = 1 << bankBits diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala index 5de44645..99c0b1b5 100644 --- a/src/main/scala/huancun/noninclusive/MSHR.scala +++ b/src/main/scala/huancun/noninclusive/MSHR.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.TLHints._ import huancun._ import huancun.utils._ import huancun.MetaData._ -import utility.ParallelMax +import utility.{MemReqSource, ParallelMax} class C_Status(implicit p: Parameters) extends HuanCunBundle { // When C nest A, A needs to know the status of C and tells C to release through to next level diff --git a/src/main/scala/huancun/noninclusive/ProbeHelper.scala b/src/main/scala/huancun/noninclusive/ProbeHelper.scala index 92bd1363..6b9109bb 100644 --- a/src/main/scala/huancun/noninclusive/ProbeHelper.scala +++ b/src/main/scala/huancun/noninclusive/ProbeHelper.scala @@ -4,8 +4,9 @@ import chipsalliance.rocketchip.config.Parameters import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink.{TLMessages, TLPermissions} -import huancun.{HuanCunModule, MSHRRequest, MemReqSource, MetaData} +import huancun.{HuanCunModule, MSHRRequest, MetaData} import huancun.utils.XSPerfAccumulate +import utility.MemReqSource class ProbeHelper(entries: Int = 5, enqDelay: Int = 1)(implicit p: Parameters) extends HuanCunModule with HasClientInfo diff --git a/src/main/scala/huancun/noninclusive/SinkC.scala b/src/main/scala/huancun/noninclusive/SinkC.scala index cc63c51d..1cf5cbbe 100644 --- a/src/main/scala/huancun/noninclusive/SinkC.scala +++ b/src/main/scala/huancun/noninclusive/SinkC.scala @@ -5,6 +5,7 @@ import chisel3.util._ import chipsalliance.rocketchip.config.Parameters import freechips.rocketchip.tilelink.{TLBundleC, TLMessages} import huancun._ +import utility.MemReqSource class SinkC(implicit p: Parameters) extends BaseSinkC { diff --git a/src/main/scala/huancun/noninclusive/SliceCtrl.scala b/src/main/scala/huancun/noninclusive/SliceCtrl.scala index 795ef5c6..99dc723b 100644 --- a/src/main/scala/huancun/noninclusive/SliceCtrl.scala +++ b/src/main/scala/huancun/noninclusive/SliceCtrl.scala @@ -4,7 +4,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3._ import chisel3.util._ import huancun._ -import utility.RegNextN +import utility.{MemReqSource, RegNextN} class SliceCtrl()(implicit p: Parameters) extends HuanCunModule {