From 2710e6d951454040c9a08b5bc3cc0d69d583dbb1 Mon Sep 17 00:00:00 2001 From: linzhida Date: Fri, 29 Nov 2024 18:25:09 +0800 Subject: [PATCH] fix(zacas): check misalign for 16 bytes amocas. --- src/isa/riscv64/instr/rva/amo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/isa/riscv64/instr/rva/amo.c b/src/isa/riscv64/instr/rva/amo.c index dc49a3c90..ca5df6776 100644 --- a/src/isa/riscv64/instr/rva/amo.c +++ b/src/isa/riscv64/instr/rva/amo.c @@ -24,6 +24,7 @@ __attribute__((cold)) def_rtl(amo_slow_path, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src2) { uint32_t funct5 = s->isa.instr.r.funct7 >> 2; int width = s->isa.instr.r.funct3 & 1 ? 8 : 4; + width = BITS(s->isa.instr.r.funct3, 2, 2) == 0 ? width : 16; #ifdef CONFIG_TDATA1_MCONTROL6 trig_action_t action = TRIG_ACTION_NONE; @@ -90,7 +91,6 @@ def_rtl(amo_slow_path, rtlreg_t *dest, const rtlreg_t *src1, const rtlreg_t *src #ifdef CONFIG_RV_ZACAS if (funct5 == 0b00101) { // amocas - width = BITS(s->isa.instr.r.funct3, 2, 2) == 0 ? width : 16; int rd = s->isa.instr.r.rd; int rs2 = s->isa.instr.r.rs2; if (width == 16 && ((rd % 2 == 1) || (rs2 % 2 == 1))) {