remove unnecessary ()

src/main/scala/yunsuan/package.scala

@@ -215,25 +215,25 @@ package object yunsuan {
       val format = Mux(
         (getOpcodeGeneral(fuOpType) === getOpcodeGeneral(vadd_vv) || getOpcodeGeneral(fuOpType) === getOpcodeGeneral(vsub_vv)),
         Mux1H(Seq( // format for vadd/vsub : 00 vvv   01 vvw   10 wvw   11 rvvv
-          (formatOH === "b00".U) -> Cat(Sew, Sew, Sew).asUInt(),
-          (formatOH === "b01".U) -> Cat(Sew, Sew, Sew2).asUInt(),
-          (formatOH === "b10".U) -> Cat(Sew2, Sew, Sew2).asUInt(),
-          (formatOH === "b11".U) -> Cat(Sew, Sew, Sew).asUInt(),
+          (formatOH === "b00".U) -> Cat(Sew, Sew, Sew).asUInt,
+          (formatOH === "b01".U) -> Cat(Sew, Sew, Sew2).asUInt,
+          (formatOH === "b10".U) -> Cat(Sew2, Sew, Sew2).asUInt,
+          (formatOH === "b11".U) -> Cat(Sew, Sew, Sew).asUInt,
         )
         ),
         Mux(
           (getOpcodeGeneral(fuOpType) === getOpcodeGeneral(vzext_vf2)),
           Mux1H(Seq( // format for vext : 00 22v   01 44v   10 88v
-            (formatOH === "b00".U) -> Cat(Sewf2, Sewf2, Sew).asUInt(),
-            (formatOH === "b01".U) -> Cat(Sewf4, Sewf4, Sew).asUInt(),
-            (formatOH === "b10".U) -> Cat(Sewf8, Sewf8, Sew).asUInt(),
+            (formatOH === "b00".U) -> Cat(Sewf2, Sewf2, Sew).asUInt,
+            (formatOH === "b01".U) -> Cat(Sewf4, Sewf4, Sew).asUInt,
+            (formatOH === "b10".U) -> Cat(Sewf8, Sewf8, Sew).asUInt,
           )
           ),
           Mux1H(Seq( // format for general opcode : 00 vvv/0xv   01 vvm   10 mmm   11 wvv
-            (formatOH === "b00".U) -> Cat(Sew, Sew, Sew).asUInt(),
-            (formatOH === "b01".U) -> Cat(Sew, Sew, Mask).asUInt(),
-            (formatOH === "b10".U) -> Cat(Mask, Mask, Mask).asUInt(),
-            (formatOH === "b11".U) -> Cat(Sew2, Sew, Sew).asUInt(),
+            (formatOH === "b00".U) -> Cat(Sew, Sew, Sew).asUInt,
+            (formatOH === "b01".U) -> Cat(Sew, Sew, Mask).asUInt,
+            (formatOH === "b10".U) -> Cat(Mask, Mask, Mask).asUInt,
+            (formatOH === "b11".U) -> Cat(Sew2, Sew, Sew).asUInt,
           )
           )
         )
@@ -322,7 +322,7 @@ package object yunsuan {
     def vmv8r              = "b0_0_0_11_111".U(OpTypeWidth.W) // vmvnr
 
     def getLmulVmvnr(fuOpType: UInt) = Cat(0.U(1.W), fuOpType(4,3))
-    def isVmvnr(fuOpType: UInt) = fuOpType(2,0).andR() && (!fuOpType(7,5).orR())
+    def isVmvnr(fuOpType: UInt) = fuOpType(2,0).andR && (!fuOpType(7,5).orR)
     def getOpcode(fuOpType: UInt) = Cat(0.U(3.W), fuOpType(2,0))
     def getSrcVdType(fuOpType: UInt, sew: UInt) = {
       val isFp = fuOpType(6)
@@ -334,7 +334,7 @@ package object yunsuan {
         !(isvrgatherei16|isvrgatherei16)   -> Cat(isFp ,isFp,  sew(1,0)),
       ))
       val uSew =   Cat(0.U(1.W), 0.U(1.W), sew(1,0))
-      val format = Cat(uSew, srcType1, uSew).asUInt()
+      val format = Cat(uSew, srcType1, uSew).asUInt
       format
     }
     def notNeedSew(fuOpType: UInt) = fuOpType(7)

src/main/scala/yunsuan/util/BitUtils.scala

@@ -164,10 +164,10 @@ object GenMask {
   // generate w/r mask
   def apply(high: Int, low: Int) = {
     require(high > low)
-    (VecInit(List.fill(high+1)(true.B)).asUInt >> low << low).asUInt()
+    (VecInit(List.fill(high+1)(true.B)).asUInt >> low << low).asUInt
   }
   def apply(pos: Int) = {
-    (1.U << pos).asUInt()
+    (1.U << pos).asUInt
   }
 }
 

src/main/scala/yunsuan/vector/VPPU.scala

@@ -83,7 +83,7 @@ class Vfslide1upModule() extends Module(){
   ))
   val result_vtm0 = (body_result_temp & body_mask & active_mask) | (io.in.src1 & body_mask & (~active_mask).asUInt) // vma=0
 
-  val result_vtm1 = (body_result_temp & body_mask & active_mask) | (Fill(128, 1.U(1.W)) & body_mask & (~active_mask).asUInt()) // vma=1
+  val result_vtm1 = (body_result_temp & body_mask & active_mask) | (Fill(128, 1.U(1.W)) & body_mask & (~active_mask).asUInt) // vma=1
 
   val resutl_vtm = Mux(io.in.vma, result_vtm1, result_vtm0)
 
@@ -97,7 +97,7 @@ class Vfslide1upModule() extends Module(){
   ))
 
   val result_vta0 = tail & tail_mask // vta=0
-  val result_vta1 = (Fill(128, 1.U(1.W)) & tail_mask) | (tail & (~tail_mask).asUInt())  // vta=1
+  val result_vta1 = (Fill(128, 1.U(1.W)) & tail_mask) | (tail & (~tail_mask).asUInt)  // vta=1
   val result_vta = Mux(io.in.vta, result_vta1, result_vta0)
 
   // body + tail

src/main/scala/yunsuan/vector/VectorConvert/util/CLZ.scala

@@ -13,7 +13,7 @@ class CLZ(len: Int, zero: Boolean) extends Module {
     val out = Output(UInt(outWidth.W))
   })
 
-  io.out := PriorityEncoder(io.in.asBools().reverse)
+  io.out := PriorityEncoder(io.in.asBools.reverse)
 }
 
 object CLZ {

src/main/scala/yunsuan/vector/VectorConvert/util/Rounding.scala

@@ -16,7 +16,7 @@ class RoundingUnit(val width: Int) extends Module {
     val r_up = Output(Bool())
   })
 
-  val (g, r, s) = (io.in(0).asBool(), io.roundIn, io.stickyIn)
+  val (g, r, s) = (io.in(0).asBool, io.roundIn, io.stickyIn)
   val inexact = r | s
   val r_up = MuxLookup(
     io.rm,
@@ -41,8 +41,8 @@ object RoundingUnit {
     val in_pad = if(in.getWidth < width + 2) padd_tail(in, width + 2) else in
     val rounder = Module(new RoundingUnit(width))
     rounder.io.in := in_pad.head(width)
-    rounder.io.roundIn := in_pad.tail(width).head(1).asBool()
-    rounder.io.stickyIn := in_pad.tail(width + 1).orR()
+    rounder.io.roundIn := in_pad.tail(width).head(1).asBool
+    rounder.io.stickyIn := in_pad.tail(width + 1).orR
     rounder.io.rm := rm
     rounder.io.signIn := sign
     rounder

src/main/scala/yunsuan/vector/VectorConvert/util/ShiftRightJam.scala

@@ -17,9 +17,9 @@ class ShiftRightJam(val len: Int) extends Module {
   val exceed_max_shift = io.shamt > len.U
   val shamt = io.shamt(max_shift_width - 1, 0)
   val sticky_mask =
-    ((1.U << shamt).asUInt() - 1.U)(len - 1, 0) | Fill(len, exceed_max_shift) //移出去那几位的mask
+    ((1.U << shamt).asUInt - 1.U)(len - 1, 0) | Fill(len, exceed_max_shift) //移出去那几位的mask
   io.out := Mux(exceed_max_shift, 0.U, io.in >> io.shamt)
-  io.sticky := (io.in & sticky_mask).orR() //看移出去的这几位是否sticky
+  io.sticky := (io.in & sticky_mask).orR //看移出去的这几位是否sticky
 }
 
 object ShiftRightJam {

src/main/scala/yunsuan/vector/VectorIdiv/SRT16Divint.scala

@@ -213,14 +213,14 @@ class SRT16Divint(bit_width: Int) extends Module {
   val x_enc = Wire(UInt((lzc_w+1).W)) // x value of priority encoder
   val d_enc = Wire(UInt((lzc_w+1).W)) // d value of priority encoder
 
-  x_enc := PriorityEncoder(abs_x_reg(bit_width-1, 0).asBools().reverse)
-  d_enc := PriorityEncoder(abs_d_reg(bit_width-1, 0).asBools().reverse)
+  x_enc := PriorityEncoder(abs_x_reg(bit_width-1, 0).asBools.reverse)
+  d_enc := PriorityEncoder(abs_d_reg(bit_width-1, 0).asBools.reverse)
 
   lzc_x := x_enc(lzc_w - 1, 0)
-  zero_x := ~abs_x_reg.orR()
+  zero_x := ~abs_x_reg.orR
   lzc_d := d_enc(lzc_w - 1, 0)
-  zero_d := ~abs_d_reg.orR()
-  d_is_one := lzc_d(lzc_w - 1, 0).andR()
+  zero_d := ~abs_d_reg.orR
+  d_is_one := lzc_d(lzc_w - 1, 0).andR
   // lzc_diff and pre shifter
   val lzc_diff = Cat(0.U(1.W),lzc_d) - Cat(0.U(1.W),lzc_x) // x d the diffenrence between lzc of x and lzc of d
   val lzc_x_ex = ZeroExt(lzc_x, 6) // Due to the possibility of multiple bit widths, it is necessary to uniformly zero expand lzc for easy storage
@@ -459,7 +459,7 @@ class SRT16Divint(bit_width: Int) extends Module {
   }
 
   // output stage
-  val Bypass_rem_is_zero = !(Bypass_final_rem_reg.orR())
+  val Bypass_rem_is_zero = !(Bypass_final_rem_reg.orR)
   val adjust = Mux(x_sign_reg, (~Bypass_rem_is_zero).asBool & (~Bypass_final_rem_reg(w_width-1)).asBool, Bypass_final_rem_reg(w_width-1)) & !early_finish_q // rem need to adjust
   val out_q_final =
     Mux(adjust, q_B_sign_c_reg, q_A_sign_c_reg)

src/main/scala/yunsuan/vector/VectorIdiv/SRT4Divint8.scala

@@ -106,10 +106,10 @@ class SRT4Divint8(bit_width: Int=8) extends Module {
   x_enc := PriorityEncoder(abs_x.asBools.reverse)
   d_enc := PriorityEncoder(abs_d.asBools.reverse)
   lzc_x := x_enc(lzc_w - 1, 0)
-  zero_x := ~abs_x.orR()
+  zero_x := ~abs_x.orR
   lzc_d := d_enc(lzc_w - 1, 0)
   val lzc_d_reg = RegEnable(lzc_d, stateReg(pre))
-  zero_d := ~abs_d.orR()
+  zero_d := ~abs_d.orR
   // q _sign
   val q_sign = Wire(Bool())
   val q_sign_reg = RegEnable(q_sign, stateReg(pre))
@@ -249,7 +249,7 @@ class SRT4Divint8(bit_width: Int=8) extends Module {
     rem_sign := rem_correct(0).asUInt +rem_correct(1).asUInt
     rem_sign_plus_d := rem_correct(0).asUInt + rem_correct(1).asUInt + const_d_reg(3)
   }
-  val rem_is_zero = !(rem_sign.orR())
+  val rem_is_zero = !(rem_sign.orR)
   val adjust = Mux(x_sign_reg, (~rem_is_zero).asBool &(~rem_sign(w_width - 1)).asBool, rem_sign(w_width -1)) & !early_finish_q
   val out_q_final =
     Mux(adjust, q_B_sign_c, q_A_sign_c)

src/main/scala/yunsuan/vector/VectorIdiv/VectorIdiv.scala

@@ -240,20 +240,20 @@ class VectorIdiv extends Module {
 
   finish := divide_8_finish.reduce(_ & _) & divide_16_finish.reduce(_ & _) & divide_32_finish.reduce(_ & _) & divide_64_finish.reduce(_ & _)
   div_out_d_zero_result :=
-    Mux(sew_hb(0), Cat(divide_64_d_zero.asUInt(), divide_32_d_zero.asUInt(), divide_16_d_zero.asUInt(), divide_8_d_zero.asUInt()),
-      Mux(sew_hb(1), Cat(0.U(8.W), divide_64_d_zero.asUInt(), divide_32_d_zero.asUInt(), divide_16_d_zero.asUInt()),
-        Mux(sew_hb(2), Cat(0.U(12.W),divide_64_d_zero.asUInt(), divide_32_d_zero.asUInt()),
-          Cat(0.U(14.W),divide_64_d_zero.asUInt()))))
+    Mux(sew_hb(0), Cat(divide_64_d_zero.asUInt, divide_32_d_zero.asUInt, divide_16_d_zero.asUInt, divide_8_d_zero.asUInt),
+      Mux(sew_hb(1), Cat(0.U(8.W), divide_64_d_zero.asUInt, divide_32_d_zero.asUInt, divide_16_d_zero.asUInt),
+        Mux(sew_hb(2), Cat(0.U(12.W),divide_64_d_zero.asUInt, divide_32_d_zero.asUInt),
+          Cat(0.U(14.W),divide_64_d_zero.asUInt))))
   div_out_q_result :=
-    Mux(sew_hb(0), Cat(divide_64_I8_q.asUInt(),divide_32_I8_q.asUInt(),divide_16_I8_q.asUInt(), divide_8_q_result.asUInt()),
-      Mux(sew_hb(1),Cat(divide_64_I16_q.asUInt(),divide_32_I16_q.asUInt(),divide_16_I16_q.asUInt()),
-        Mux(sew_hb(2),Cat(divide_64_I32_q.asUInt(),divide_32_I32_q.asUInt()),
-          divide_64_I64_q.asUInt())))
+    Mux(sew_hb(0), Cat(divide_64_I8_q.asUInt,divide_32_I8_q.asUInt,divide_16_I8_q.asUInt, divide_8_q_result.asUInt),
+      Mux(sew_hb(1),Cat(divide_64_I16_q.asUInt,divide_32_I16_q.asUInt,divide_16_I16_q.asUInt),
+        Mux(sew_hb(2),Cat(divide_64_I32_q.asUInt,divide_32_I32_q.asUInt),
+          divide_64_I64_q.asUInt)))
   div_out_rem_result :=
-    Mux(sew_hb(0), Cat(divide_64_I8_rem.asUInt(), divide_32_I8_rem.asUInt(), divide_16_I8_rem.asUInt(), divide_8_rem_result.asUInt()),
-      Mux(sew_hb(1), Cat(divide_64_I16_rem.asUInt(), divide_32_I16_rem.asUInt(), divide_16_I16_rem.asUInt()),
-        Mux(sew_hb(2), Cat(divide_64_I32_rem.asUInt(), divide_32_I32_rem.asUInt()),
-          divide_64_I64_rem.asUInt())))
+    Mux(sew_hb(0), Cat(divide_64_I8_rem.asUInt, divide_32_I8_rem.asUInt, divide_16_I8_rem.asUInt, divide_8_rem_result.asUInt),
+      Mux(sew_hb(1), Cat(divide_64_I16_rem.asUInt, divide_32_I16_rem.asUInt, divide_16_I16_rem.asUInt),
+        Mux(sew_hb(2), Cat(divide_64_I32_rem.asUInt, divide_32_I32_rem.asUInt),
+          divide_64_I64_rem.asUInt)))
 
 
   // output

src/main/scala/yunsuan/vector/VectorIntAdder.scala

@@ -2,7 +2,6 @@ package yunsuan.vector
 
 import chisel3._
 import chisel3.util._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import yunsuan.{OpType, VipuType0, VectorElementFormat}
 
 /**
@@ -359,10 +358,3 @@ class VectorIntAdder() extends Module {
   )
 
 }
-
-object MainAdderTest extends App {
-  println(ChiselStage.emitVerilog(new VectorIntAdder()))
-
-  (new ChiselStage).execute(Array("--emission-options=disableMemRandomization,disableRegisterRandomization",
-    "--target-dir", "./generated/Adder"), Seq(ChiselGeneratorAnnotation(() => new VectorIntAdder())))
-}