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add vfcvt fu #83

Merged
merged 22 commits into from
Sep 25, 2023
Merged

add vfcvt fu #83

merged 22 commits into from
Sep 25, 2023

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wissygh
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@wissygh wissygh commented Sep 24, 2023 •
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co-author @sinceforYy

  1. add vfcvt fu.
  2. suppport vfrsqrt7, vfrec7 and all vector float convert inst in RVV1.0.
  3. note: exclude fuType=0 & fuType =5 in all_fuType. waiting a guy to fix it. https://github.com/wissygh/YunSuan/blob/7c7ae5e559d72dfa09e5ef980d8fa5422799ab9d/src/test/csrc/include/vpu_constant.h#L29

wissygh and others added 21 commits September 24, 2023 00:22
@wissygh
add vcvt
3afd4cf
@wissygh
rtl: refactor estimate7 & fp2fp widen
0181959
@wissygh
rtl: refactor int2fp
efc9bd6
@wissygh
rtl: refactor fp2fp norrow
34ec353
@wissygh
rtl: refactor fp2int
293c0fb
@wissygh
rtl: fix & refactor fp2int
85228d6
@wissygh
rtl: share shift left & reform
297b717
@wissygh
rtl: fix fp2int
25723e8
@sinceforYy @wissygh
add fp16 fp32 and fix golden model
df9e7d1
@wissygh
rtl: share adder, shift right & rounding
d94db46
@wissygh
rtl: refactor unequal logic
f29299c
@wissygh
rtl: clear old logic & add cvtwrapper to gen verilog
5ca9fe9
@sinceforYy @wissygh
refactor fp32 fp2int&int2fp share adder & rounding
d533437
@wissygh
rtl: fix shift right
62e3826
@sinceforYy @wissygh
rtl: cvt fp16 fp32 add reg & no test
a5bddc6
@wissygh
rtl: add reg for cvt64
741828f
@sinceforYy @wissygh
rtl: fix fp32 reg
39d4b19
@sinceforYy @wissygh
rtl: fix cvt fp16 fp_result later 1 clk
1fc76ab
@wissygh
rtl: fix contral logic & clear useless code
b48b806
@wissygh
test: fix vfcvt golden
43336e2
@sinceforYy
rtl:refactor cvt fp16 fp32 reg
7c7ae5e
@wissygh wissygh force-pushed the VCVT branch 2 times, most recently from 8bbdf3b to 43336e2 Compare September 25, 2023 01:18
@xiaofeibao-xjtu xiaofeibao-xjtu merged commit 4b82884 into OpenXiangShan:master Sep 25, 2023
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@xiaofeibao-xjtu xiaofeibao-xjtu xiaofeibao-xjtu approved these changes

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3 participants
@wissygh @xiaofeibao-xjtu @sinceforYy