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fix bug: vfalu test #84

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merged 1 commit into from
Sep 27, 2023
Merged

fix bug: vfalu test #84

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2 changes: 1 addition & 1 deletion src/main/scala/yunsuan/vector/VectorFloatAdder.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -448,7 +448,7 @@ private[vector] class FloatAdderF32WidenF16MixedPipeline(val is_print:Boolean =
val result_fsgnjx = Mux(
res_is_f32,
Cat(fp_bFix.head(1) ^ fp_aFix.head(1), fp_aFix(30, 0)),
Cat(0.U(16.W), Cat(fp_bFix(15) ^ fp_aFix(15), fp_bFix(14, 0)))
Cat(0.U(16.W), Cat(fp_bFix(15) ^ fp_aFix(15), fp_aFix(14, 0)))
)
val result_fclass = Wire(UInt(floatWidth.W))
val result_fmerge = Mux(
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4 changes: 2 additions & 2 deletions src/test/csrc/test_driver.cpp
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Expand Up @@ -371,8 +371,8 @@ void TestDriver::get_random_input() {
input.sew = gen_random_sew();
input.widen = gen_random_widen();
input.src_widen = gen_random_src_widen();
input.is_frs1 = gen_random_is_frs1();
input.is_frs2 = gen_random_is_frs2();
input.is_frs1 = false;
input.is_frs2 = false;
gen_random_vecinfo();
gen_random_uopidx();
gen_input_vperm();
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9 changes: 8 additions & 1 deletion src/test/scala/top/VectorSimTop.scala
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Expand Up @@ -159,7 +159,14 @@ class SimTop() extends VPUTestModule {
vfa.io.frs1 := in.src(1)(0) // VS1(63,0)
vfa.io.fp_b := src2
// TODO: change mask
vfa.io.mask := Cat(src3(48),src3(32),src3(16),src3(0))
val maskTemp = Cat(src3(48),src3(32),src3(16),src3(0))
vfa.io.mask := Mux1H(
Seq(
(sew === 1.U) -> maskTemp,
(sew === 2.U) -> Cat(maskTemp(2),maskTemp(0)),
(sew === 3.U) -> maskTemp(0)
)
)
vfa.io.uop_idx := uop_idx(0)
// TODO: which module to handle dest's original value
vfa.io.round_mode := rm
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