diff memcpy COW optimization

.gitignore

@@ -7,3 +7,5 @@ autom4te.cache/
 .gdb_history
 .#*
 *~
+.vscode
+

difftest/.gitignore

@@ -0,0 +1 @@
+build

difftest/Makefile

@@ -0,0 +1,84 @@
+CC  = clang
+CXX = clang++
+
+GUEST_ISA = riscv64
+BUILD_DIR = $(abspath ./build)
+TARGET    = $(BUILD_DIR)/$(GUEST_ISA)-spike-so
+
+# Dependencies for building Spike
+SPIKE_PATH     = $(abspath ..)
+SPIKE_TARGET   = $(BUILD_DIR)/spike
+SPIKE_MAKEFILE = $(BUILD_DIR)/Makefile
+
+SPIKE_CFLAGS    = -O3 -DDIFFTEST
+SPIKE_CXXFLAGS  = -O3 -DDIFFTEST -Wno-c99-designator
+SPIKE_LDFLAGS   =
+
+ifneq ($(CPU),)
+SPIKE_CFLAGS   += -DCPU_$(CPU)
+SPIKE_CXXFLAGS += -DCPU_$(CPU)
+endif
+
+ifeq ($(DEBUG),)
+SPIKE_CFLAGS   += -g0
+SPIKE_CXXFLAGS += -g0
+endif
+
+ifeq ($(SANCOV),1)
+SPIKE_CFLAGS   += -fsanitize-coverage=trace-pc-guard -fsanitize-coverage=pc-table -g
+SPIKE_CXXFLAGS += -fsanitize-coverage=trace-pc-guard -fsanitize-coverage=pc-table -g
+SPIKE_LDFLAGS  += -fsanitize-coverage=trace-pc-guard -fsanitize-coverage=pc-table -g
+endif
+
+CONFIGURE_FLAGS = -q CC=$(CC) CXX=$(CXX)         \
+    --with-boost=no	--with-boost-asio=no --with-boost-regex=no \
+    CFLAGS="$(SPIKE_CFLAGS)" CXXFLAGS="$(SPIKE_CXXFLAGS)"      \
+    LDFLAGS="$(SPIKE_LDFLAGS)"
+
+SPIKE_INCS = fesvr riscv disasm customext fdt softfloat spike_main spike_dasm
+INC_PATH   = -I$(SPIKE_PATH) -I$(BUILD_DIR) $(addprefix -I$(SPIKE_PATH)/, $(SPIKE_INCS))
+
+SPIKE_SRCS = $(shell find $(SPIKE_PATH) -maxdepth 2 -name '*.cc') \
+             $(shell find $(SPIKE_PATH) -maxdepth 2 -name '*.h')
+SPIKE_LIBS = libriscv.a libdisasm.a libsoftfloat.a libfesvr.a libfdt.a
+INC_LIBS   = $(addprefix $(BUILD_DIR)/, $(SPIKE_LIBS))
+
+# We need some utilities from spike
+CXX_UTILS = $(BUILD_DIR)/difftest_utils.cc
+
+$(CXX_UTILS): $(SPIKE_PATH)/spike_main/spike.cc
+	cp $< $(CXX_UTILS)
+	@sed -i 's/static //g' $@
+	@sed -i 's/int main/static int spike_main/g' $@
+
+# Dependencies for building the difftest dynamic library
+DIFFTEST_SOURCES = $(shell find . -maxdepth 1 -name '*.cc') $(CXX_UTILS)
+DIFFTEST_HEADERS = $(shell find . -maxdepth 1 -name '*.h')
+CXXFLAGS = $(SPIKE_CXXFLAGS) --std=c++17 -shared -fPIC
+ifneq ($(SANCOV),1)
+CXXFLAGS += -flto
+endif
+
+ifneq ($(DEBUG),)
+CONFIGURE_FLAGS += --enable-commitlog
+CXXFLAGS += -DDIFFTEST_LOG_FILE=\"$(NOOP_HOME)/build/spike.log\"
+endif
+
+$(BUILD_DIR):
+	mkdir -p $(BUILD_DIR)
+
+$(SPIKE_MAKEFILE): $(SPIKE_PATH)/configure | $(BUILD_DIR)
+	cd $(@D) && $(abspath $(SPIKE_PATH))/configure $(CONFIGURE_FLAGS)
+
+$(SPIKE_TARGET): $(SPIKE_MAKEFILE) $(SPIKE_SRCS)
+	$(MAKE) -s -C $(BUILD_DIR)
+
+$(TARGET): $(SPIKE_TARGET) $(DIFFTEST_SOURCES) $(DIFFTEST_HEADERS) | $(BUILD_DIR)
+	$(CXX) $(CXXFLAGS) $(INC_PATH) $(DIFFTEST_SOURCES) $(INC_LIBS) -o $@
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+.DEFAULT_GOAL = $(TARGET)
+
+.PHONY: clean

difftest/README.md

@@ -0,0 +1,31 @@
+# Spike as a Reference Model
+
+The Spike RISC-V ISA simulator can be a golden reference model for CPU co-simulation as well.
+This directory contains the wrapper files for using Spike as the REF used in DiffTest.
+
+## Supported CPUs
+
+RISC-V allows diverse implementation-specific behaviors as long as they don't violate the ISA.
+Therefore, to co-simulate Spike, one of the RISC-V implementations, with another implementation
+without errors, we have to align their behaviors on the undefined or design-specific regions.
+
+Currently we are supporting CPUs including:
+- [XiangShan](https://github.com/OpenXiangShan/XiangShan)
+- [NutShell](https://github.com/OSCPU/NutShell)
+- [Rocket Chip](https://github.com/chipsalliance/rocket-chip)
+
+## How to Compile
+
+To compile the Spike into a dynamic library for co-simulation via DiffTest, run:
+
+```
+cd riscv-isa-sim/difftest
+make CPU=XIANGSHAN -jN
+```
+
+Replace `XIANGSHAN` with `ROCKET` or `NUTSHELL` for co-simulation with Rocket or NutShell.
+
+## Coverage Instrumentation with LLVM
+
+Add `SANCOV=1` to the `make` command to instrument the source code with LLVM coverage.
+This enables fuzzers to be guided with branch coverage feedback from a golden RISC-V model.

difftest/difftest-def.h

@@ -0,0 +1,46 @@
+#ifndef __DIFFTEST_DEF_H
+#define __DIFFTEST_DEF_H
+
+#if defined(CPU_NUTSHELL)
+#elif defined(CPU_XIANGSHAN)
+#elif defined(CPU_ROCKET_CHIP)
+#else
+// This is the default CPU
+#define CPU_NUTSHELL
+#endif
+
+#if defined(CPU_XIANGSHAN) || defined(CPU_ROCKET_CHIP)
+#define CONFIG_DIFF_FPU
+#endif
+
+#if defined(CPU_XIANGSHAN)
+#define CONFIG_DIFF_DEBUG_MODE
+// #define CONFIG_DIFF_RVV  // Default off
+#endif
+
+#if defined(CPU_NUTSHELL)
+#define CONFIG_DIFF_ISA_STRING "rv64imaczicsr_zifencei"
+#define CONFIG_MEMORY_SIZE     (2 * 1024 * 1024 * 1024UL)
+#define CONFIG_FLASH_BASE      0x40000000UL
+#define CONFIG_FLASH_SIZE      0x1000UL
+#define CONFIG_PMP_NUM         0
+#elif defined(CPU_XIANGSHAN)
+    #if defined(CONFIG_DIFF_RVV)
+    #define CONFIG_DIFF_ISA_STRING "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval"
+    #else
+    #define CONFIG_DIFF_ISA_STRING "RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval"
+    #endif // CONFIG_DIFF_RVV
+#define CONFIG_MEMORY_SIZE     (16 * 1024 * 1024 * 1024UL)
+#define CONFIG_FLASH_BASE      0x10000000UL
+#define CONFIG_FLASH_SIZE      0x100000UL
+#define CONFIG_PMP_NUM         16
+#define CONFIG_PMP_GRAN        12
+#elif defined(CPU_ROCKET_CHIP)
+#define CONFIG_DIFF_ISA_STRING "rv64imafdczicsr_zifencei_zihpm_zicntr"
+#define CONFIG_MEMORY_SIZE     (2 * 1024 * 1024 * 1024UL)
+#define CONFIG_FLASH_BASE      0x10000000UL
+#define CONFIG_FLASH_SIZE      0x10000UL
+#define CONFIG_PMP_NUM         0
+#endif
+
+#endif