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I have a test load of an hx8k part that nextnpr apparently is miss-placing a signal.
To make sure it is not old tools I rebuilt the tools
Yosys 0.48+40 (git sha1 281e474d4, x86_64-pc-linux-gnu-g++ 14.2.1_p20241116 -fPIC -O3)
icestorm 71907709498b80176ead1ccb1e3424ded9e50f5c
nextpnr f01465f
I have two builds, one a full build that places properly and the test build that does not. Both use the same pcf file.
the snippet of interest from the routing log is here :
Info: Packing PLLs..
Info: Input frequency of PLL 'p1.uut' is constrained to 12.0 MHz
Info: VCO frequency of PLL 'p1.uut' is constrained to 588.2 MHz
Info: PLL 'p1.uut' has LOCK output, need to pass all outputs via LUT
Info: constrained 'ds_SB_DFFESR_Q_11_D_SB_LUT4_O_LC' to X1/Y32/lc0
Info: constrained 'pll_locked_buf_SB_DFF_Q_3_DFFLC' to X1/Y32/lc1
Info: Promoting globals..
Info: promoting dsel_true_SB_LUT4_I2_I3[0] [reset] (fanout 142)
Info: promoting clk100 (fanout 114)
Info: promoting clk$SB_IO_IN (fanout 82)
Info: promoting pps_SB_DFFSR_Q_D_SB_LUT4_I3_O [reset] (fanout 24)
Info: promoting dsel_true_SB_LUT4_I2_I3_SB_LUT4_I2_O[1] [cen] (fanout 16)
Info: Constraining chains...
Info: 9 LCs used to legalise carry chains.
Info: Checksum: 0x0864c37f
bebc74d has all the files required to reproduce the problem - they are in the directory FPGA_IO_test. Removing the routing of pll_locked line PDP8e.v line 158 causes the problem to disappear.
I have a test load of an hx8k part that nextnpr apparently is miss-placing a signal.
To make sure it is not old tools I rebuilt the tools
Yosys 0.48+40 (git sha1 281e474d4, x86_64-pc-linux-gnu-g++ 14.2.1_p20241116 -fPIC -O3)
icestorm 71907709498b80176ead1ccb1e3424ded9e50f5c
nextpnr f01465f
I have two builds, one a full build that places properly and the test build that does not. Both use the same pcf file.
the snippet of interest from the routing log is here :
Info: Packing PLLs..
Info: Input frequency of PLL 'p1.uut' is constrained to 12.0 MHz
Info: VCO frequency of PLL 'p1.uut' is constrained to 588.2 MHz
Info: PLL 'p1.uut' has LOCK output, need to pass all outputs via LUT
Info: constrained 'ds_SB_DFFESR_Q_11_D_SB_LUT4_O_LC' to X1/Y32/lc0
Info: constrained 'pll_locked_buf_SB_DFF_Q_3_DFFLC' to X1/Y32/lc1
Info: Promoting globals..
Info: promoting dsel_true_SB_LUT4_I2_I3[0] [reset] (fanout 142)
Info: promoting clk100 (fanout 114)
Info: promoting clk$SB_IO_IN (fanout 82)
Info: promoting pps_SB_DFFSR_Q_D_SB_LUT4_I3_O [reset] (fanout 24)
Info: promoting dsel_true_SB_LUT4_I2_I3_SB_LUT4_I2_O[1] [cen] (fanout 16)
Info: Constraining chains...
Info: 9 LCs used to legalise carry chains.
Info: Checksum: 0x0864c37f
Info: Device utilisation:
Info: ICESTORM_LC: 357/ 7680 4%
Info: ICESTORM_RAM: 0/ 32 0%
Info: SB_IO: 60/ 256 23%
Info: SB_GB: 5/ 8 62%
Info: ICESTORM_PLL: 1/ 2 50%
Info: SB_WARMBOOT: 0/ 1 0%
ERROR: Bel 'X1/Y32/lc0' of type 'ICESTORM_LC' is not valid for cell 'ds_SB_DFFESR _Q_11_D_SB_LUT4_O_LC' of type 'ICESTORM_LC'
4 warnings, 1 error
On the good build, pll_locked_buf is assigned to Bel`X1/Y32/lc0 (not lc1 as above)
The test app, Makefile and pcf can be uploaded if they would be of help
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