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0172-2023-11-04.md

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4 Nov 2023

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Some fixes to raybox-zero-caravel

I found after running a two-frame make coco_test_gl that things became 'unknown'.

After working on a bunch of corrections and reworking the POV SPI stuff, I think I put it down to some registers that were not initialised at reset, as well as maybe some ambiguous states in how the POV SPI (and also spi_registers) works??

I think I've got it working now.

So far I've tested in Verilator (make csr) and on the FPGA. I tested most of vec/regs on the FPGA, plus demo mode 'inc' behaviour, and it seemed fine. I tested fewer (but enough?) of the vec/regs and demo 'inc' behaviour in Verilator, and they too seemed fine.

I also think I've got the coco_test_gl tests giving consistent results.

These are the tests I'm running on coco_test_gl:

  • i_inc_px/y disabled (00): Should have consistent vec overlay -- would allow POV SPI to take over if desired
    • If this FAILS (it didn't):
      • Stop the sim
      • Load VCD
      • Start next test
      • Work out: Is the problem due to vec (POV), reg, or both?
      • Inspect POV state -- use X5.gtkw? Make X6?
  • i_inc_px/y enabled: Should show difference in vec overlay
    • This should weed out reg SPI errors, because it disables POV.
    • If there is STILL a failure, either POV-disable is not working, or regs are bad.
    • NOTE: It worked
  • Repeat with registered outputs (tests above were first done without)

If it works out OK, tidy up (reset) state and contract lines in POV to make it more readable.

While waiting for tests:

  • Write tests that actually send a new POV via LA SPI. NOTE: SOC might be too slow to do this within 1 frame! Or sometimes it executes too fast (when cached).
  • Design use of IO[11] as clock: Put it in a smarter position (top-right?); get rid of user_clock2 -- Don't forget user_defines for it, too. No longer analog! Make sure OEB is set correctly (and not conflicting with Ellen)
  • Remove i_test_wb_clk_i and replace its gpout1:alt with something else
  • Try analog part:
    • Harald Pretl custom cell?
    • Custom GDS in TT05? -- Suffers no nice output. Look at Harald's TT05 submission
    • Full custom GDS drop-in -- Power/LVS is confusing
    • Analog GDS portion to add to UPW -- borrow from Pawel
  • Check latest hardens after code fixes (and reports)
  • Do final test run on FPGA

Note to Pawel to bring in new version:

  • top_ew_algofoogle.v (and GL netlist?)
  • tests
  • GDS/LEF, etc
  • updated snippet
  • user_defines:
    • Change this: 
      `define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_ANALOG         // Ellen: bandgap (analog[4])
    • To this: 
      `define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL   // Anton: anton_clock_in

Howdy Pawel, I've updated my design. Ellen has assigned me an extra pin (DIGITAL[11]), and I've followed her suggestion to make it my main clock source.

For this, user_defines will need to be updated to change this pin from ANALOG to INPUT_NOPULL, i.e. change this:

`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_ANALOG         // Ellen: bandgap (analog[4])

To this:

`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_USER_STD_INPUT_NOPULL   // Anton: anton_clock_in

I've got an updated snippet too, in the usual place: https://github.com/algofoogle/raybox-zero/blob/ew/src/rtl/ew_caravel_snippets/SNIPPET2_ShareIns.v

A couple of top_ew_algofoogle ports have also changed: https://github.com/algofoogle/raybox-zero/blob/ew/src/rtl/top_ew_algofoogle.v

All the other files, as usual, can be found in my caravel repo: https://github.com/algofoogle/raybox-zero-caravel

NOTE: New EW combined submission repo: https://github.com/embelon/Silicon_Contact_3GBT

Next steps