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0219-2024-10-07.md

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7 Oct 2024

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0218-2024-10-05.md 0220-2024-10-11.md

GFMPW-1 bring-up (continued)

I've put test firmware into subdirectories of algofoogle-multi-caravel/firmware/.

These subdirectories (e.g. ./basic_blink/) should be copied into a clone of caravel_board, nested within /firmware/gf180/.

You can then make and flash one to your Caravel board by doing (say):

cd firmware/gf180/basic_blink
make clean flash

Tests done:

  • mux_test design 13: MUX_DESIGN=13 make clean flash:
    • Verified IO[31:16] outputs 0101010110101010
  • mux_test design 14: MUX_DESIGN=14 make clean flash:
    • Verified IO[31:16] outputs 1010101101010101
  • mux_test design 11: MUX_DESIGN=11 make clean flash:
    • Verified that IO[30:24] follow IO[37:31]
    • Verified that IO[23:8] follow la_data_in[23:8]
  • mux_test design 12: MUX_DESIGN=12 make clean flash:
    • Measured IO[31:8]: 
      31:30   r_mux_io5_reset_enb     zz          (Verilog error: configured as INPUTS)
29      io5_reset               z           (Verilog error: configured as INPUT)
28      sys_reset               0           sys_reset not currently asserted (disabled anyway)
27:26   r_mux_sel0              00          ...
25:24   r_mux_sel1              00          ...
23:22   r_mux_sel2              11          ...
21:20   r_mux_sel3              11          ...Select design 1100 (12)
19:18   r_mux_sys_reset_enb     11          Disable wb_rst_i
17:16   r_mux_auto_reset_enb    00          Enable "auto-reset non-selected designs"
15:8    i_design_reset          11111111    Manually hold all designs in reset anyway
    • There's an ERROR in the Verilog: only top 6 bits should be configured as inputs, but 9 bits are, so IO[31:29] are INPUTS instead of outputs. This doesn't affect the operation of the mux or overall chip... it just affects this one test.
    • NOTE: We could probably work around this by writing firmware to override IO[31:29] from BIDIR to OUTPUT.
  • trzf_test: make clean flash:
    • gpout[2:0] present clk,clk/2,clk/4 as expected.
    • GPIO[9:8] seems to present VSYNC,HSYNC as expected.
    • GPIO[15:10] look like they could be expected RGB data.
    • GPIO[16] looks like expected texture CSB signal.
    • GPIO[17] looks like texture SCLK.
    • GPIO[18] appears to have a valid QSPI read command and address pattern.

GPIO maps

GPIO trzf/trzf2 IO CPUy IO
6 (Unused) I rst I
7 (Unused) I ext_int I
8 o_hsync O data_bus[0] I
9 o_vsync O data_bus[1] I
10 o_rgb[0] O data_bus[2] I
11 o_rgb[1] O data_bus[3] I
12 o_rgb[2] O data_bus[4] I
13 o_rgb[3] O data_bus[5] I
14 o_rgb[4] O data_bus[6] I
15 o_rgb[5] O data_bus[7] I
16 o_tex_csb O p0_io[0] IO
17 o_tex_sclk O p0_io[1] IO
18 io_tex_io[0] IO p0_io[2] IO
19 i_tex_in[1] I p0_io[3] IO
20 i_tex_in[2] I p0_io[4] IO
21 i_tex_in[3] I p0_io[5] IO
22 i_vec_csb I p0_io[6] IO
23 i_vec_sclk I p0_io[7] IO
24 i_vec_mosi I p1_io[0] IO
25 i_reg_csb I p1_io[1] IO
26 i_reg_sclk I p1_io[2] IO
27 i_reg_mosi I p1_io[3] IO
28 i_debug_vec I addr_bus[0] O
29 i_debug_map I addr_bus[1] O
30 i_debug_trace I addr_bus[2] O
31 i_reg_outs_enb I addr_bus[3] O
32 i_mode0/inc_px I addr_bus[4] O
33 i_mode1/inc_py I addr_bus[5] O
34 i_mode2/gen_tex I addr_bus[6] O
35 o_gpout[0] O addr_bus[7] O
36 o_gpout[1] O addr_bus[8] O
37 o_gpout[2] O addr_bus[9] O

Control board options

I'd like a board that can be used to help test my GFMPW-1 chips, i.e. act as a universal testbench.

Requirements are:

  • Minimum of 32 GPIOs, but ideally at least 36: 32 are used by Diego's design, 2 are for a UART interface to a host PC, and ideally we'd also control Caravel's CLK and RESETb.
  • All GPIOs should be at least 5-5.5V-tolerant, but ideally natively 5V.
  • At least a 10MHz clock, but 40-50MHz would be better.
  • Ideally should be PC-controlled, though it's acceptable to just be driven by its own firmware.

Options include:

  • Arduino Mega 2560 (based on ATMega2560):
    • 5-volt native
    • 54 GPIOs
    • 16MHz
    • PWM & UART
    • Interrupts
    • 1x SPI
  • Older Arduino Mega -- basically the same?? Slightly fewer peripherals/storage?
  • Android Open ADK (Accessories Development Kit) -- based on Arduino Mega 2560?
  • XC9572XL, or 144/288 variants? Available in larger pin counts. 5V-tolerant (but not native).
  • STM32F103
    • STM32F103R* (64-pin) looks like it has 31 5V-tolerant GPIOs
    • STM32F103V* (100-pin) looks like it has 60.
    • STM32F103Z* (144-pin) looks like it has 89.
  • Anything with suitable bi-directional level shifters, inc. OBLS
  • 2 or more MCUs linked?
  • 89C52 has 32 GPIOs
  • These (for example) all have internal Flash and run at up to 5.5V:
    Part ISA MHz Price IO count
    PIC18F46Q10T-I/PT ? 64MHz $2.21 36
    PIC18F55Q43-I/PT ? 64MHz $2.65 44
    CY8C4246AZI-M443 ARM Cortex-M0 48MHz $2.25 38
    NUC029LAN ARM Cortex-M0 72MHz $2.44 40
    NUC123SD4AN0 ARM Cortex-M0 72MHz $3.74 47

More testing of GFMPW-1...

For some notes on testing and actually seeing raybox-zero (top_raybox_zero_fsm, or just "trzf") running on GFMPW-1, see the next journal: 0220