From ca0629373b82b128dab64134fea327a256c4be62 Mon Sep 17 00:00:00 2001 From: Igor Wodiany Date: Thu, 6 Jun 2024 14:19:25 +0100 Subject: [PATCH] Move PIE from submodule into MAMBO repository (#121) * Remove pie submodule from git * Add PIE as part of MAMBO repository Original repository at https://github.com/beehive-lab/pie --- .gitmodules | 3 - pie | 1 - pie/.gitignore | 3 + pie/LICENSE | 202 +++++++++++ pie/a64.txt | 113 ++++++ pie/arm.txt | 476 ++++++++++++++++++++++++ pie/generate_common.rb | 132 +++++++ pie/generate_decoder.rb | 291 +++++++++++++++ pie/generate_encoder.rb | 117 ++++++ pie/generate_field-decoder.rb | 102 ++++++ pie/makefile | 44 +++ pie/riscv.txt | 291 +++++++++++++++ pie/thumb.txt | 665 ++++++++++++++++++++++++++++++++++ 13 files changed, 2436 insertions(+), 4 deletions(-) delete mode 160000 pie create mode 100644 pie/.gitignore create mode 100644 pie/LICENSE create mode 100644 pie/a64.txt create mode 100644 pie/arm.txt create mode 100644 pie/generate_common.rb create mode 100644 pie/generate_decoder.rb create mode 100644 pie/generate_encoder.rb create mode 100644 pie/generate_field-decoder.rb create mode 100644 pie/makefile create mode 100644 pie/riscv.txt create mode 100644 pie/thumb.txt diff --git a/.gitmodules b/.gitmodules index 8eb36960..e69de29b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +0,0 @@ -[submodule "pie"] - path = pie - url = https://github.com/beehive-lab/pie.git diff --git a/pie b/pie deleted file mode 160000 index 981cf92a..00000000 --- a/pie +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 981cf92a8f1156be2a188ed77d1667039c64709b diff --git a/pie/.gitignore b/pie/.gitignore new file mode 100644 index 00000000..71c67bdc --- /dev/null +++ b/pie/.gitignore @@ -0,0 +1,3 @@ +*.c +*.h +*.o diff --git a/pie/LICENSE b/pie/LICENSE new file mode 100644 index 00000000..d6456956 --- /dev/null +++ b/pie/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/pie/a64.txt b/pie/a64.txt new file mode 100644 index 00000000..d290514c --- /dev/null +++ b/pie/a64.txt @@ -0,0 +1,113 @@ +# +# This file is part of PIE, an instruction encoder / decoder generator: +# https://github.com/beehive-lab/pie +# +# Copyright 2014-2016 Amanieu d'Antras +# Copyright 2015-2016 Guillermo Callaghan +# Copyright 2011-2016 Cosmin Gorgovan +# Copyright 2017-2021 The University of Manchester +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +CBZ_CBNZ a011010b cccccccc cccccccc cccddddd, a:sf, b:op, c:imm19, d:rt +B_cond 01010100 aaaaaaaa aaaaaaaa aaa0bbbb, a:imm19, b:cond +SVC 11010100 000aaaaa aaaaaaaa aaa00001, a:imm16 +HVC 11010100 000aaaaa aaaaaaaa aaa00010, a:imm16 +SMC 11010100 000aaaaa aaaaaaaa aaa00011, a:imm16 +BRK 11010100 001aaaaa aaaaaaaa aaa00000, a:imm16 +HLT 11010100 010aaaaa aaaaaaaa aaa00000, a:imm16 +DCPS1 11010100 101aaaaa aaaaaaaa aaa00001, a:imm16 +DCPS2 11010100 101aaaaa aaaaaaaa aaa00010, a:imm16 +DCPS3 11010100 101aaaaa aaaaaaaa aaa00011, a:imm16 +MSR_immed 11010101 00000aaa 0100bbbb ccc11111, a:op1, b:crm, c:op2 +HINT 11010101 00000011 0010aaaa bbb11111, a:crm, b:op2 +CLREX 11010101 00000011 0011aaaa 01011111, a:crm +DSB 11010101 00000011 0011aaaa 10011111, a:crm +DMB 11010101 00000011 0011aaaa 10111111, a:crm +ISB 11010101 00000011 0011aaaa 11011111, a:crm +SYS 11010101 00001aaa bbbbcccc dddeeeee, a:op1, b:crn, c:crm, d:op2, e:rt +MRS_MSR_reg 11010101 00a1bccc ddddeeee fffggggg, a:r, b:o0, c:op1, d:crn, e:crm, f:op2, g:rt +SYSL 11010101 00101aaa bbbbcccc dddeeeee, a:op1, b:crn, c:crm, d:op2, e:rt +TBZ_TBNZ a011011b cccccddd dddddddd dddeeeee, a:b5, b:op, c:b40, d:imm14, e:rt +B_BL a00101bb bbbbbbbb bbbbbbbb bbbbbbbb, a:op, b:imm26 +BR 11010110 00011111 000000aa aaa00000, a:rn +BLR 11010110 00111111 000000aa aaa00000, a:rn +RET 11010110 01011111 000000aa aaa00000, a:rn +ERET 11010110 10011111 00000011 11100000 +DRPS 11010110 10111111 00000011 11100000 +LDX_STX aa001000 bcdeeeee fggggghh hhhiiiii, a:size, b:o2, c:l, d:o1, e:rs, f:o0, g:rt2, h:rn, i:rt +LDR_lit aa011b00 cccccccc cccccccc cccddddd, a:opc, b:v, c:imm19, d:rt +LDP_STP aa101b0c cdeeeeee efffffgg ggghhhhh, a:opc, b:v, c:type, d:l, e:imm7, f:rt2, g:rn, h:rt +LDR_STR_immed aa111b00 cc0ddddd ddddeeff fffggggg, a:size, b:v, c:opc, d:imm9, e:type, f:rn, g:rt +LDR_STR_reg aa111b00 cc1ddddd eeef10gg ggghhhhh, a:size, b:v, c:opc, d:rm, e:option, f:s, g:rn, h:rt +LDR_STR_unsigned_immed aa111b01 ccdddddd ddddddee eeefffff, a:size, b:v, c:opc, d:imm12, e:rn, f:rt +LDx_STx_multiple 0a001100 0b000000 ccccddee eeefffff, a:q, b:l, c:opcode, d:size, e:rn, f:rt +LDx_STx_multiple_post 0a001100 1b0ccccc ddddeeff fffggggg, a:q, b:l, c:rm, d:opcode, e:size, f:rn, g:rt +LDx_STx_single 0a001101 0bc00000 dddeffgg ggghhhhh, a:q, b:l, c:r, d:opcode, e:s, f:size, g:rn, h:rt +LDx_STx_single_post 0a001101 1bcddddd eeefgghh hhhiiiii, a:q, b:l, c:r, d:rm, e:opcode, f:s, g:size, h:rn, i:rt +LDADD aa111000 bc1ddddd 000000ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDCLR aa111000 bc1ddddd 000100ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDEOR aa111000 bc1ddddd 001000ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDSMAX aa111000 bc1ddddd 010000ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDSMIN aa111000 bc1ddddd 010100ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDUMAX aa111000 bc1ddddd 011000ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDUMIN aa111000 bc1ddddd 011100ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +LDSET aa111000 bc1ddddd 001100ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +SWP aa111000 bc1ddddd 100000ee eeefffff, a:size, b:a, c:r, d:rs, e:rn, f:rt +ADD_SUB_immed abc10001 ddeeeeee eeeeeeff fffggggg, a:sf, b:op, c:s, d:shift, e:imm12, f:rn, g:rd +BFM abb10011 0cdddddd eeeeeeff fffggggg, a:sf, b:opc, c:n, d:immr, e:imms, f:rn, g:rd +EXTR a0010011 1b0ccccc ddddddee eeefffff, a:sf, b:n, c:rm, d:imms, e:rn, f:rd +logical_immed abb10010 0cdddddd eeeeeeff fffggggg, a:sf, b:opc, c:n, d:immr, e:imms, f:rn, g:rd +MOV_wide abb10010 1ccddddd dddddddd dddeeeee, a:sf, b:opc, c:hw, d:imm16, e:rd +ADR abb10000 cccccccc cccccccc cccddddd, a:op, b:immlo, c:immhi, d:rd +ADD_SUB_ext_reg abc01011 001ddddd eeefffgg ggghhhhh, a:sf, b:op, c:s, d:rm, e:option, f:imm3, g:rn, h:rd +ADD_SUB_shift_reg abc01011 dd0eeeee ffffffgg ggghhhhh, a:sf, b:op, c:s, d:shift, e:rm, f:imm6, g:rn, h:rd +ADC_SBC abc11010 000ddddd 000000ee eeefffff, a:sf, b:op, c:s, d:rm, e:rn, f:rd +CCMP_CCMN_immed ab111010 010ccccc dddd10ee eee0ffff, a:sf, b:op, c:imm5, d:cond, e:rn, f:nzcv +CCMP_CCMN_reg ab111010 010ccccc dddd00ee eee0ffff, a:sf, b:op, c:rm, d:cond, e:rn, f:nzcv +cond_select ab011010 100ccccc ddddeeff fffggggg, a:sf, b:op, c:rm, d:cond, e:op2, f:rn, g:rd +data_proc_reg1 a1011010 11000000 bbbbbbcc cccddddd, a:sf, b:opcode, c:rn, d:rd +data_proc_reg2 a0011010 110bbbbb ccccccdd dddeeeee, a:sf, b:rm, c:opcode, d:rn, e:rd +data_proc_reg3 a0011011 bbbccccc deeeeeff fffggggg, a:sf, b:op31, c:rm, d:o0, e:Ra, f:rn, g:rd +logical_reg abb01010 ccdeeeee ffffffgg ggghhhhh, a:sf, b:opc, c:shift, d:n, e:rm, f:imm6, g:rn, h:rd +simd_across_lane 0ab01110 cc11000d dddd10ee eeefffff, a:q, b:u, c:size, d:opcode, e:rn, f:rd +simd_copy 0ab01110 000ccccc 0dddd1ee eeefffff, a:q, b:op, c:imm5, d:imm4, e:rn, f:rd +simd_extract 0a101110 000bbbbb 0cccc0dd dddeeeee, a:q, b:rm, c:imm4, d:rn, e:rd +simd_modified_immed 0ab01111 00000ccc dddd01ee eeefffff, a:q, b:op, c:abc, d:cmode, e:defgh, f:rd +simd_permute 0a001110 bb0ccccc 0ddd10ee eeefffff, a:q, b:size, c:rm, d:opcode, e:rn, f:rd +simd_scalar_copy 01011110 000aaaaa 000001bb bbbccccc, a:imm5, b:rn, c:rd +simd_scalar_pairwise 01a11110 bb11000c cccc10dd dddeeeee, a:u, b:size, c:opcode, d:rn, e:rd +simd_scalar_shift_immed 01a11111 0bbbbccc ddddd1ee eeefffff, a:u, b:immh, c:immb, d:opcode, e:rn, f:rd +simd_scalar_three_diff 01a11110 bb1ccccc dddd00ee eeefffff, a:u, b:size, c:rm, d:opcode, e:rn, f:rd +simd_scalar_three_same 01a11110 bb1ccccc ddddd1ee eeefffff, a:u, b:size, c:rm, d:opcode, e:rn, f:rd +simd_scalar_two_reg 01a11110 bb10000c cccc10dd dddeeeee, a:u, b:size, c:opcode, d:rn, e:rd +simd_scalar_x_indexed 01a11111 bbcdeeee ffffg0hh hhhiiiii, a:u, b:size, c:l, d:m, e:rm, f:opcode, g:H, h:rn, i:rd +simd_shift_immed 0ab01111 0ccccddd eeeee1ff fffggggg, a:q, b:u, c:immh:!:0000, d:immb, e:opcode, f:rn, g:rd +simd_table_lookup 0a001110 000bbbbb 0ccd00ee eeefffff, a:q, b:rm, c:len, d:op, e:rn, f:rd +simd_three_diff 0ab01110 cc1ddddd eeee00ff fffggggg, a:q, b:u, c:size, d:rm, e:opcode, f:rn, g:rd +simd_three_same 0ab01110 cc1ddddd ccccc1dd dddeeeee, a:q, b:u, c:size, d:rm, c:opcode, d:rn, e:rd +simd_two_reg 0ab01110 cc10000d dddd10ee eeefffff, a:q, b:u, c:size, d:opcode, e:rn, f:rd +simd_x_indexed 0ab01111 ccdeffff ggggh0ii iiijjjjj, a:q, b:u, c:size, d:l, e:m, f:rm, g:opcode, h:H, i:rn, j:rd +crypto_aes 01001110 0010100a aaaa10bb bbbccccc, a:opcode, b:rn, c:rd +crypto_sha_reg3 01011110 000aaaaa 0ccc00dd dddeeeee, a:rm, c:opcode, d:rn, e:rd +crypto_sha_reg2 01011110 0010100a aaaa10bb bbbccccc, a:opcode, b:rn, c:rd +FCMP 00011110 aa1bbbbb 001000cc cccddddd, a:type, b:rm, c:rn, d:opcode2 +FCCMP 00011110 aa1bbbbb cccc01dd dddeffff, a:type, b:rm, c:cond, d:rn, e:op, f:nzcv +FCSEL 00011110 aa1bbbbb cccc11dd dddeeeee, a:type, b:rm, c:cond, d:rn, e:rd +float_reg1 00011110 aa1bbbbb b10000cc cccddddd, a:type, b:opcode, c:rn, d:rd +float_reg2 00011110 aa1bbbbb cccc10dd dddeeeee, a:type, b:rm, c:opcode, d:rn, e:rd +float_reg3 00011111 aabccccc deeeeeff fffggggg, a:type, b:o1, c:rm, d:o0, e:Ra, f:rn, g:rd +FMOV_immed 00011110 aa1bbbbb bbb10000 000ccccc, a:type, b:imm8, c:rd +float_cvt_fixed a0011110 bb0ccddd eeeeeeff fffggggg, a:sf, b:type, c:rmode, d:opcode, e:scale, f:rn, g:rd +float_cvt_int a0011110 bb1ccddd 000000ee eeefffff, a:sf, b:type, c:rmode, d:opcode, e:rn, f:rd diff --git a/pie/arm.txt b/pie/arm.txt new file mode 100644 index 00000000..2803f9dc --- /dev/null +++ b/pie/arm.txt @@ -0,0 +1,476 @@ +# +# This file is part of PIE, an instruction encoder / decoder generator: +# https://github.com/beehive-lab/pie +# +# Copyright 2011-2016 Cosmin Gorgovan +# Copyright 2017-2021 The University of Manchester +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# Core instructions +# +adc aaaa00b0 101cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +add aaaa00b0 100cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +and aaaa00b0 000cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +b aaaa1010 bbbbbbbb bbbbbbbb bbbbbbbb, a:auto_cond, b:offset_branch +bfc aaaa0111 110bbbbb ccccdddd d0011111, a:auto_cond, c:rt, d:lsb, b:msb +bfi aaaa0111 110bbbbb ccccdddd d001eeee, a:auto_cond, c:rt, e:rn, d:lsb, b:msb +bic aaaa00b1 110cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +bkpt aaaa0001 0010bbbb bbbbbbbb 0111cccc, a:auto_cond, b:imm12, c:imm4 +bl aaaa1011 bbbbbbbb bbbbbbbb bbbbbbbb, a:auto_cond, b:offset_branch +blx aaaa0001 00101111 11111111 0011bbbb, a:auto_cond, b:rn +blxi 1111101a bbbbbbbb bbbbbbbb bbbbbbbb, a:h, b:imm24 +bx aaaa0001 00101111 11111111 0001bbbb, a:auto_cond, b:rn +cdp aaaa1110 bbbbcccc ddddeeee fff0gggg, a:auto_cond, b:opc1, c:crn, d:crd, e:coproc, f:opc2, g:crm +cdp2 11111110 bbbbcccc ddddeeee fff0gggg, b:opc1, c:crn, d:crd, e:coproc, f:opc2, g:crm +clrex 11110101 01111111 11110000 00011111 +clz aaaa0001 01101111 bbbb1111 0001cccc, a:auto_cond, b:rd, c:rm +cmn aaaa00b1 0111cccc 0000dddd dddddddd, a:auto_cond, b:immediate, c:rn, d:operand2 +cmp aaaa00b1 0101cccc 0000dddd dddddddd, a:auto_cond, b:immediate, c:rn, d:operand2 +dbg aaaa0011 00100000 11110000 1111bbbb, a:auto_cond, b:option +dmb 11110101 01111111 11110000 0101aaaa, a:option +dsb 11110101 01111111 11110000 0100aaaa, a:option +eor aaaa00b0 001cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +isb 11110101 01111111 11110000 0110aaaa, a:option +ldc aaaa110p udw1bbbb ccccdddd eeeeeeee, a:auto_cond, p:p, u:u, d:d, w:w, b:rn, c:crd, d:coproc, e:imm8 +ldm aaaa100b cde1ffff gggggggg gggggggg, a:auto_cond, f:rn, g:registers, b:prepostindex, c:updown, e:writeback, d:psr +ldr aaaa01bc d0e1ffff gggghhhh hhhhhhhh, a:auto_cond, b:immediate, g:rd, f:rn, h:offset, c:prepostindex, d:updown, e:writeback +ldrb aaaa01bc d1e1ffff gggghhhh hhhhhhhh, a:auto_cond, b:immediate, g:rd, f:rn, h:offset, c:prepostindex, d:updown, e:writeback +ldrbt aaaa01b0 u111cccc ddddeeee eeeeeeee, a:auto_cond, b:immediate, d:rd, c:rn, u:updown, e:operand2 +ldrd aaaa000b cde0ffff gggghhhh 1101iiii, a:auto_cond, d:immediate, g:rd, f:rn, i:rm_imm4l, h:imm4h, b:prepostindex, c:updown, e:writeback +ldrex aaaa0001 1001bbbb cccc1111 10011111, a:auto_cond, c:rd, b:rn +ldrexb aaaa0001 1101bbbb cccc1111 10011111, a:auto_cond, c:rd, b:rn +ldrexd aaaa0001 1011bbbb cccc1111 10011111, a:auto_cond, c:rd, b:rn +ldrexh aaaa0001 1111bbbb cccc1111 10011111, a:auto_cond, c:rd, b:rn +ldrh aaaa000b cde1ffff gggghhhh 1011iiii, a:auto_cond, d:immediate, g:rd, f:rn, i:rm_imm4l, h:imm4h, b:prepostindex, c:updown, e:writeback +ldrht aaaa0000 ub11cccc dddddeee 1011ffff, a:auto_cond, b:immediate, d:rd, c:rn, f:rm_imm4l, e:imm4h, u:updown +ldrsb aaaa000p ubw1cccc ddddeeee 1101ffff, a:auto_cond, b:immediate, d:rd, c:rn, f:rm_imm4l, e:imm4h, p:index, u:updown, w:writeback +ldrsbt aaaa0000 ub11cccc ddddeeee 1101ffff, a:auto_cond, b:immediate, d:rd, c:rn, f:rm, e:imm4h, u:updown +ldrsh aaaa000p ubw1cccc ddddeeee 1111ffff, a:auto_cond, b:immediate, d:rd, c:rn, f:rm_imm4l, e:imm4h, p:prepostindex, u:updown, w:writeback +ldrsht aaaa0000 ub11cccc ddddeeee 1111ffff, a:auto_cond, b:immediate, d:rd, c:rn, f:rm, e:imm4h, u:updown +ldrt aaaa01b0 u011cccc ddddeeee eeeeeeee, a:auto_cond, b:immediate, d:rd, c:rn, u:updown, e:operand2 +mcr aaaa1110 bbb0cccc ddddeeee fff1gggg, a:auto_cond, b:opc1, c:crn, d:rd, e:coproc, f:opc2, g:crm +mcrr aaaa1100 0100bbbb ccccdddd eeeeffff, a:auto_cond, d:coproc, e:opc1, c:rt, b:rt2, f:crm +mla aaaa0000 0010bbbb ccccdddd 1001eeee, a:auto_cond, b:rd, e:rm, d:rs, c:rn +mls aaaa0000 0110bbbb ccccdddd 1001eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +mov aaaa00b1 101c0000 ddddeeee eeeeeeee, a:auto_cond, b:immediate, c:set_condition, d:rd, e:operand2 +movt aaaa0011 0100bbbb ccccdddd dddddddd, a:auto_cond, c:rd, b:rn, d:operand2 +movw aaaa0011 0000bbbb ccccdddd dddddddd, a:auto_cond, c:rd, b:rn, d:operand2 +mrc aaaa1110 bbb1cccc ddddeeee fff1gggg, a:auto_cond, b:opc1, c:crn, d:rd, e:coproc, f:opc2, g:crm +mrrc aaaa1100 0101bbbb ccccdddd eeeeffff, a:auto_cond, d:coproc, e:opc1, c:rt, b:rt2, f:crm +mrs aaaa0001 00001111 bbbb0000 00000000, a:auto_cond, b:rd +msr aaaa0001 0010bb00 11110000 0000cccc, a:auto_cond, c:rn, b:mask +msri aaaa0011 0010bb00 1111cccc cccccccc, a:auto_cond, b:mask, c:imm12 +mul aaaa0000 0000bbbb 0000cccc 1001dddd, a:auto_cond, b:rd, d:rm, c:rs +mvn aaaa00b1 111c0000 ddddeeee eeeeeeee, a:auto_cond, b:immediate, c:set_condition, d:rd, e:operand2 +nop aaaa0011 00100000 11110000 00000000, a:auto_cond +orr aaaa00b1 100cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +pkh aaaa0110 1000bbbb ccccdddd de01ffff, a:auto_cond, c:rd, b:rn, f:rm, e:tb, d:imm5 +pld 111101i1 ab01cccc 1111dddd dddddddd, i:immediate, a:updown, b:is_read, c:rn, d:operand2 +pli 11110110 a101bbbb 1111cccc cdd0eeee, a:updown, b:rn, c:imm5, d:type, e:rm +plii 11110100 a101bbbb 1111cccc cccccccc, a:updown, b:rn, c:imm12 +qadd aaaa0001 0000bbbb cccc0000 0101dddd, a:auto_cond, c:rd, d:rm, b:rn +qadd16 aaaa0110 0010bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm +qadd8 aaaa0110 0010bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm +qasx aaaa0110 0010bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:rn, d:rm +qdadd aaaa0001 0100bbbb cccc0000 0101dddd, a:auto_cond, c:rd, d:rm, b:rn +qdsub aaaa0001 0110bbbb cccc0000 0101dddd, a:auto_cond, c:rd, d:rm, b:rn +qsax aaaa0110 0010bbbb cccc1111 0101dddd, a:auto_cond, c:rd, b:rn, d:rm +qsub aaaa0001 0010bbbb cccc0000 0101dddd, a:auto_cond, c:rd, d:rm, b:rn +qsub16 aaaa0110 0010bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +qsub8 aaaa0110 0010bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +rbit aaaa0110 11111111 bbbb1111 0011cccc, a:auto_cond, b:rd, c:rm +rev aaaa0110 10111111 bbbb1111 0011cccc, a:auto_cond, b:rd, c:rm +rev16 aaaa0110 10111111 bbbb1111 1011cccc, a:auto_cond, b:rd, c:rm +revsh aaaa0110 11111111 bbbb1111 1011cccc, a:auto_cond, b:rd, c:rm +rrx aaaa0001 101s0000 bbbb0000 0110cccc, a:auto_cond, s:set_condition, b:rd, c:rm +rsb aaaa00b0 011cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +rsc aaaa00b0 111fcccc ddddeeee eeeeeeee, a:auto_cond, b:immediate, f:set_condition, d:rd, c:rn, e:operand2 +sadd16 aaaa0110 0001bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm +sadd8 aaaa0110 0001bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm +sasx aaaa0110 0001bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:rn, d:rm +sbc aaaa00b0 110cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +sbfx aaaa0111 101bbbbb ccccdddd d101eeee, a:auto_cond, c:rd, e:rn, d:lsb, b:widthm1 +sdiv aaaa0111 0001bbbb 1111cccc 0001dddd, a:auto_cond, b:rd, d:rn, c:rm +sel aaaa0110 1000bbbb cccc1111 1011dddd, a:auto_cond, c:rd, b:rn, d:rm +setend 11110001 00000001 000000e0 00000000, e:set_bigend +setpan 11110001 00010000 000000a0 00000000, a:imm +sev aaaa0011 00100000 11110000 00000100, a:auto_cond +shadd16 aaaa0110 0011bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm +shadd8 aaaa0110 0011bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm +shasx aaaa0110 0011bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:rn, d:rm +shsax aaaa0110 0011bbbb cccc1111 0101dddd, a:auto_cond, c:rd, b:rn, d:rm +shsub16 aaaa0110 0011bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +shsub8 aaaa0110 0011bbbb cccc1111 1111dddd, a:auto_cond, c:rd, b:rn, d:rm +smlabb aaaa0001 0000bbbb ccccdddd 1000eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlabt aaaa0001 0000bbbb ccccdddd 1100eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlatb aaaa0001 0000bbbb ccccdddd 1010eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlatt aaaa0001 0000bbbb ccccdddd 1110eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlad aaaa0111 0000bbbb ccccdddd 00m1eeee, a:auto_cond, m:swap, b:rd, e:rn, d:rm, c:ra +smlal aaaa0000 111bcccc ddddeeee 1001ffff, a:auto_cond, b:set_condition, c:rdhi, d:rdlo, e:rm, f:rn +smlalbb aaaa0001 0100bbbb ccccdddd 1000eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlalbt aaaa0001 0100bbbb ccccdddd 1100eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlaltb aaaa0001 0100bbbb ccccdddd 1010eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlaltt aaaa0001 0100bbbb ccccdddd 1110eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlald aaaa0111 0100bbbb ccccdddd 0001eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlaldx aaaa0111 0100bbbb ccccdddd 0011eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlawb aaaa0001 0010bbbb ccccdddd 1000eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlawt aaaa0001 0010bbbb ccccdddd 1100eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlsd aaaa0111 0000bbbb ccccdddd 0101eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlsdx aaaa0111 0000bbbb ccccdddd 0111eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smlsld aaaa0111 0100bbbb ccccdddd 0101eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smlsldx aaaa0111 0100bbbb ccccdddd 0111eeee, a:auto_cond, c:rd_lo, b:rd_hi, e:rn, d:rm +smmla aaaa0111 0101bbbb ccccdddd 0001eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smmlar aaaa0111 0101bbbb ccccdddd 0011eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smmls aaaa0111 0101bbbb ccccdddd 1101eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smmlsr aaaa0111 0101bbbb ccccdddd 1111eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +smmul aaaa0111 0101bbbb 1111cccc 0001dddd, a:auto_cond, b:rd, d:rn, c:rm +smmulr aaaa0111 0101bbbb 1111cccc 0011dddd, a:auto_cond, b:rd, d:rn, c:rm +smuad aaaa0111 0000bbbb 1111cccc 0001dddd, a:auto_cond, b:rd, d:rn, c:rm +smuadx aaaa0111 0000bbbb 1111cccc 0011dddd, a:auto_cond, b:rd, d:rn, c:rm +smulbb aaaa0001 0110bbbb 0000cccc 1000dddd, a:auto_cond, b:rd, d:rn, c:rm +smulbt aaaa0001 0110bbbb 0000cccc 1100dddd, a:auto_cond, b:rd, d:rn, c:rm +smultb aaaa0001 0110bbbb 0000cccc 1010dddd, a:auto_cond, b:rd, d:rn, c:rm +smultt aaaa0001 0110bbbb 0000cccc 1110dddd, a:auto_cond, b:rd, d:rn, c:rm +smull aaaa0000 110bcccc ddddeeee 1001ffff, a:auto_cond, b:set_condition, c:rdhi, d:rdlo, e:rm, f:rn +smulwb aaaa0001 0010bbbb 0000cccc 1010dddd, a:auto_cond, b:rd, d:rn, c:rm +smulwt aaaa0001 0010bbbb 0000cccc 1110dddd, a:auto_cond, b:rd, d:rn, c:rm +smusd aaaa0111 0000bbbb 1111cccc 0101dddd, a:auto_cond, b:rd, d:rn, c:rm +smusdx aaaa0111 0000bbbb 1111cccc 0111dddd, a:auto_cond, b:rd, d:rn, c:rm +ssat aaaa0110 101bbbbb ccccdddd de01ffff, a:auto_cond, c:rd, b:sat_imm, f:rn, e:sh, d:imm5 +ssat16 aaaa0110 1010bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:sat_imm, d:rn +ssax aaaa0110 0001bbbb cccc1111 0101dddd, a:auto_cond, c:rd, b:rn, d:rm +ssub16 aaaa0110 0001bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +ssub8 aaaa0110 0001bbbb cccc1111 1111dddd, a:auto_cond, c:rd, b:rn, d:rm +stc aaaa110b cde0ffff gggghhhh iiiiiiii, a:auto_cond, b:p, c:upwards, d:d, e:writeback, f:rn, g:vd, h:opcode, i:imm8 +stm aaaa100b cde0ffff gggggggg gggggggg, a:auto_cond, f:rn, g:registers, b:prepostindex, c:updown, e:writeback, d:psr +str aaaa01bc d0e0ffff gggghhhh hhhhhhhh, a:auto_cond, b:immediate, g:rd, f:rn, h:offset, c:prepostindex, d:updown, e:writeback +strb aaaa01bc d1e0ffff gggghhhh hhhhhhhh, a:auto_cond, b:immediate, g:rd, f:rn, h:offset, c:prepostindex, d:updown, e:writeback +strbt aaaa01b0 d110ffff gggghhhh hhhhhhhh, a:auto_cond, b:immediate, g:rd, f:rn, h:offset, d:updown +strd aaaa000b cde0ffff gggghhhh 1111iiii, a:auto_cond, d:immediate, g:rd, f:rn, i:rm_imm4l, h:imm4h, b:prepostindex, c:updown, e:writeback +strex aaaa0001 1000bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm +strexb aaaa0001 1100bbbb cccc1111 1001dddd, a:auto_cond, c:rd, d:rt, b:rn +strexd aaaa0001 1010bbbb cccc1111 1001dddd, a:auto_cond, c:rd, d:rt, b:rn +strexh aaaa0001 1110bbbb cccc1111 1001dddd, a:auto_cond, c:rd, d:rt, b:rn +strh aaaa000b cde0ffff gggghhhh 1011iiii, a:auto_cond, d:immediate, g:rd, f:rn, i:rm_imm4l, h:imm4h, b:prepostindex, c:updown, e:writeback +strht aaaa0000 ui10bbbb ccccdddd 1011eeee, a:auto_cond, i:immediate, c:rd, b:rn, e:rm_imm4l, d:imm4h, u:updown +strt aaaa01i0 u010bbbb ccccdddd dddddddd, a:auto_cond, i:immediate, c:rd, b:rn, d:operand2, u:updown +sub aaaa00b0 010cdddd eeeeffff ffffffff, a:auto_cond, b:immediate, c:set_condition, e:rd, d:rn, f:operand2 +svc aaaa1111 bbbbbbbb bbbbbbbb bbbbbbbb, a:auto_cond, b:comment +swp aaaa0001 0000cccc dddd0000 1001eeee, a:auto_cond, d:rt, e:rt2, c:rn +swpb aaaa0001 0100cccc dddd0000 1001eeee, a:auto_cond, d:rt, e:rt2, c:rn +sxtab aaaa0110 1010bbbb ccccdd00 0111eeee, a:auto_cond, c:rd, b:rn, e:rm, d:rotate +sxtab16 aaaa0110 1000bbbb ccccdd00 0111eeee, a:auto_cond, c:rd, b:rn, e:rm, d:rotate +sxtah aaaa0110 1011bbbb ccccdd00 0111eeee, a:auto_cond, c:rd, b:rn, e:rm, d:rotate +sxtb aaaa0110 10101111 bbbbcc00 0111dddd, a:auto_cond, b:rd, d:rm, c:rotate +sxtb16 aaaa0110 10001111 bbbbcc00 0111dddd, a:auto_cond, b:rd, d:rm, c:rotate +sxth aaaa0110 10111111 bbbbcc00 0111dddd, a:auto_cond, b:rd, d:rm, c:rotate +teq aaaa00b1 0011cccc 0000dddd dddddddd, a:auto_cond, b:immediate, c:rn, d:operand2 +tst aaaa00b1 0001cccc 0000dddd dddddddd, a:auto_cond, b:immediate, c:rn, d:operand2 +uadd16 aaaa0110 0101cccc dddd1111 0001eeee, a:auto_cond, d:rd, c:rn, e:rm +uadd8 aaaa0110 0101cccc dddd1111 1001eeee, a:auto_cond, d:rd, c:rn, e:rm +uasx aaaa0110 0101cccc dddd1111 0011eeee, a:auto_cond, d:rd, c:rn, e:rm +ubfx aaaa0111 111bbbbb ccccdddd d101eeee, a:auto_cond, c:rd, e:rn, d:lsb, b:widthm1 +udf 11100111 1111bbbb bbbbbbbb 1111cccc, b:imm12, c:imm4 +udiv aaaa0111 0011bbbb 1111cccc 0001dddd, a:auto_cond, b:rd, d:rn, c:rm +uhadd16 aaaa0110 0111bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm +uhadd8 aaaa0110 0111bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm +uhasx aaaa0110 0111bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:rn, d:rm +uhsax aaaa0110 0111bbbb cccc1111 0101dddd, a:auto_cond, c:rd, b:rn, d:rm +uhsub16 aaaa0110 0111bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +uhsub8 aaaa0110 0111bbbb cccc1111 1111dddd, a:auto_cond, c:rd, b:rn, d:rm +umaal aaaa0000 0100aaaa bbbbcccc 1001dddd, a:auto_cond, b:rd_lo, a:rd_hi, d:rn, c:rm +umlal aaaa0000 101bcccc ddddeeee 1001ffff, a:auto_cond, b:set_condition, c:rdhi, d:rdlo, e:rm, f:rn +umull aaaa0000 100bcccc ddddeeee 1001ffff, a:auto_cond, b:set_condition, c:rdhi, d:rdlo, e:rm, f:rn +uqadd16 aaaa0110 0110bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm +uqadd8 aaaa0110 0110bbbb cccc1111 1001dddd, a:auto_cond, c:rd, b:rn, d:rm +uqasx aaaa0110 0110bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:rn, d:rm +uqsax aaaa0110 0110bbbb cccc1111 0101dddd, a:auto_cond, c:rd, b:rn, d:rm +uqsub16 aaaa0110 0110bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +uqsub8 aaaa0110 0110bbbb cccc1111 1111dddd, a:auto_cond, c:rd, b:rn, d:rm +usad8 aaaa0111 1000bbbb cccc1111 0001dddd, a:auto_cond, c:rd, b:rn, d:rm +usada8 aaaa0111 1000bbbb ccccdddd 0001eeee, a:auto_cond, b:rd, e:rn, d:rm, c:ra +usat aaaa0110 111bbbbb ccccdddd de01ffff, a:auto_cond, c:rd, b:sat_imm, f:rn, e:sh, d:imm5 +usat16 aaaa0110 1110bbbb cccc1111 0011dddd, a:auto_cond, c:rd, b:sat_imm, d:rn +usax aaaa0110 0101bbbb cccc1111 0101dddd, a:auto_cond, c:rd, b:rn, d:rm +usub16 aaaa0110 0101bbbb cccc1111 0111dddd, a:auto_cond, c:rd, b:rn, d:rm +usub8 aaaa0110 0101bbbb cccc1111 1111dddd, a:auto_cond, c:rd, b:rn, d:rm +uxtab aaaa0110 1110bbbb ccccdd00 0111eeee, a:auto_cond, c:rd, b:rn, e:rm, d:rotate +uxtab16 aaaa0110 1100bbbb ccccdd00 0111eeee, a:auto_cond, c:rd, b:rn, e:rm, d:rotate +uxtah aaaa0110 1111bbbb ccccdd00 0111eeee, a:auto_cond, c:rd, b:rn, e:rm, d:rotate +uxtb aaaa0110 11101111 bbbbcc00 0111dddd, a:auto_cond, b:rd, d:rm, c:rotate +uxtb16 aaaa0110 11001111 bbbbcc00 0111dddd, a:auto_cond, b:rd, d:rm, c:rotate +uxth aaaa0110 11111111 bbbbcc00 0111dddd, a:auto_cond, b:rd, d:rm, c:rotate +wfe aaaa0011 00100000 11110000 00000010, a:auto_cond +wfi aaaa0011 00100000 11110000 00000011, a:auto_cond +yield aaaa0011 00100000 11110000 00000001, a:auto_cond +# +# +# NEON and VFP instructions +# +# naming rules: if there are separate encodings for integer and fp, add _i, _f suffxies +# neon_, vfp_ prefixes +# _scal = scalar +# _hp = half precision +# _sp = single precision +# _dp = double precision +# _i = integer +# _f = floating point +# _fp = fixed point +# _core = arm core register +# i = immediate +# z = compare with immediate #0 +# +# Ordering of operands: auto_cond, op, float_p, unsign, size, q +# +neon_vaba 1111001u 0daabbbb cccc0111 nqm1eeee, u:unsign, a:size, q:q, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vabal 1111001u 1daabbbb cccc0101 n0m0eeee, u:unsign, a:size:!:11, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vabd_i 1111001u 0daabbbb cccc0111 nqm0eeee, u:unsign, a:size, q:q, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vabd_f 11110011 0d1saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vabdl 1111001u 1daabbbb cccc0111 n0m0eeee, u:unsign, a:size:!:11, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vabs 11110011 1d11ss01 aaaa0f11 0qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm + vfp_vabs aaaa1110 1d110000 bbbb101s 11m0cccc, a:auto_cond, s:size, d:d, b:vd, m:m, c:vm +neon_vacge 11110011 0d0saaaa bbbb1110 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vacgt 11110011 0d1saaaa bbbb1110 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vadd_i 11110010 0abbcccc dddd1000 efg0hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vadd_f 11110010 0d0saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vadd aaaa1110 0d11bbbb cccc101s n0meeeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vaddhn 11110010 1dssaaaa bbbb0100 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vaddl 1111001u 1dssaaaa bbbb0000 n0m0cccc, s:size:!:11, u:unsign, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vaddw 1111001u 1dssaaaa bbbb0001 n0m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vand 11110010 0d00aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vbici 1111001i 1d000aaa bbbbcccc 0q11eeee, q:q, d:d, b:vd, c:cmode:=:0001:0011:0101:0111:1001:1011, i:i, a:imm3, e:imm4 +neon_vbic 11110010 0d01aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vbif 11110011 0d11aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vbit 11110011 0d10aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vbsl 11110011 0d01aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vceq_i 11110011 0dssaaaa bbbb1000 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vceq_f 11110010 0d0saaaa bbbb1110 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vceqz 11110011 1d11ss01 aaaa0f01 0qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcge_i 1111001u 0dssaaaa bbbb0011 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcge_f 11110011 0d0saaaa bbbb1110 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcgez 11110011 1d11ss01 aaaa0f00 1qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcgt_i 1111001u 0dssaaaa bbbb0011 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcgt_f 11110011 0d1saaaa bbbb1110 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcgtz 11110011 1d11ss01 aaaa0f00 0qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vclez 11110011 1d11ss01 aaaa0f01 1qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcls 11110011 1d11ss00 aaaa0100 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcltz 11110011 1d11ss01 aaaa0f10 0qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vclz 11110011 1d11ss00 aaaa0100 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm + vfp_vcmp aaaa1110 1b110100 cccc101d 01e0ffff, a:auto_cond, b:d, c:vd, d:sz, e:m, f:vm + vfp_vcmpz aaaa1110 1b110101 cccc101d 01000000, a:auto_cond, b:d, c:vd, d:sz + vfp_vcmpe aaaa1110 1b110100 cccc101d 11e0ffff, a:auto_cond, b:d, c:vd, d:sz, e:m, f:vm + vfp_vcmpez aaaa1110 1b110101 cccc101d 11000000, a:auto_cond, b:d, c:vd, d:sz +neon_vcnt 11110011 1d11ss00 aaaa0101 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcvt_f_i 11110011 1d11ss11 aaaa011o oqm0bbbb, o:op, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcvt_f_fp 1111001u 1daaaaaa bbbb111o 0qm1cccc, o:op, u:unsign, q:q, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vcvt_hp_sp 11110011 1d11ss10 aaaa011o 00m0bbbb, o:op, s:size, d:d, a:vd, m:m, b:vm + vfp_vcvt_f_i aaaa1110 1b111ccc dddd101e o1g0hhhh, a:auto_cond, o:op, c:opcode2, e:sz, b:d, d:vd, g:m, h:vm + vfp_vcvt_f_fp aaaa1110 1d111o1u bbbb101c e1i0ffff, a:auto_cond, o:op, u:unsign, c:sf, e:sx, d:d, b:vd, f:imm4, i:i + vfp_vcvt_dp_sp aaaa1110 1d110111 bbbb101s 11m0cccc, a:auto_cond, s:size, d:d, b:vd, m:m, c:vm + vfp_vcvtb aaaa1110 1d11001o bbbb1010 01m0cccc, a:auto_cond, o:op, d:d, b:vd, m:m, c:vm + vfp_vcvtt aaaa1110 1d11001o bbbb1010 11m0cccc, a:auto_cond, o:op, d:d, b:vd, m:m, c:vm + vfp_vdiv aaaa1110 1d00bbbb cccc101s n0m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vdup_scal 11110011 1d11aaaa bbbb1100 0qm0cccc, a:auto_cond, q:q, a:imm4, d:d, b:vd, m:m, c:vm +neon_vdup_core aaaa1110 1bq0cccc ffff1011 d0e10000, a:auto_cond, b:b, e:e, q:q, d:d, c:vd, f:rt +neon_veor 11110011 0d00aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vext 11110010 1d11aaaa bbbbcccc nqm0eeee, q:q, d:d, b:vd, n:n, a:vn, m:m, e:vm, c:imm4 +neon_vfma 11110010 0d0saaaa bbbb1100 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vfmal 11111100 0a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vfmal_scal 11111110 0a00bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vfms 11110010 0d1saaaa bbbb1100 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vfma aaaa1110 1d10bbbb cccc101s n0m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm + vfp_vfms aaaa1110 1d10bbbb cccc101s n1m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vfmsl_scal 11111110 0a01bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vfmsl 11111100 1a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm + vfp_vfnma aaaa1110 1d01bbbb cccc101s n1m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm + vfp_vfnms aaaa1110 1d01bbbb cccc101s n0m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vhadd 1111001u 0dssaaaa bbbb0000 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vhsub 1111001u 0dssaaaa bbbb0010 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vins 11111110 1a110000 bbbb1010 11c0dddd, a:d, b:vd, c:m, d:vm +neon_vldx_m 11110100 0a10bbbb ccccdddd eeffgggg, d:opcode, e:size, a:d, c:vd, b:rn, f:align, g:rm +neon_vldx_s_o 11110100 1a10bbbb ccccddee ffffgggg, e:opcode, d:size, a:d, c:vd, b:rn, f:index_align, g:rm +neon_vldx_s_a 11110100 1a10bbbb cccc11dd eetgffff, d:opcode, e:size, a:d, c:vd, t:inc, b:rn, g:align, f:rm + vfp_vldm_dp aaaa110b cde1ffff gggg1011 hhhhhhhh, a:auto_cond, b:p, c:upwards, d:d, e:writeback, f:rn, g:vd, h:imm8 + vfp_vldm_sp aaaa110b cde1ffff gggg1010 hhhhhhhh, a:auto_cond, b:p, c:upwards, d:d, e:writeback, f:rn, g:vd, h:imm8 + vfp_vldr_dp aaaa1101 bc01dddd eeee1011 ffffffff, a:auto_cond, b:upwards, c:d, d:rn, e:vd, f:imm8 + vfp_vldr_sp aaaa1101 bc01dddd eeee1010 ffffffff, a:auto_cond, b:upwards, c:d, d:rn, e:vd, f:imm8 +neon_vmax_i 1111001u 0dssaaaa bbbb0110 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmin_i 1111001u 0dssaaaa bbbb0110 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmax_f 11110010 0d0saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmin_f 11110010 0d1saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmla_i 11110010 0dssaaaa bbbb1001 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmls_i 11110011 0dssaaaa bbbb1001 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmlal_i 1111001u 1dssaaaa bbbb1000 n0m0cccc, u:unsign, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmlsl_i 1111001u 1dssaaaa bbbb1010 n0m0cccc, u:unsign, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmla_f 11110010 0d0saaaa bbbb1101 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmls_f 11110010 0d1saaaa bbbb1101 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vmla_f aaaa1110 0b00cccc dddd101s e0f0gggg, a:auto_cond, s:size, b:d, c:vn, d:vd, e:n, f:m, g:vm + vfp_vmls_f aaaa1110 0b00cccc dddd101s e1f0gggg, a:auto_cond, s:size, b:d, c:vn, d:vd, e:n, f:m, g:vm +neon_vmla_scal 1111001q 1dssaaaa bbbb000f n1m0cccc, f:float_p, s:size:!:11, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmls_scal 1111001q 1dssaaaa bbbb010f n1m0cccc, f:float_p, s:size:!:11, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmlal_scal 1111001u 1dssaaaa bbbb0010 n1m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmlsl_scal 1111001u 1dssaaaa bbbb0110 n1m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmovi 1111001i 1d000aaa bbbbcccc 0qo1eeee, q:q, d:d, b:vd, o:op, c:cmode:=:0000:0010:0100:0110:1000:1010:1100:1101:1110:1111, i:i, a:imm3, e:imm4 + vfp_vmovi aaaa1110 1d11bbbb cccc101s 0000eeee, a:auto_cond, s:size, d:d, c:vd, b:imm4h, e:imm4l +#neon_vmov 11110010 0d10aaaa bbbb0001 c1e1ffff, # encoded as vorr Rd, Rn = Rm + vfp_vmov aaaa1110 1d110000 bbbb101s 01m0cccc, a:auto_cond, s:size, d:d, b:vd, m:m, c:vm + vfp_vmov_core_scal aaaa1110 0bb0cccc dddd1011 eff10000, a:auto_cond, e:d, c:vd, b:opc1, f:opc2, d:rt + vfp_vmov_scal_core aaaa1110 bcc1dddd eeee1011 fgg10000, a:auto_cond, b:unsign, e:rt, f:n, d:vn, c:opc1, g:opc2 + vfp_vmov_core_sp aaaa1110 000obbbb cccc1010 n0010000, a:auto_cond, o:op, c:rt, n:n, b:vn + vfp_vmov_2core_2sp aaaa1100 010obbbb cccc1010 00m1dddd, a:auto_cond, o:op, c:rt, b:rt2, m:m, d:vm + vfp_vmov_2core_dp aaaa1100 010obbbb cccc1011 00m1dddd, a:auto_cond, o:op, c:rt, b:rt2, m:m, d:vm + vfp_vmov_hp aaaa1110 000bcccc dddd1001 e0010000, a:cond, b:op, d:rt, e:n, c:vn +neon_vmovl 1111001u 1daaa000 bbbb1010 00m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm3 +neon_vmovn 11110011 1d11ss10 aaaa0010 00m0bbbb, s:size, d:d, a:vd, m:m, b:vm + vfp_vmovx 11111110 1a110000 bbbb1010 01c0dddd, a:d, b:vd, c:m, d:vm + vfp_vmrs aaaa1110 11110001 bbbb1010 00010000, a:auto_cond, b:rt + vfp_vmsr aaaa1110 11100001 bbbb1010 00010000, a:auto_cond, b:rt +neon_vmul_i 1111001a 0bccdddd eeee1001 fgh1iiii, a:opcode, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vmull_i 1111001a 1bccdddd eeee11f0 g0h0iiii, a:opcode, f:opcode4, c:size, b:d, e:vd, g:n, d:vn, h:m, i:vm +neon_vmul_f 11110011 0d0saaaa bbbb1101 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vmul_f aaaa1110 0b10cccc dddd101s e0f0gggg, a:auto_cond, s:size, b:d, c:vn, d:vd, e:n, f:m, g:vm +neon_vmul_scal 1111001a 1bccdddd eeee100f g1h0iiii, a:opcode, f:opcode5, c:size, b:d, e:vd, g:n, d:vn, h:m, i:vm +neon_vmull_scal 1111001a 1bccdddd eeee1010 f1g0hhhh, a:opcode, c:size, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vmvni 1111001i 1d000aaa bbbbcccc 0q11eeee, q:q, d:d, b:vd, c:cmode:=:0000:0010:0100:0110:1000:1010:1100:1101, i:i, a:imm3, e:imm4 +neon_vmvn 11110011 1a11bb00 cccc0101 1de0ffff, b:size, d:q, a:d, c:vd, e:m, f:vm +neon_vneg 11110011 1d11ss01 aaaa0f11 1qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm + vfp_vneg aaaa1110 1d110001 bbbb101s 01m0cccc, a:auto_cond, s:size, d:d, b:vd, m:m, c:vm + vfp_vnmla aaaa1110 0d01bbbb cccc101s n1m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm + vfp_vnmls aaaa1110 0d01bbbb cccc101s n0m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm + vfp_vnmul aaaa1110 0d10bbbb cccc101s n1m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vorn 11110010 0d11aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vorri 1111001i 1d000aaa bbbbcccc 0q01eeee, q:q, d:d, b:vd, c:cmode:=:0001:0011:0101:0111:1001:1011:, i:i, a:imm3, e:imm4 +neon_vorr 11110010 0d10aaaa bbbb0001 nqm1cccc, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpadal 11110011 1d11ss00 aaaa0110 oqm0bbbb, o:unsign, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vpadd_i 11110010 0dssaaaa bbbb1011 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpadd_f 11110011 0d0saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpaddl 11110011 1d11ss00 aaaa0010 oqm0bbbb, o:unsign, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vpmax_i 1111001u 0dssaaaa bbbb1010 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpmin_i 1111001u 0dssaaaa bbbb1010 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpmax_f 11110011 0d0saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpmin_f 11110011 0d1saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vpop_dp aaaa1100 1d111101 bbbb1011 cccccccc, a:auto_cond, d:d, b:vd, c:imm8 + vfp_vpop_sp aaaa1100 1d111101 bbbb1010 cccccccc, a:auto_cond, d:d, b:vd, c:imm8 + vfp_vpush_dp aaaa1101 0d101101 bbbb1011 cccccccc, a:auto_cond, d:d, b:vd, c:imm8 + vfp_vpush_sp aaaa1101 0d101101 bbbb1010 cccccccc, a:auto_cond, d:d, b:vd, c:imm8 +neon_vqabs 11110011 1d11ss00 aaaa0111 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vqadd 1111001a 0bccdddd eeee0000 fgh1iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vqdmlal_i 11110010 1dssaaaa bbbb1001 n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmlsl_i 11110010 1dssaaaa bbbb1011 n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmlal_scal 11110010 1dssaaaa bbbb0011 n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmlsl_scal 11110010 1dssaaaa bbbb0111 n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmulh_i 11110010 0dssaaaa bbbb1011 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmulh_scal 1111001q 1dssaaaa bbbb1100 n1m0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmull_i 11110010 1dssaaaa bbbb1101 n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmull_scal 11110010 1dssaaaa bbbb1011 n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqmovn 11110011 1d11ss10 aaaa0010 1om0bbbb, o:unsign, s:size, d:d, a:vd, m:m, b:vm +neon_vqmovun 11110011 1d11ss10 aaaa0010 01m0bbbb, s:size, d:d, a:vd, m:m, b:vm +neon_vqneg 11110011 1d11ss00 aaaa0111 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vqrdmlaha1 11110011 0abbcccc dddd1011 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vqrdmlaha2 1111001a 1bccdddd eeee1110 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vqrdmlsha1 11110011 0abbcccc dddd1100 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vqrdmlsha2 1111001a 1bccdddd eeee1111 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vqrdmulh_i 11110011 0dssaaaa bbbb1011 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqrdmulh_scal 1111001q 1dssaaaa bbbb1101 n1m0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqrshl 1111001u 0dssaaaa bbbb0101 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqrshrn 1111001u 1daaaaaa bbbb1001 01m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vqrshrun 11110011 1daaaaaa bbbb1000 01m1cccc, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vqshl 1111001u 0dssaaaa bbbb0100 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, m:m, c:vm, n:n, a:vn +neon_vqshli 1111001u 1daaaaaa bbbb0111 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vqshlui 11110011 1daaaaaa bbbb0110 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vqshrn 1111001u 1daaaaaa bbbb1001 00m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vqshrun 11110011 1daaaaaa bbbb1000 00m1cccc, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vqsub 1111001u 0dssaaaa bbbb0010 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vraddhn 11110011 1abbcccc dddd0100 e0f0gggg, b:size, a:d, d:vd, e:n, c:vn, f:m, g:vm +neon_vrecpe 11110011 1d11ss11 aaaa010f 0qm0bbbb, f:float_p, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrecps 11110010 0d0saaaa bbbb1111 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrev16 11110011 1d11ss00 aaaa0001 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrev32 11110011 1d11ss00 aaaa0000 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrev64 11110011 1d11ss00 aaaa0000 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrhadd 1111001u 0dssaaaa bbbb0001 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrshl 1111001u 0dssaaaa bbbb0101 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrshr 1111001a 1bcccccc dddd0010 efg1hhhh, a:unsign, f:q, b:d, d:vd, g:m, h:vm, e:l, c:imm6 +neon_vrshrn 11110010 1abbbbbb cccc1000 01d1eeee, a:d, c:vd, d:m, e:vm, b:imm6 +neon_vrsqrte 11110011 1d11ss11 aaaa010f 1qm0bbbb, f:floating_point, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrsqrts 11110010 0d1saaaa bbbb1111 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrsra 1111001u 1daaaaaa bbbb0011 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vrsubhn 11110011 1dssaaaa bbbb0110 n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsdot 11111100 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm +neon_vsdot_scal 11111110 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm +neon_vshl 1111001u 0dssaaaa bbbb0100 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vshli 11110010 1daaaaaa bbbb0101 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vshll 1111001u 1daaaaaa bbbb1010 00m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vshll2 11110011 1d11ss10 aaaa0011 00m0bbbb, s:size, d:d, a:vd, m:m, b:vm +neon_vshr 1111001u 1daaaaaa bbbb0000 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vshrn 11110010 1daaaaaa bbbb1000 00m1cccc, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vsli 11110011 1daaaaaa bbbb0101 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 + vfp_vsqrt aaaa1110 1d110001 bbbb101s 11m0cccc, a:auto_cond, s:size, d:d, b:vd, m:m, c:vm +neon_vsra 1111001a 1bcccccc dddd0001 efg1hhhh, a:unsign, f:q, b:d, d:vd, g:m, h:vm, e:l, c:imm6 +neon_vsri 11110011 1daaaaaa bbbb0100 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vstx_m 11110100 0a00bbbb ccccdddd eeffgggg, d:opcode, e:size, a:d, c:vd, b:rn, f:align, g:rm +neon_vstx_s_o 11110100 1a00bbbb ccccddee ffffgggg, e:opcode, d:size:!:11, a:d, c:vd, b:rn, f:index_align, g:rm + vfp_vstm_dp aaaa110b cde0ffff gggg1011 hhhhhhhh, a:auto_cond, b:p, c:upwards, d:d, e:writeback, f:rn, g:vd, h:imm8 + vfp_vstm_sp aaaa110b cde0ffff gggg1010 hhhhhhhh, a:auto_cond, b:p, c:upwards, d:d, e:writeback, f:rn, g:vd, h:imm8 + vfp_vstr_dp aaaa1101 bc00dddd eeee1011 ffffffff, a:auto_cond, b:upwards, c:d, d:rn, e:vd, f:imm8 + vfp_vstr_sp aaaa1101 bc00dddd eeee1010 ffffffff, a:auto_cond, b:upwards, c:d, d:rn, e:vd, f:imm8 +neon_vsub_i 11110011 0abbcccc dddd1000 efg0hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vsub_f 11110010 0d1saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vsub_f aaaa1110 0d11bbbb cccc101s n1m0eeee, a:auto_cond, s:size, d:d, c:vd, n:n, b:vn, m:m, e:vm +neon_vsubhn 11110010 1dssaaaa bbbb0110 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsubl 1111001u 1dssaaaa bbbb0010 n0m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsubw 1111001u 1dssaaaa bbbb0011 n0m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsudot 11111110 1a00bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vswp 11110011 1a11bb10 cccc0000 0de0ffff, b:size, d:q, a:d, c:vd, e:m, f:vm +neon_vtbl 11110011 1d11aaaa bbbb10cc n0m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm +neon_vtbx 11110011 1d11aaaa bbbb10cc n1m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm +neon_vtrn 11110011 1a11bb10 cccc0000 1de0ffff, b:size, d:q, a:d, c:vd, e:m, f:vm +neon_vtst 11110010 0dssaaaa bbbb1000 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vudot 11111100 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vudot_scal 11111110 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vusdot 11111100 1a10bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vusdot_scal 11111110 1a00bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vuzp 11110011 1d11ss10 aaaa0001 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vzip 11110011 1d11ss10 aaaa0001 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm + +br aaaa101b cccccccc cccccccc cccccccc, a:auto_cond, b:link, c:offset_branch +bx_t aaaa0001 00101111 11111111 00b1cccc, a:auto_cond, b:link, c:rn +blxi_t 1111101a bbbbbbbb bbbbbbbb bbbbbbbb, a:h, b:imm24 +data_proc aaaa00bc cccdeeee ffffgggg gggggggg, a:auto_cond, b:immediate, c:opcode, d:set_condition, f:rd, e:rn, g:operand2 +multiply aaaa0000 00bcdddd eeeeffff 1001gggg, a:auto_cond, b:accumulate, c:set_condition, d:rd, g:rm, f:rs, e:rn +s_data_transfer aaaa01bc defghhhh iiiijjjj jjjjjjjj, a:auto_cond, g:loadstore, b:immediate, e:byteword, i:rd, h:rn, j:offset, c:prepostindex, d:updown, f:writeback +h_data_transfer aaaabbbc defghhhh iiiijjjj kkkkllll, a:auto_cond, b:opcode, g:size, k:opcode2, e:immediate, i:rd, h:rn, l:rm, j:imm4h, c:prepostindex, d:updown, f:writeback +b_data_transfer aaaa100b cdefgggg hhhhhhhh hhhhhhhh, a:auto_cond, f:loadstore, g:rn, h:registers, b:prepostindex, c:updown, e:writeback, d:psr +svc_t aaaa1111 bbbbbbbb bbbbbbbb bbbbbbbb, a:auto_cond, b:comment +mem_hints_pli 1111aaaa bcccdddd 1111eeee eff0gggg, a:opcode1, b:updown, c:opcode2, d:rn, e:imm5, f:type, g:rm +mem_hints_pld 1111aaaa bcddeeee 1111ffff ffffffff, a:opcode1, b:updown, c:read_only, d:opcode2, e:rn, f:imm12 +vfp_ldm_stm aaaa110b cdefgggg hhhhiiii jjjjjjjj, a:auto_cond, b:p, c:upwards, d:d, e:writeback, f:load_store, g:rn, h:vd, i:opcode, j:imm8 +coproc_trans aaaa1110 bbbcdddd eeeeffff ggg1hhhh, a:auto_cond, b:opc1, c:load_store, d:crn, e:rd, f:coproc, g:opc2, h:crm +coproc_dp aaaa1110 bbbbcccc ddddeeee fff0gggg, a:auto_cond, b:opc1, c:crn, d:crd, e:coproc, f:opc2, g:crm +dsp_long_res aaaabbbb bbbcdddd eeeeffff gghhiiii, a:auto_cond, b:opcode, c:set_condition, d:rdhi, e:rdlo, f:rm, g:opcode2, h:setting, i:rn +vops 1111001a bcddeeee ffffgghi jklmnnnn, a:opcode, b:opcode2, g:opcode3, h:opcode4, i:opcode5, m:opcode6, d:size, k:q, c:d, f:vd, j:n, e:vn, l:m, n:vm +v_trans_mult 11110100 abccdddd eeeeffgg hhhhiiii, a:opcode, c:opcode2, f:opcode3, g:opcode4, h:params, b:d, e:vd, d:rn, i:rm +v_ops_2reg 11110011 abccddee ffffgggg hij0kkkk, a:opcode, c:opcode2, e:opcode3, g:opcode4, h:opcode5, d:size, b:d, f:vd, i:q, j:m, k:vm +v_ops_imm6 1111001a 1bcccccc ddddeeee fghijjjj, e:opcode, a:u, b:d, d:vd, g:q, h:m, j:vm, f:l, c:imm6, i:f3 +v_ops_1reg_mod_imm 1111001a bcdddeee ffffgggg hij1kkkk, b:opcode, d:opcode2, h:opcode3, g:cmode, c:d, f:vd, i:q, a:i, e:imm3, k:imm4, j:op +vfp_data_proc aaaa1110 1b110ccc dddd101e f1g0hhhh, a:auto_cond, b:d, c:opc2, d:vd, e:sz, f:op, g:m, h:vm +cpsr_trans_reg aaaa0001 00bbccdd eeee0000 0000ffff, a:auto_cond, b:opcode, c:mask, d:f2, e:rd, f:rn +cpsr_trans_imm aaaa0011 0010bb00 1111cccc cccccccc, a:auto_cond, b:mask, c:imm12 +divide aaaabbbb bbbbcccc 1111dddd 0001eeee, a:auto_cond, b:opcode, c:rd, e:rn, d:rm +sync 11110101 01111111 11110000 aaaabbbb, a:opcode, b:option +extend aaaabbbb bbbbcccc ddddee00 0111ffff, a:auto_cond, b:opcode, d:rd, c:rn, f:rm, e:rotate +vfp_3reg aaaabbbb bcddeeee ffffgggh i0j0kkkk, a:auto_cond, b:opcode, c:d, d:opcode2, e:vn, f:vd, g:opcode3, h:sz, i:n, j:m, k:vm +trans_arm_vfp aaaa1110 000bcccc ddddeeee fgh1iiii, a:auto_cond, b:op, c:vn, d:rd, e:opcode, f:n, g:f3, h:m, i:f5 +vfp_imm8_1reg aaaa1110 1b11cccc ddddeeee 0000ffff, a:auto_cond, e:opcode, b:d, d:vd, c:imm4h, f:imm4l +vfp_trans_2arm_reg aaaa1100 bbbcdddd eeee1011 00f1gggg, a:auto_cond, b:opcode, c:op, d:rt2, e:rt, f:m, g:vm diff --git a/pie/generate_common.rb b/pie/generate_common.rb new file mode 100644 index 00000000..5f52622d --- /dev/null +++ b/pie/generate_common.rb @@ -0,0 +1,132 @@ +=begin + +This file is part of PIE, an instruction encoder / decoder generator: + https://github.com/beehive-lab/pie + +Copyright 2011-2016 Cosmin Gorgovan +Copyright 2017-2021 The University of Manchester + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +=end + +def process_insts(filename, swaphw = false) + process_file(filename, true, swaphw) +end + +def process_all(filename, swaphw = false) + process_file(filename, false, swaphw) +end + +def do_swaphw(encoding) + return encoding[16..31] + encoding[0..15] if encoding.size == 32 + return encoding +end + +def process_file(filename, insts_only = false, swaphw = false) + insts = [] + + File.readlines(filename).each do |raw_line| + raw_line.strip! + if raw_line.empty? + break if insts_only + next + end + next if raw_line[0] == '#' + raw_line = raw_line.split('#')[0] + line = raw_line.split(/[, ]+/) + + inst = Hash.new + inst[:name] = line[0] + + inst[:bitmap] = "" + i = 1 + while (line[i] and !line[i].include?(':')) + inst[:bitmap] += line[i].strip + i += 1 + end + + inst[:fields] = {} + (i...line.size).each do |i| + field = line[i].split(':') + inst[:fields][field[0]] = {} + inst[:fields][field[0]][:name] = field[1].strip + if field[2] + case field[2] + when "!" + cond = :diff + when "=" + cond = :eq + else + abort "Unsupported condition: #{field[2][0]} on line: #{line}" + end + inst[:fields][field[0]][:cond] = cond + inst[:fields][field[0]][:cond_vals] = field[3..-1].map {|v| v.to_i(2)} + end + end + + # check that all fields have been defined + inst[:bitmap].each_char do |f| + unless f == '0' or f == '1' or inst[:fields][f] + warn "Error: field #{f} not defined for #{inst[:name]}" + warn raw_line + abort + end + end + + if swaphw + inst[:bitmap] = do_swaphw(inst[:bitmap]) + end + + insts.push inst + end + + return insts +end + +def inst_len_to_cptr(len) + case len + when 16 + c_ptr = "uint16_t" + when 32 + c_ptr = "uint32_t" + else + abort "Unknown instruction word width: #{len}" + end + return c_ptr +end + +def get_min_inst_len(insts) + min = 99999 + insts.each do |inst| + min = inst[:bitmap].size if inst[:bitmap].size < min + end + return min +end + +def get_max_inst_len(insts) + max = 0 + insts.each do |inst| + max = inst[:bitmap].size if inst[:bitmap].size > max + end + return max +end + +def get_field_shift(bitmap, label) + bitmap.size - bitmap.rindex(label) - 1 +end + +def get_field_mask(bitmap, label) + width = bitmap.rindex(label) - bitmap.index(label) + 1 + return "0x" + ((1 << width) -1).to_s(16) +end diff --git a/pie/generate_decoder.rb b/pie/generate_decoder.rb new file mode 100644 index 00000000..8a82c0b6 --- /dev/null +++ b/pie/generate_decoder.rb @@ -0,0 +1,291 @@ +=begin + +This file is part of PIE, an instruction encoder / decoder generator: + https://github.com/beehive-lab/pie + +Copyright 2011-2016 Cosmin Gorgovan +Copyright 2017-2021 The University of Manchester + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +=end + +require './generate_common.rb' + +class Node + attr_accessor :depth, :instruction, :left, :right + @depth + @value + @left + @right +end + +def generate_f_prot(insts, c_ptr) + print "#{ARGV[0]}_instruction #{ARGV[0]}_decode(#{c_ptr} *address)" +end + +def generate_header(insts, inst_len) + puts "#ifndef __#{ARGV[0].upcase}_PIE_DECODER_H__" + puts "#define __#{ARGV[0].upcase}_PIE_DECODER_H__" + puts "#include " + puts "typedef enum {" + insts.each do |inst| + puts " #{ARGV[0].upcase}_#{inst[:name].upcase}," + end + puts " #{ARGV[0].upcase}_INVALID" + puts "} #{ARGV[0]}_instruction;" + generate_f_prot(insts, inst_len_to_cptr(inst_len)) + puts ";" + puts "#endif" +end + +def select_bit(instructions, allowed_bits) + bit = 0 + selected_bit = -1 + selected_bit_count = 0 + + while (allowed_bits > 0) + cur_bit_mask = (0x80000000 >> bit) + + if ((allowed_bits & cur_bit_mask) != 0) + count = 0 + instructions.each do |instruction| + set_bits = instruction[:bitmask_set_bits] + count += 1 if ((set_bits & cur_bit_mask) != 0) + end + if (count > selected_bit_count) + selected_bit = bit + selected_bit_count = count + end + end + + allowed_bits &= ~cur_bit_mask + bit += 1 + end + + return selected_bit +end + +def build_tree(instructions, remaining_bits, var_inst_len) + if (instructions.size == 0) + return nil + end + + if (instructions.size == 1 and ((instructions[0][:bitmask_set_bits] & remaining_bits) == 0)) + node = Node.new + node.instruction = instructions[0] + return node + end + + progress = false + bit = -1 + if (var_inst_len) + if ((remaining_bits & 0xFFFF0000) != 0) + bit = select_bit(instructions, remaining_bits & 0xFFFF0000) + end + + if bit < 0 + bit = select_bit(instructions, remaining_bits & 0xFFFF) + end + else + bit = select_bit(instructions, remaining_bits) + end + + if (bit >= 0) + left = [] + right = [] + + instructions.each do |instruction| + if (instruction[:bitmap][bit] == '0') + left.push(instruction) + progress = true + elsif (instruction[:bitmap][bit] == '1') + right.push(instruction) + progress = true + elsif (instruction[:bitmap][bit].match(/[a-z]/)) + left.push(instruction) + right.push(instruction) + else + warn max_word_length + warn instructions.inspect + abort "Unknown bit value in bit #{bit} in " + instruction[:bitmap] + " in " + instruction[:name] + end + end + end + + node = Node.new + node.depth = bit + + #terminate after scanning the whole instruction word + unless (progress) + most_specific = 0 + i = nil + instructions.each do |instruction| + count = instruction[:bitmap].count("01") + if count > most_specific + most_specific = count + i = instruction + end + end + + node.instruction = i + return node + end + + remaining_bits &= ~(0x80000000 >> bit) + node.left = build_tree(left, remaining_bits, var_inst_len) + node.right = build_tree(right, remaining_bits, var_inst_len) + return node +end + +def indent(depth) + (0..depth).each do |i| + print " " + end +end + +def generate_c(node, depth, def_inst_width, sub) + indent(depth) + if (node == nil) + puts "return #{ARGV[0].upcase}_INVALID;" + return + end + if (node.instruction) + puts "// #{node.instruction[:bitmap].gsub(/[a-z]/, 'x')}" + indent(depth) + puts "return #{ARGV[0].upcase}_#{node.instruction[:name].to_s.upcase};" + return + end + + if ((node.depth - sub) >= def_inst_width) + puts "instruction = *(++address);" + sub += def_inst_width + indent(depth) + end + puts "if ((instruction & (1 << #{(def_inst_width - (node.depth - sub) -1)})) == 0) {" + generate_c(node.left, depth+1, def_inst_width, sub) + indent(depth) + puts "} else {" + generate_c(node.right, depth+1, def_inst_width, sub) + indent(depth) + puts "}" +end + +def get_field_width(inst, field_label) + return inst[:bitmap].count(field_label) +end + +def inst_set_field(inst, field_label, field_width, val) + index = -1 + while (index = inst[:bitmap].index(field_label, index + 1)) + field_width -= 1 + inst[:bitmap][index] = ((val >> field_width) & 1).to_s(2); + end +end + +def handle_cond_field(inst) + insts = [] + return insts unless inst[:fields] + + inst[:fields].each do |field_label, field| + if field[:cond] + field_width = get_field_width(inst, field_label) + (0...(1 << field_width)).each do |value| + is_valid = false + if field[:cond] == :diff && !field[:cond_vals].include?(value) + is_valid = true + end + if field[:cond] == :eq && field[:cond_vals].include?(value) + is_valid = true + end + + if is_valid + new_inst = inst.dup + new_inst[:bitmap] = inst[:bitmap].dup + new_inst[:fields] = new_inst[:fields].dup + new_inst[:fields].each do |fl, f| + new_inst[:fields][fl] = new_inst[:fields][fl].dup + end + new_inst[:fields][field_label].delete(:cond) + new_inst[:fields][field_label].delete(:cond_vals) + inst_set_field(new_inst, field_label, field_width, value) + insts.push(new_inst) + end + end + break + end + end + + results = [] + insts.each do |new_inst| + t_insts = handle_cond_field(new_inst) + if t_insts.size > 0 + results.concat(t_insts) + else + results.push(new_inst) + end + end + + return results +end + +def generate_decoder(raw_insts, inst_len) + max_word_length = get_max_inst_len(raw_insts) + if (inst_len != max_word_length && inst_len*2 != max_word_length) + abort "Unsupported configuration (#{inst_len}, #{max_word_length})" + end + var_inst_len = (inst_len != max_word_length) + + insts = [] + raw_insts.each do |inst| + new_insts = handle_cond_field(inst) + if new_insts.size > 0 + insts.concat(new_insts) + else + insts.push(inst) + end + end + + insts.each do |inst| + inst[:bitmask_set_bits] = inst[:bitmap].gsub('0','1').gsub(/[a-z]/, '0').to_i(2) + inst[:bitmask_value] = inst[:bitmap].gsub(/[a-z]/, '0').to_i(2) + + if (inst[:bitmap].size < max_word_length) + inst[:bitmask_set_bits] = inst[:bitmask_set_bits] << inst_len + inst[:bitmask_value] = inst[:bitmask_set_bits] << inst_len + end + end + + c_ptr = inst_len_to_cptr(inst_len) + puts "#include \"pie-#{ARGV[0]}-decoder.h\"\n\n" + generate_f_prot(insts, c_ptr) + puts " {" + puts " #{c_ptr} instruction = *address;" + tree = build_tree(insts, (1 << max_word_length) - 1, var_inst_len) + generate_c(tree, 0, inst_len, 0) + puts "}" +end + +is_header = ARGV[1...ARGV.size].include?("header") +swaphw = ARGV[1...ARGV.size].include?("swaphw") + +insts = process_insts(ARGV[0] + ".txt", swaphw) + +inst_len = get_min_inst_len(insts) + +if (is_header) + generate_header(insts, inst_len) +else + generate_decoder(insts, inst_len) +end + diff --git a/pie/generate_encoder.rb b/pie/generate_encoder.rb new file mode 100644 index 00000000..522545bc --- /dev/null +++ b/pie/generate_encoder.rb @@ -0,0 +1,117 @@ +=begin + +This file is part of PIE, an instruction encoder / decoder generator: + https://github.com/beehive-lab/pie + +Copyright 2011-2016 Cosmin Gorgovan +Copyright 2017-2021 The University of Manchester + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +=end + +require './generate_common.rb' + +def has_cond_field(inst) + inst[:fields].each_pair do |field_label, field| + return true if field[:name] == "auto_cond" + end + return false +end + +def generate_f_prot(inst, inst_len, cond) + prot = "void #{ARGV[0]}_#{inst[:name]}" + prot += "_cond" if has_cond_field(inst) and cond + prot += " (\n" + prot += "\t#{inst_len_to_cptr(inst_len)} **address" + + inst[:fields].each_pair do |field_label, field| + prot += ",\n\tunsigned int #{field[:name]}" unless (field[:name] == "auto_cond" && !cond) + end + + prot += "\n)" + + return prot +end + +def generate_f_body(inst, def_inst_len, cond, swaphw) + body = "{\n" + body += "\t// #{inst[:bitmap]}\n" + body += "\t#{inst_len_to_cptr(inst[:bitmap].size)} inst = 0x" + + fixed_fields = inst[:bitmap].gsub(/[a-z]/, '0').to_i(2).to_s(16) + body += fixed_fields + + inst[:fields].each_pair do |label, field| + if field[:name] == "auto_cond" and !cond + body += " | (14 << #{get_field_shift(inst[:bitmap], label)})" + else + body += " | ((#{field[:name]} & #{get_field_mask(inst[:bitmap], label)}) << #{get_field_shift(inst[:bitmap], label)})" + end + end + + body += ";\n\t" + if (inst[:bitmap].size == def_inst_len) + body += "**address = inst;\n" + elsif (inst[:bitmap].size == def_inst_len*2) + body += "*(*address#{swaphw ? ' + 1' : ''}) = (#{inst_len_to_cptr(def_inst_len)})(inst >> #{def_inst_len});\n" + bitmask = ((1 << def_inst_len) - 1).to_s(16) + body += "\t*(*address#{swaphw ? '' : ' + 1'}) = (#{inst_len_to_cptr(def_inst_len)})(inst & 0x#{bitmask});\n" + else + abort "Unknown instruction inst word length" + end + + body += "}" + + return body +end + +def generate_encoder(insts, inst_len, is_header, swaphw) + insts.each do |inst| + if has_cond_field(inst) + print generate_f_prot(inst, inst_len, true) + puts ";" if is_header + puts generate_f_body(inst, inst_len, true, swaphw) unless is_header + end + print generate_f_prot(inst, inst_len, false) + puts ";" if is_header + puts generate_f_body(inst, inst_len, false, swaphw) unless is_header + end +end + +def generate_header(insts, inst_len) + puts "#ifndef __#{ARGV[0].upcase}_PIE_ENCODER_H__" + puts "#define __#{ARGV[0].upcase}_PIE_ENCODER_H__" + puts "#include " + + generate_encoder(insts, inst_len, true, false) + + puts "#endif" +end + +def generate_all(insts, inst_len, swaphw) + puts "#include \"pie-#{ARGV[0]}-encoder.h\"" + + generate_encoder(insts, inst_len, false, swaphw) +end + +is_header = ARGV[1...ARGV.size].include?("header") +swaphw = ARGV[1...ARGV.size].include?("swaphw") + +insts = process_all(ARGV[0] + ".txt", false) +inst_len = get_min_inst_len(insts) +if (is_header) + generate_header(insts, inst_len) +else + generate_all(insts, inst_len, swaphw) +end diff --git a/pie/generate_field-decoder.rb b/pie/generate_field-decoder.rb new file mode 100644 index 00000000..4f8d989e --- /dev/null +++ b/pie/generate_field-decoder.rb @@ -0,0 +1,102 @@ +=begin + +This file is part of PIE, an instruction encoder / decoder generator: + https://github.com/beehive-lab/pie + +Copyright 2011-2016 Cosmin Gorgovan +Copyright 2017-2021 The University of Manchester + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +=end + +require './generate_common.rb' + +def generate_f_prot(inst, inst_len) + prot = "void #{ARGV[0]}_#{inst[:name]}_decode_fields" + prot += " (\n" + prot += "\t#{inst_len_to_cptr(inst_len)} *address" + + inst[:fields].each_pair do |field_label, field| + next if field[:name] == "auto_cond" + prot += ",\n\tunsigned int *#{field[:name]}" + end + + prot += ")" + + return prot +end + +def generate_f_body(inst, def_inst_len, swaphw) + body = "\n{\n" + + if (inst[:bitmap].size == def_inst_len) + body += "\t#{inst_len_to_cptr(inst[:bitmap].size)} instruction = *address;\n" + elsif (inst[:bitmap].size == def_inst_len * 2) + if (swaphw) + body += "\t#{inst_len_to_cptr(inst[:bitmap].size)} instruction = (*(address + 1) << #{def_inst_len}) | *address;\n" + else + body += "\t#{inst_len_to_cptr(inst[:bitmap].size)} instruction = (*address << #{def_inst_len}) | *(address + 1);\n" + end + else + abort "Unknown instruction inst word length" + end + + inst[:fields].each_pair do |label, field| + next if field[:name] == "auto_cond" + shift = get_field_shift(inst[:bitmap], label) + mask = get_field_mask(inst[:bitmap], label) + body += "\t*#{field[:name]} = (instruction >> #{shift}) & #{mask};\n" + end + + body += "}" + + return body +end + +def generate_field_decoder(insts, inst_len, is_header, swaphw) + insts.each do |inst| + # skip instructions with no arguments + next if inst[:fields].size == 0 or (inst[:fields].size == 1 && inst[:fields].first[1][:name] == "auto_cond") + print generate_f_prot(inst, inst_len) + puts ";" if is_header + puts generate_f_body(inst, inst_len, swaphw) unless is_header + end +end + +def generate_header(insts, inst_len) + puts "#ifndef __#{ARGV[0].upcase}_PIE_FIELD_DECODER_H__" + puts "#define __#{ARGV[0].upcase}_PIE_FIELD_DECODER_H__" + puts "#include " + + generate_field_decoder(insts, inst_len, true, false) + + puts "#endif" +end + +def generate_all(insts, inst_len, swaphw) + puts "#include \"pie-#{ARGV[0]}-field-decoder.h\"" + + generate_field_decoder(insts, inst_len, false, swaphw) +end + +is_header = ARGV[1...ARGV.size].include?("header") +swaphw = ARGV[1...ARGV.size].include?("swaphw") + +insts = process_all(ARGV[0] + ".txt", false) +inst_len = get_min_inst_len(insts) +if (is_header) + generate_header(insts, inst_len) +else + generate_all(insts, inst_len, swaphw) +end diff --git a/pie/makefile b/pie/makefile new file mode 100644 index 00000000..c05b5e90 --- /dev/null +++ b/pie/makefile @@ -0,0 +1,44 @@ +CFLAGS= -Os -Wall -g -std=c99 #-DPIE_AUTOINC + +C_ARCH = $(shell $(CC) -dumpmachine | awk -F '-' '{print $$1}') +ifeq ($(findstring arm, $(C_ARCH)), arm) + NATIVE_TARGETS = arm thumb +endif +ifeq ($(C_ARCH),aarch64) + NATIVE_TARGETS = a64 +endif +ifeq ($(C_ARCH),riscv64) + NATIVE_TARGETS = riscv +endif + +ifeq ($(ARCH),riscv) + OPTS=swaphw +endif + +.SECONDARY: +.PHONY: native print_arch all pie clean + +native: print_arch $(NATIVE_TARGETS) + +print_arch: + $(info PIE: detected architecture "$(C_ARCH)") + +all: thumb arm a64 riscv + +%: + $(MAKE) --no-print-directory ARCH=$@ pie + +pie: pie-$(ARCH)-decoder.o pie-$(ARCH)-encoder.o pie-$(ARCH)-field-decoder.o + +pie-$(ARCH)-%.o: pie-$(ARCH)-%.c pie-$(ARCH)-%.h + $(CC) -c $(CFLAGS) $< -o $@ + +pie-$(ARCH)-%.h: generate_%.rb $(ARCH).txt + ruby $< $(ARCH) header $(OPTS) > $@ + +pie-$(ARCH)-%.c: generate_%.rb $(ARCH).txt + ruby $< $(ARCH) $(OPTS) > $@ + +clean: + rm -f *.o pie-arm-*.h pie-thumb-*.h pie-a64-*.h pie-riscv-*.h pie-*.c + diff --git a/pie/riscv.txt b/pie/riscv.txt new file mode 100644 index 00000000..7a7265d4 --- /dev/null +++ b/pie/riscv.txt @@ -0,0 +1,291 @@ +# +# This file is part of PIE, an instruction encoder / decoder generator: +# https://github.com/beehive-lab/pie +# +# Copyright 2020 Guillermo Callaghan +# Copyright 2020-2021 The University of Manchester +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# +# Risc -V Compressed Instructions +# Several instructions are only valid for certain operands; when invalid, they +# are marked: +# * RES to indicate that the opcode is reserved for future standard extensions +# * NSE to indicate that the opcode is reserved for custom extensions +# * HINT to indicate that the opcode is reserved for microarchitectural hints. +# +# +# RVC Standard Extension for Compressed Instructions -- RVC 2.0 Ratified +# Instruction listing for RVC, Quadrant 0 +c_illegal 00000000 00000000 +c_addi4spn 000aaaaa aaabbb00, b:rd, a:nzuimm:!:0 # (RES, nzuimm=0) +c_fld 001aaabb bccddd00, d:f_rd, b:rs1, a:uimmhi, c:uimmlo # RV32/64 +#c_lq 001aaabb bccddd00, d:rd, b:rs1, a:uimmhi, c:uimmlo # RV128 +c_lw 010aaabb bccddd00, d:rd, b:rs1, a:uimmhi, c:uimmlo +#c_flw 011aaabb bccddd00, d:f_rd, b:rs1, a:uimmhi, c:uimmlo # RV32 +c_ld 011aaabb bccddd00, d:rd, b:rs1, a:uimmhi, c:uimmlo # RV64/128 +c_fsd 101aaabb bccddd00, d:f_rs2, b:rs1, a:uimmhi, c:uimmlo # RV32/64 +#c_sq 101aaabb bccddd00, d:rs2, b:rs1, a:uimmhi, c:uimmlo # RV128 +c_sw 110aaabb bccddd00, d:rs2, b:rs1, a:uimmhi, c:uimmlo +#c_fsw 111aaabb bccddd00, d:f_rs2, b:rs1, a:uimmhi, c:uimmlo # RV32 +c_sd 111aaabb bccddd00, d:rs2, b:rs1, a:uimmhi, c:uimmlo # RV64/128 +# +# Instruction listing for RVC, Quadrant 1 +# | 15 14 13 | 12 | 11 10 | 9 8 7 | 6 5 | 4 3 2 | 1 0 | +# Reserved | 1 0 0 | 1 | 1 1 | --- | 1 0 | -- | 0 1 | +# Reserved | 1 0 0 | 1 | 1 1 | --- | 1 1 | -- | 0 1 | +c_nop 000a0000 0bbbbb01, a:nzimmhi, b:nzimmlo # (HINT, nzimm != 0) +c_addi 000abbbb bccccc01, b:rs1_rd:!:0, a:nzimmhi, c:nzimmlo # (HINT, nzimm=0) +c_jal 001aaaaa aaaaaa01, a:imm # (RV32) +c_addiw 001abbbb bccccc01, b:rs1_rd:!:0, a:nzimmhi, c:nzimmlo # (RV64/128; RES, rd=0) +c_li 010abbbb bccccc01, b:rd:!:0, a:nzimmhi, c:nzimmlo # (HINT, rd=0) +c_addi16sp 011a0001 0bbbbb01, a:nzimmhi, b:nzimmlo # (RES, nzimm=0) +c_lui 011abbbb bccccc01, b:rd:!:00000:00010, a:nzimmhi, c:nzimmlo # (RES, nzimm=0; HINT, rd=0) +c_srli 100a00bb bccccc01, b:rs1_rd, a:nzuimmhi, c:nzuimmlo # (RV32 NSE, nzuimm[5]=1) +#c_srli64 100000aa a0000001, a:rs1_rd # (RV128; RV32/64 HINT) +c_srai 100a01bb bccccc01, b:rs1_rd, a:nzuimmhi, c:nzuimmlo # (RV32 NSE, nzuimm[5]=1) +#c_srai64 100001aa a0000001, a:rs1_rd # (RV128; RV32/64 HINT) +c_andi 100a10bb bccccc01, b:rs1_rd, a:immhi, c:immlo +c_sub 100011aa a00bbb01, a:rs1_rd, b:rs2 +c_xor 100011aa a01bbb01, a:rs1_rd, b:rs2 +c_or 100011aa a10bbb01, a:rs1_rd, b:rs2 +c_and 100011aa a11bbb01, a:rs1_rd, b:rs2 +c_subw 100111aa a00bbb01, a:rs1_rd, b:rs2 # (RV64/128; RV32 RES) +c_addw 100111aa a01bbb01, a:rs1_rd, b:rs2 # (RV64/128; RV32 RES) +c_j 101aaaaa aaaaaa01, a:imm +c_beqz 110aaabb bccccc01, b:rs1, a:immhi, c:immlo +c_bnez 111aaabb bccccc01, b:rs1, a:immhi, c:immlo +# +# Instruction listing for RVC, Quadrant 2 +c_slli 000abbbb bccccc10, b:rs1_rd:!:0, a:nzuimmhi, c:nzuimmlo # (HINT, rd=0; RV32 NSE, nzuimm[5]=1) +#c_slli64 0000aaaa a0000010, a:rs1_rd:!:0 # (RV128; RV32/64 HINT; HINT, rd=0) +c_fldsp 001abbbb bccccc10, b:rd, a:uimmhi, c:uimmlo # (RV32/64) +#c_lqsp 001abbbb bccccc10, b:rd:!:0, a:uimmhi, c:uimmlo # (RV128; RES, rd=0) +c_lwsp 010abbbb bccccc10, b:rd:!:0, a:uimmhi, c:uimmlo # (RES, rd=0) +c_flwsp 011abbbb bccccc10, b:rd, a:uimmhi, c:uimmlo # (RV32) +c_ldsp 011abbbb bccccc10, b:rd:!:0, a:uimmhi, c:uimmlo # (RV64/128; RES, rd=0) +c_jr 1000aaaa a0000010, a:rs1:!:0 # (RES, rs1=0) +c_mv 1000aaaa abbbbb10, a:rd:!:0, b:rs2:!:0 # (HINT, rd=0) +c_ebreak 10010000 00000010 +c_jalr 1001aaaa a0000010, a:rs1:!:0 +c_add 1001aaaa abbbbb10, a:rs1_rd:!:0, b:rs2:!:0 # (HINT, rd=0) +c_fsdsp 101aaaaa abbbbb10, b:rs2, a:uimm # (RV32/64) +#c_sqsp 101aaaaa abbbbb10, b:rs2, a:uimm # (RV128) +c_swsp 110aaaaa abbbbb10, b:rs2, a:uimm +#c_fswsp 111aaaaa abbbbb10, b:rs2, a:uimm # (RV32) +c_sdsp 111aaaaa abbbbb10, b:rs2, a:uimm # (RV64/128) +# +# +# +# These instruction are created from: +# The RISC-V Instruction Set Manual +# Volume I: Unprivileged ISA +# Document Version 20191213 +# +# RV32I Base Integer Instruction Set -- RV32I 2.1 Ratified +lui aaaaaaaa aaaaaaaa aaaabbbb b0110111, b:rd, a:imm +auipc aaaaaaaa aaaaaaaa aaaabbbb b0010111, b:rd, a:imm +jal aaaaaaaa aaaaaaaa aaaabbbb b1101111, b:rd, a:imm +jalr aaaaaaaa aaaabbbb b000cccc c1100111, c:rd, b:rs1, a:imm +beq aaaaaaab bbbbcccc c000dddd d1100011, c:rs1, b:rs2, a:immhi, d:immlo +bne aaaaaaab bbbbcccc c001dddd d1100011, c:rs1, b:rs2, a:immhi, d:immlo +blt aaaaaaab bbbbcccc c100dddd d1100011, c:rs1, b:rs2, a:immhi, d:immlo +bge aaaaaaab bbbbcccc c101dddd d1100011, c:rs1, b:rs2, a:immhi, d:immlo +bltu aaaaaaab bbbbcccc c110dddd d1100011, c:rs1, b:rs2, a:immhi, d:immlo +bgeu aaaaaaab bbbbcccc c111dddd d1100011, c:rs1, b:rs2, a:immhi, d:immlo +lb aaaaaaaa aaaabbbb b000cccc c0000011, c:rd, b:rs1, a:imm +lh aaaaaaaa aaaabbbb b001cccc c0000011, c:rd, b:rs1, a:imm +lw aaaaaaaa aaaabbbb b010cccc c0000011, c:rd, b:rs1, a:imm +lbu aaaaaaaa aaaabbbb b100cccc c0000011, c:rd, b:rs1, a:imm +lhu aaaaaaaa aaaabbbb b101cccc c0000011, c:rd, b:rs1, a:imm +sb aaaaaaab bbbbcccc c000dddd d0100011, b:rs2, c:rs1, a:immhi, d:immlo +sh aaaaaaab bbbbcccc c001dddd d0100011, b:rs2, c:rs1, a:immhi, d:immlo +sw aaaaaaab bbbbcccc c010dddd d0100011, b:rs2, c:rs1, a:immhi, d:immlo +addi aaaaaaaa aaaabbbb b000cccc c0010011, c:rd, b:rs1, a:imm +slti aaaaaaaa aaaabbbb b010cccc c0010011, c:rd, b:rs1, a:imm +sltiu aaaaaaaa aaaabbbb b011cccc c0010011, c:rd, b:rs1, a:imm +xori aaaaaaaa aaaabbbb b100cccc c0010011, c:rd, b:rs1, a:imm +ori aaaaaaaa aaaabbbb b110cccc c0010011, c:rd, b:rs1, a:imm +andi aaaaaaaa aaaabbbb b111cccc c0010011, c:rd, b:rs1, a:imm +slli 000000aa aaaabbbb b001cccc c0010011, c:rd, b:rs1, a:shamt # rv32i/rv64i shamt[5] must be 0 for rv32i +srli 000000aa aaaabbbb b101cccc c0010011, c:rd, b:rs1, a:shamt # rv32i/rv64i shamt[5] must be 0 for rv32i +srai 010000aa aaaabbbb b101cccc c0010011, c:rd, b:rs1, a:shamt # rv32i/rv64i shamt[5] must be 0 for rv32i +add 0000000a aaaabbbb b000cccc c0110011, c:rd, b:rs1, a:rs2 +sub 0100000a aaaabbbb b000cccc c0110011, c:rd, b:rs1, a:rs2 +sll 0000000a aaaabbbb b001cccc c0110011, c:rd, b:rs1, a:rs2 +slt 0000000a aaaabbbb b010cccc c0110011, c:rd, b:rs1, a:rs2 +sltu 0000000a aaaabbbb b011cccc c0110011, c:rd, b:rs1, a:rs2 +xor 0000000a aaaabbbb b100cccc c0110011, c:rd, b:rs1, a:rs2 +srl 0000000a aaaabbbb b101cccc c0110011, c:rd, b:rs1, a:rs2 +sra 0100000a aaaabbbb b101cccc c0110011, c:rd, b:rs1, a:rs2 +or 0000000a aaaabbbb b110cccc c0110011, c:rd, b:rs1, a:rs2 +and 0000000a aaaabbbb b111cccc c0110011, c:rd, b:rs1, a:rs2 +fence aaaabbbb cccc0000 00000000 00001111, a:fm, b:pred, c:succ +ecall 00000000 00000000 00000000 01110011 +ebreak 00000000 00010000 00000000 01110011 +# +# RV64I Base Integer Instruction Set (in addition to RV32I) -- RV64I 2.1 Ratified +# SLLI, SRLI and SRAI are declared in RV32I, where the shamt field was extended one bit. +lwu aaaaaaaa aaaabbbb b110cccc c0000011, c:rd, b:rs1, a:imm +ld aaaaaaaa aaaabbbb b011cccc c0000011, c:rd, b:rs1, a:imm +sd aaaaaaab bbbbcccc c011dddd d0100011, b:rs2, c:rs1, a:immhi, d:immlo +addiw aaaaaaaa aaaabbbb b000cccc c0011011, c:rd, b:rs1, a:imm +slliw 0000000a aaaabbbb b001cccc c0011011, c:rd, b:rs1, a:shamt +srliw 0000000a aaaabbbb b101cccc c0011011, c:rd, b:rs1, a:shamt +sraiw 0100000a aaaabbbb b101cccc c0011011, c:rd, b:rs1, a:shamt +addw 0000000a aaaabbbb b000cccc c0111011, c:rd, b:rs1, a:rs2 +subw 0100000a aaaabbbb b000cccc c0111011, c:rd, b:rs1, a:rs2 +sllw 0000000a aaaabbbb b001cccc c0111011, c:rd, b:rs1, a:rs2 +srlw 0000000a aaaabbbb b101cccc c0111011, c:rd, b:rs1, a:rs2 +sraw 0100000a aaaabbbb b101cccc c0111011, c:rd, b:rs1, a:rs2 +# +# RV32/RV64 Zifencei Standard Extension for Instruction-Fetch Fence, -- Zifencei 2.0 Ratified +fencei 00000000 00000000 00010000 00001111 +# +# RV32/RV64 Zicsr Standard Extension for Control and Status Register Instructions,-- Zicsr 2.0 Ratified +csrrw aaaaaaaa aaaabbbb b001cccc c1110011, c:rd, a:csr_reg, b:rs1 +csrrs aaaaaaaa aaaabbbb b010cccc c1110011, c:rd, a:csr_reg, b:rs1 +csrrc aaaaaaaa aaaabbbb b011cccc c1110011, c:rd, a:csr_reg, b:rs1 +csrrwi aaaaaaaa aaaabbbb b101cccc c1110011, c:rd, a:csr_reg, b:uimm +csrrsi aaaaaaaa aaaabbbb b110cccc c1110011, c:rd, a:csr_reg, b:uimm +csrrci aaaaaaaa aaaabbbb b111cccc c1110011, c:rd, a:csr_reg, b:uimm +# +# RV32M Standard Extension for Integer Multiplication and Division-- RV32M 2.0 Ratified +mul 0000001a aaaabbbb b000cccc c0110011, c:rd, b:rs1, a:rs2 +mulh 0000001a aaaabbbb b001cccc c0110011, c:rd, b:rs1, a:rs2 +mulhsu 0000001a aaaabbbb b010cccc c0110011, c:rd, b:rs1, a:rs2 +mulhu 0000001a aaaabbbb b011cccc c0110011, c:rd, b:rs1, a:rs2 +div 0000001a aaaabbbb b100cccc c0110011, c:rd, b:rs1, a:rs2 +divu 0000001a aaaabbbb b101cccc c0110011, c:rd, b:rs1, a:rs2 +rem 0000001a aaaabbbb b110cccc c0110011, c:rd, b:rs1, a:rs2 +remu 0000001a aaaabbbb b111cccc c0110011, c:rd, b:rs1, a:rs2 +# +# RV64M Standard Extension for Integer Multiplication and Division (in addition to RV32M) -- RV64M 2.0 Ratified +mulw 0000001a aaaabbbb b000cccc c0111011, c:rd, b:rs1, a:rs2 +divw 0000001a aaaabbbb b100cccc c0111011, c:rd, b:rs1, a:rs2 +divuw 0000001a aaaabbbb b101cccc c0111011, c:rd, b:rs1, a:rs2 +remw 0000001a aaaabbbb b110cccc c0111011, c:rd, b:rs1, a:rs2 +remuw 0000001a aaaabbbb b111cccc c0111011, c:rd, b:rs1, a:rs2 +# +# RV32A Standard Extension for Atomic Instructions -- RV32A 2.1 Ratified +lr_w 00010ab0 0000cccc c010dddd d0101111, a:aq, b:rl, d:rd, c:rs1 +sc_w 00011abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoswap_w 00001abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoadd_w 00000abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoxor_w 00100abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoand_w 01100abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoor_w 01000abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amomin_w 10000abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amomax_w 10100abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amominu_w 11000abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amomaxu_w 11100abc ccccdddd d010eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +# +# RV64A Standard Extension for Atomic Instructions (in addition to RV32A) -- RV64A 2.1 Ratified +lr_d 00010ab0 0000cccc c011dddd d0101111, a:aq, b:rl, d:rd, c:rs1 +sc_d 00011abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoswap_d 00001abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoadd_d 00000abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoxor_d 00100abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoand_d 01100abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amoor_d 01000abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amomin_d 10000abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amomax_d 10100abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amominu_d 11000abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +amomaxu_d 11100abc ccccdddd d011eeee e0101111, a:aq, b:rl, e:rd, c:rs2, d:rs1 +# +# RV32F Standard Extension for Single-Precision Floating-Point -- RV32F 2.2 Ratified +flw aaaaaaaa aaaabbbb b010cccc c0000111, c:f_rd, b:rs1, a:offset +fsw aaaaaaab bbbbcccc c010dddd d0100111, b:f_rs2, c:rs1, a:offsethi, d:offsetlo +fmadd_s aaaaa00b bbbbcccc cdddeeee e1000011, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fmsub_s aaaaa00b bbbbcccc cdddeeee e1000111, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fnmsub_s aaaaa00b bbbbcccc cdddeeee e1001011, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fnmadd_s aaaaa00b bbbbcccc cdddeeee e1001111, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fadd_s 0000000a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fsub_s 0000100a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fmul_s 0001000a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fdiv_s 0001100a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fsqrt_s 01011000 0000aaaa abbbcccc c1010011, c:f_rd, a:f_rs1, b:rm +fsgnj_s 0010000a aaaabbbb b000cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fsgnjn_s 0010000a aaaabbbb b001cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fsgnjx_s 0010000a aaaabbbb b010cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fmin_s 0010100a aaaabbbb b000cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fmax_s 0010100a aaaabbbb b001cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fcvt_w_s 11000000 0000aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fcvt_wu_s 11000000 0001aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fmv_x_w 11100000 0000aaaa a000bbbb b1010011, b:rd, a:f_rs1 +feq_s 1010000a aaaabbbb b010cccc c1010011, c:rd, b:f_rs1, a:f_rs2 +flt_s 1010000a aaaabbbb b001cccc c1010011, c:rd, b:f_rs1, a:f_rs2 +fle_s 1010000a aaaabbbb b000cccc c1010011, c:rd, b:f_rs1, a:f_rs2 +fclass_s 11100000 0000aaaa a001bbbb b1010011, b:rd, a:f_rs1 +fcvt_s_w 11010000 0000aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +fcvt_s_wu 11010000 0001aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +fmv_w_x 11110000 0000aaaa a000bbbb b1010011, b:f_rd, a:rs1 +# +# RV64F Standard Extension for Single-Precision Floating-Point (in addition to RV32F) -- RV64F 2.2 Ratified +fcvt_l_s 11000000 0010aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fcvt_lu_s 11000000 0011aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fcvt_s_l 11010000 0010aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +fcvt_s_lu 11010000 0011aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +# +# RV32D Standard Extension for Double-Precision Floating-Point -- RV32D 2.2 Ratified +fld aaaaaaaa aaaabbbb b011cccc c0000111, c:f_rd, b:rs1, a:offset +fsd aaaaaaab bbbbcccc c011dddd d0100111, b:f_rs2, c:rs1, a:offsethi, d:offsetlo +fmadd_d aaaaa01b bbbbcccc cdddeeee e1000011, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fmsub_d aaaaa01b bbbbcccc cdddeeee e1000111, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fnmsub_d aaaaa01b bbbbcccc cdddeeee e1001011, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fnmadd_d aaaaa01b bbbbcccc cdddeeee e1001111, e:f_rd, c:f_rs1, b:f_rs2, a:f_rs3, d:rm +fadd_d 0000001a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fsub_d 0000101a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fmul_d 0001001a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fdiv_d 0001101a aaaabbbb bcccdddd d1010011, d:f_rd, b:f_rs1, a:f_rs2, c:rm +fsqrt_d 01011010 0000aaaa abbbcccc c1010011, c:f_rd, a:f_rs1, b:rm +fsgnj_d 0010001a aaaabbbb b000cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fsgnjn_d 0010001a aaaabbbb b001cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fsgnjx_d 0010001a aaaabbbb b010cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fmin_d 0010101a aaaabbbb b000cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fmax_d 0010101a aaaabbbb b001cccc c1010011, c:f_rd, b:f_rs1, a:f_rs2 +fcvt_s_d 01000000 0001aaaa abbbcccc c1010011, c:f_rd, a:f_rs1, b:rm +fcvt_d_s 01000010 0000aaaa abbbcccc c1010011, c:f_rd, a:f_rs1, b:rm +feq_d 1010001a aaaabbbb b010cccc c1010011, c:rd, b:f_rs1, a:f_rs2 +flt_d 1010001a aaaabbbb b001cccc c1010011, c:rd, b:f_rs1, a:f_rs2 +fle_d 1010001a aaaabbbb b000cccc c1010011, c:rd, b:f_rs1, a:f_rs2 +fclass_d 11100010 0000aaaa a001bbbb b1010011, b:rd, a:f_rs1 +fcvt_w_d 11000010 0000aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fcvt_wu_d 11000010 0001aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fcvt_d_w 11010010 0000aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +fcvt_d_wu 11010010 0001aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +# +# RV64D Standard Extension for Double-Precision Floating-Point (in addition to RV32D) -- RV64D 2.2 Ratified +fcvt_l_d 11000010 0010aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fcvt_lu_d 11000010 0011aaaa abbbcccc c1010011, c:rd, a:f_rs1, b:rm +fmv_x_d 11100010 0000aaaa a000bbbb b1010011, b:rd, a:f_rs1 +fcvt_d_l 11010010 0010aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +fcvt_d_lu 11010010 0011aaaa abbbcccc c1010011, c:f_rd, a:rs1, b:rm +fmv_d_x 11110010 0000aaaa a000bbbb b1010011, b:f_rd, a:rs1 + +# +# Generic instruction types +# +branch aaaaaaab bbbbcccc cdddeeee e1100011, d:funct3, c:rs1, b:rs2, a:immhi, e:immlo +# +# TODO: fix the argument order to match the instruction defs +# +#c_branch 110aaabb bccccc01, b:rs1, a:immhi, c:immlo +#r_type aaaaaaab bbbbcccc cdddeeee efffffff, a:funct7, b:rs2, c:rs1, d:funct3, e:rd, f:opcode +#i_type aaaaaaaa aaaabbbb bcccdddd deeeeeee, a:imm, b:rs1, c:funct3, d:rd, e:opcode +#s_type aaaaaaab bbbbcccc cdddeeee efffffff, a:immhi, b:rs2, c:rs1, d:funct3, e:immlo, f:opcode +#b_type aaaaaaab bbbbcccc cdddeeee efffffff, a:immhi, b:rs2, c:rs1, d:funct3, e:immlo, f:opcode +#u_type aaaaaaaa aaaaaaaa aaaabbbb bccccccc, a:imm, b:rd, c:opcode # U and J are the same +#j_type aaaaaaaa aaaaaaaa aaaabbbb bccccccc, a:imm, b:rd, c:opcode # the encoding of imm is different diff --git a/pie/thumb.txt b/pie/thumb.txt new file mode 100644 index 00000000..babd3924 --- /dev/null +++ b/pie/thumb.txt @@ -0,0 +1,665 @@ +# +# This file is part of PIE, an instruction encoder / decoder generator: +# https://github.com/beehive-lab/pie +# +# Copyright 2011-2016 Cosmin Gorgovan +# Copyright 2017-2021 The University of Manchester +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# Suffixes: h - 16-bit instructions which allow use of the high registers (i.e. R8-R15) +# r - instructions which use Rdn, i.e. the same register as both Rd and Rn to allow encoding a larger immediate +# i - immediate +# m - the immediate is subtracted +# +# +# 16-bit Thumb instructions +# +adc16 01000001 01aaabbb, a:rm, b:rdn +add16 0001100a aabbbccc, a:rm, b:rn, c:rd +add_from_pc16 10100aaa bbbbbbbb, a:rd, b:imm8 +add_from_sp16 10101aaa bbbbbbbb, a:rd, b:imm8 +addh16 01000100 abbbbccc, a:dn, b:rm, c:rdn +addi16 0001110a aabbbccc, a:imm3, b:rn, c:rd +addri16 00110aaa bbbbbbbb, a:rdn, b:imm8 +add_sp_i16 10110000 0aaaaaaa, a:imm7 +and16 01000000 00aaabbb, a:rm, b:rdn +asr16 01000001 00aaabbb, a:rm, b:rdn +asri16 00010aaa aabbbccc, a:imm5, b:rm, c:rd +b16 11100aaa aaaaaaaa, a:imm11 +bic16 01000011 10aaabbb, a:rm, b:rdn +bkpt16 10111110 aaaaaaaa, a:imm8 +b_cond16 1101aaaa bbbbbbbb, a:condition, b:imm8 +blx16 01000111 1aaaa000, a:rm +bx16 01000111 0aaaa000, a:rm +cbnz16 101110a1 bbbbbccc, a:imm1, b:imm5, c:rn +cbz16 101100a1 bbbbbccc, a:imm1, b:imm5, c:rn +cmn16 01000010 11aaabbb, a:rm, b:rdn +cmp16 01000010 10aaabbb, a:rm, b:rdn +cmph16 01000101 abbbbccc, a:dn, b:rm, c:rdn +cmpri16 00101aaa bbbbbbbb, a:rdn, b:imm8 +eor16 01000000 01aaabbb, a:rm, b:rdn +it16 10111111 aaaabbbb, a:cond, b:mask +ldmfd16 11001aaa bbbbbbbb, a:rn, b:reglist +ldr16 0101100a aabbbccc, a:rm, b:rn, c:rd +ldrb16 0101110a aabbbccc, a:rm, b:rn, c:rd +ldrbi16 01111aaa aabbbccc, a:imm5, b:rn, c:rd +ldrh16 0101101a aabbbccc, a:rm, b:rn, c:rd +ldrhi16 10001aaa aabbbccc, a:imm5, b:rn, c:rd +ldri16 01101aaa aabbbccc, a:imm5, b:rn, c:rd +ldr_pc_16 01001aaa bbbbbbbb, a:rd, b:imm8 +ldrsb16 0101011a aabbbccc, a:rm, b:rn, c:rd +ldrsh16 0101111a aabbbccc, a:rm, b:rn, c:rd +ldr_sp16 10011aaa bbbbbbbb, a:rd, b:imm8 +lsl16 01000000 10aaabbb, a:rm, b:rdn +lsli16 00000aaa aabbbccc, a:imm5, b:rm, c:rd +lsr16 01000000 11aaabbb, a:rm, b:rdn +lsri16 00001aaa aabbbccc, a:imm5, b:rm, c:rd +movh16 01000110 abbbbccc, a:dn, b:rm, c:rdn +movi16 00000000 00aaabbb, a:rm, b:rd +movri16 00100aaa bbbbbbbb, a:rdn, b:imm8 +mul16 01000011 01aaabbb, a:rm, b:rdn +mvn16 01000011 11aaabbb, a:rm, b:rdn +nop16 10111111 00000000 +orr16 01000011 00aaabbb, a:rm, b:rdn +pop16 1011110a aaaaaaaa, a:reg +push16 1011010a aaaaaaaa, a:reg +rev16 10111010 00aaabbb, a:rn, b:rd +rev1616 10111010 01aaabbb, a:rn, b:rd +revsh16 10111010 11aaabbb, a:rn, b:rd +ror16 01000001 11aaabbb, a:rm, b:rdn +rsbi16 01000010 01aaabbb, a:rm, b:rdn +sbc16 01000001 10aaabbb, a:rm, b:rdn +setend16 10110110 0101e000, e:is_bigend +setpan 10110110 0001a000, a:imm +sev16 10111111 01000000 +stmea16 11000aaa bbbbbbbb, a:rn, b:reglist +str16 0101000a aabbbccc, a:rm, b:rn, c:rd +strb16 0101010a aabbbccc, a:rm, b:rn, c:rd +strbi16 01110aaa aabbbccc, a:imm5, b:rn, c:rd +strh16 0101001a aabbbccc, a:rm, b:rn, c:rd +strhi16 10000aaa aabbbccc, a:imm5, b:rn, c:rd +stri16 01100aaa aabbbccc, a:imm5, b:rn, c:rd +str_sp16 10010aaa bbbbbbbb, a:rd, b:imm8 +sub16 0001101a aabbbccc, a:rm, b:rn, c:rd +subi16 0001111a aabbbccc, a:imm3, b:rn, c:rd +subri16 00111aaa bbbbbbbb, a:rdn, b:imm8 +sub_sp_i16 10110000 1aaaaaaa, a:imm7 +svc16 11011111 aaaaaaaa, a:imm8 +sxtb16 10110010 01aaabbb, a:rm, b:rd +sxth16 10110010 00aaabbb, a:rm, b:rd +tst16 01000010 00aaabbb, a:rm, b:rdn +udf16 11011110 aaaaaaaa, a:imm8 +uxtb16 10110010 11aaabbb, a:rm, b:rd +uxth16 10110010 10aaabbb, a:rm, b:rd +wfe16 10111111 00100000 +wfi16 10111111 00110000 +yield16 10111111 00010000 +# +# +# 32-bit Thumb instructions +# +adc32 11101011 010abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +adci32 11110a01 010bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +add32 11101011 000abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +addi32 11110a01 000bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +addwi32 11110a10 0000bbbb 0cccdddd eeeeeeee, a:imm1, b:rn, c:imm3, d:rd, e:imm8 +adrwi_post32 11110a10 1000bbbb 0cccdddd eeeeeeee, a:imm1, b:rn, c:imm3, d:rd, e:imm8 +adrwi_pre32 11110a10 0010bbbb 0cccdddd eeeeeeee, a:imm1, b:rn, c:imm3, d:rd, e:imm8 +and32 11101010 000abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +andi32 11110a00 000bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +asr32 11111010 010abbbb 1111cccc 0000dddd, a:set_flags, b:rn, c:rd, d:rm +asri32 11101010 010a1111 0bbbcccc dd10eeee, a:set_flags, b:imm3, c:rd, d:imm2, e:rm +b32 11110abb bbbbbbbb 10c1deee eeeeeeee, a:sign_bit, b:offset_high, c:j1, d:j2, e:offset_low +b_cond32 11110abb bbcccccc 10d0efff ffffffff, a:sign_bit, b:condition, c:offset_high, d:j1, e:j2, f:offset_low +bfc32 11110011 01101111 0aaabbbb cc0ddddd, a:imm3, b:rd, c:imm2, d:imm5 +bfi32 11110011 011aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +bic32 11101010 001abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +bici32 11110a00 001bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +bl32 11110abb bbbbbbbb 11c1deee eeeeeeee, a:sign_bit, b:offset_high, c:j1, d:j2, e:offset_low +bl_arm32 11110abb bbbbbbbb 11c0deee eeeeeeee, a:sign_bit, b:offset_high, c:j1, d:j2, e:offset_low +cdp32 11101110 aaaabbbb ccccdddd eee0ffff, d:coproc, a:opc1, c:crd, b:crn, f:crm, e:opc2 +cdp232 11111110 aaaabbbb ccccdddd eee0ffff, d:coproc, a:opc1, c:crd, b:crn, f:crm, e:opc2 +clrex32 11110011 10111111 10001111 0010aaaa, a:option +clz32 11111010 1011aaaa 1111bbbb 1000cccc, a:rn, b:rd, c:rm +cmn32 11101011 0001aaaa 0bbb1111 ccddeeee, a:rn, b:imm3, c:imm2, d:shift_type, e:rm +cmni32 11110a01 0001bbbb 0ccc1111 dddddddd, a:imm1, b:rn, c:imm3, d:imm8 +cmp32 11101011 1011aaaa 0bbb1111 ccddeeee, a:rn, b:imm3, c:imm2, d:shift_type, e:rm +cmpi32 11110a01 1011bbbb 0ccc1111 dddddddd, a:imm1, b:rn, c:imm3, d:imm8 +dbg32 11110011 10101111 10000000 1111aaaa, a:option +dmb32 11110011 10111111 10001111 0101aaaa, a:option +dsb32 11110011 10111111 10001111 0100aaaa, a:option +eor32 11101010 100abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +eori32 11110a00 100bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +isb32 11110011 10111111 10001111 0110aaaa, a:option +ldc32 1110110p udw1aaaa bbbbcccc eeeeeeee, c:coproc, d:d, b:crd, a:rn, p:pre_index, u:upwards, w:writeback, e:imm8 +ldc232 1111110p udw1aaaa bbbbcccc eeeeeeee, c:coproc, d:d, b:crd, a:rn, p:pre_index, u:upwards, w:writeback, e:imm8 +ldmea32 11101001 00a1bbbb cccccccc cccccccc, a:writeback, b:rn, c:reglist +ldmfd32 11101000 10a1bbbb cccccccc cccccccc, a:writeback, b:rn, c:reglist +ldr32 11111000 0101aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +ldrb32 11111000 0001aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +ldrbi32 11111000 0001cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +ldrbl32 11111000 a0011111 bbbbcccc cccccccc, b:rt, c:imm12, a:upwards +ldrbwi32 11111000 1001cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +ldrbt32 11111000 0001aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +ldrd32 1110100a b1c1dddd eeeeffff gggggggg, a:pre_index, b:upwards, c:writeback, d:rn, e:rt, f:rd, g:imm8 +ldrex32 11101000 0101aaaa bbbb1111 cccccccc, a:rn, b:rt, c:imm8 +ldrexb32 11101000 1101aaaa bbbb1111 01001111, a:rn, b:rt +ldrexd32 11101000 1101aaaa bbbbcccc 01111111, a:rn, b:rt, c:rt2 +ldrexh32 11101000 1101aaaa bbbb1111 01011111, a:rn, b:rt +ldrh32 11111000 0011aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +ldrhi32 11111000 0011cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +ldrhl32 11111000 a0111111 bbbbcccc cccccccc, b:rt, c:imm12, a:upwards +ldrhwi32 11111000 1011cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +ldrht32 11111000 0011aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +ldri32 11111000 0101cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +ldrl32 11111000 a1011111 ddddeeee eeeeeeee, d:rt, e:imm12, a:upwards +ldrsb32 11111001 0001aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +ldrsbi32 11111001 0001cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +ldrsbl32 11111001 a0011111 bbbbcccc cccccccc, b:rt, c:imm12, a:upwards +ldrsbwi32 11111001 1001cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +ldrsbt32 11111001 0001aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +ldrsh32 11111001 0011aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +ldrshi32 11111001 0011cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +ldrshl32 11111001 a0111111 bbbbcccc cccccccc, b:rt, c:imm12, a:upwards +ldrshwi32 11111001 1011cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +ldrsht32 11111001 0011aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +ldrt32 11111000 0101aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +ldrwi32 11111000 1101cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +lsl32 11111010 000abbbb 1111cccc 0000dddd, a:set_flags, b:rn, c:rd, d:rm +lsli32 11101010 010a1111 0bbbcccc dd00eeee, a:set_flags, b:imm3, c:rd, d:imm2, e:rm +lsr32 11111010 001abbbb 1111cccc 0000dddd, a:set_flags, b:rn, c:rd, d:rm +lsri32 11101010 010a1111 0bbbcccc dd01eeee, a:set_flags, b:imm3, c:rd, d:imm2, e:rm +mcr32 11101110 aaa0bbbb ccccdddd eee1ffff, a:opc1, b:crn, c:rt, d:coproc, e:opc2, f:crm +mcr232 11111110 aaa0bbbb ccccdddd eee1ffff, a:opc1, b:crn, c:rt, d:coproc, e:opc2, f:crm +mcrr32 11101100 0100aaaa bbbbcccc ddddeeee, c:coproc, d:opc1, b:rt, a:rt2, e:crm +mcrr232 11111100 0100aaaa bbbbcccc ddddeeee, c:coproc, d:opc1, b:rt, a:rt2, e:crm +mla32 11111011 0000aaaa bbbbcccc 0000dddd, a:rn, b:racc, c:rd, d:rm +mls32 11111011 0000aaaa bbbbcccc 0001dddd, a:rn, b:racc, c:rd, d:rm +mov32 11101010 010a1111 0000bbbb 0000cccc, a:set_flags, b:rd, c:rm +movi32 11110a00 010b1111 0cccdddd eeeeeeee, a:imm1, b:set_condition, c:imm3, d:rd, e:imm8 +movwi32 11110a10 0100bbbb 0cccdddd eeeeeeee, a:imm1, b:imm4, c:imm3, d:rd, e:imm8 +movti32 11110a10 1100bbbb 0cccdddd eeeeeeee, a:imm1, b:imm4, c:imm3, d:rd, e:imm8 +mrc32 11101110 aaa1bbbb ccccdddd eee1ffff, a:opc1, b:crn, c:rt, d:coproc, e:opc2, f:crm +mrc232 11111110 aaa1bbbb ccccdddd eee1ffff, a:opc1, b:crn, c:rt, d:coproc, e:opc2, f:crm +mrrc32 11101100 0101aaaa bbbbcccc ddddeeee, c:coproc, d:opc, b:rt, a:rt2, e:crm +mrrc232 11111100 0101aaaa bbbbcccc ddddeeee, c:coproc, d:opc, b:rt, a:rt2, e:crm +mrs32 11110011 11101111 1000aaaa 00000000, a:rd +msr32 11110011 1000bbbb 1000cc00 00000000, b:rn, c:mask +mul32 11111011 0000aaaa 1111bbbb 0000cccc, a:rn, b:rd, c:rm +mvn32 11101010 011a1111 0bbbcccc ddeeffff, a:set_flags, b:imm3, c:rd, d:imm2, e:shift_type, f:rm +mvni32 11110a00 011b1111 0cccdddd eeeeeeee, a:imm1, b:set_condition, c:imm3, d:rd, e:imm8 +nop32 11110011 10101111 10000000 00000000 +orn32 11101010 011abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +orni32 11110a00 011bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +orr32 11101010 010abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +orri32 11110a00 010bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +pkh32 11101010 1100aaaa 0bbbcccc ddeeffff, a:rn, b:imm3, c:rd, d:imm2, e:shift_type, f:rm +pld32 11111000 0001aaaa 11110000 00bbcccc, a:rn, b:shift, c:rm +pldi32 11111000 1001aaaa 1111bbbb bbbbbbbb, a:rn, b:imm12 +pldim32 11111000 0001aaaa 11111100 bbbbbbbb, a:rn, b:imm8 +pld_lit32 11111000 u0011111 1111aaaa aaaaaaaa, u:upwards, a:imm12 +pldw32 11111000 0011aaaa 11110000 00bbcccc, a:rn, b:shift, c:rm +pldwi32 11111000 1011aaaa 1111bbbb bbbbbbbb, a:rn, b:imm12 +pldwim32 11111000 0011aaaa 11111100 bbbbbbbb, a:rn, b:imm8 +pli32 11111001 0001aaaa 11110000 00bbcccc, a:rn, c:rm, b:shift +plii32 11111001 1001aaaa 1111bbbb bbbbbbbb, a:rn, b:imm12 +pliim32 11111001 0001aaaa 11111100 bbbbbbbb, a:rn, b:imm8 +pli_lit32 11111001 u0011111 1111aaaa aaaaaaaa, u:upwards, a:imm12 +qadd32 11111010 1000aaaa 1111bbbb 1000cccc, a:rn, b:rd, c:rm +qadd1632 11111010 1001aaaa 1111bbbb 0001cccc, b:rd, a:rn, c:rm +qadd832 11111010 1000aaaa 1111bbbb 0001cccc, b:rd, a:rn, c:rm +qasx32 11111010 1010aaaa 1111bbbb 0001cccc, b:rd, a:rn, c:rm +qdadd32 11111010 1000aaaa 1111bbbb 1001cccc, a:rn, b:rd, c:rm +qdsub32 11111010 1000aaaa 1111bbbb 1011cccc, a:rn, b:rd, c:rm +qsax32 11111010 1110aaaa 1111bbbb 0001cccc, b:rd, a:rn, c:rm +qsub32 11111010 1000aaaa 1111bbbb 1010cccc, a:rn, b:rd, c:rm +qsub1632 11111010 1101aaaa 1111bbbb 0001cccc, b:rd, a:rn, c:rm +qsub832 11111010 1100aaaa 1111bbbb 0001cccc, b:rd, a:rn, c:rm +rbit32 11111010 1001aaaa 1111bbbb 1010cccc, a:rn, b:rd, c:rm +rev32 11111010 1001aaaa 1111bbbb 1000cccc, a:rn, b:rd, c:rm +rev1632 11111010 1001aaaa 1111bbbb 1001cccc, a:rn, b:rd, c:rm +revsh32 11111010 1001aaaa 1111bbbb 1011cccc, a:rn, b:rd, c:rm +ror32 11111010 011abbbb 1111cccc 0000dddd, a:set_flags, b:rn, c:rd, d:rm +rori32 11101010 010a1111 0bbbcccc dd11eeee, a:set_flags, b:imm3, c:rd, d:imm2, e:rm +rrx32 11101010 010a1111 0000bbbb 0011cccc, a:set_flags, b:rd, c:rm +rsb32 11101011 110abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +rsbi32 11110a01 110bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +sadd1632 11111010 1001aaaa 1111bbbb 0000cccc, b:rd, a:rn, c:rm +sadd832 11111010 1000aaaa 1111bbbb 0000cccc, b:rd, a:rn, c:rm +sasx32 11111010 1010aaaa 1111bbbb 0000cccc, b:rd, a:rn, c:rm +sbc32 11101011 011abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +sbci32 11110a01 011bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +sbfx32 11110011 010aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +sdiv32 11111011 1001aaaa 1111bbbb 1111cccc, a:rn, b:rdhi, c:rm +sel32 11111010 1010aaaa 1111bbbb 1000cccc, a:rn, b:rd, c:rm +sev32 11110011 10101111 10000000 00000100 +shadd1632 11111010 1001aaaa 1111bbbb 0010cccc, b:rd, a:rn, c:rm +shadd832 11111010 1000aaaa 1111bbbb 0010cccc, b:rd, a:rn, c:rm +shasx32 11111010 1010aaaa 1111bbbb 0010cccc, b:rd, a:rn, c:rm +shsax32 11111010 1110aaaa 1111bbbb 0010cccc, b:rd, a:rn, c:rm +shsub1632 11111010 1101aaaa 1111bbbb 0010cccc, b:rd, a:rn, c:rm +shsub832 11111010 1100aaaa 1111bbbb 0010cccc, b:rd, a:rn, c:rm +simd_add_sub32 11111010 1aaabbbb 1111cccc 0dddeeee, a:opcode, b:rn, c:rd, d:pref, e:rm +smlabb32 11111011 0001aaaa bbbbcccc 0000eeee, c:rd, a:rn, e:rm, b:ra +smlabt32 11111011 0001aaaa bbbbcccc 0001eeee, c:rd, a:rn, e:rm, b:ra +smlatb32 11111011 0001aaaa bbbbcccc 0010eeee, c:rd, a:rn, e:rm, b:ra +smlatt32 11111011 0001aaaa bbbbcccc 0011eeee, c:rd, a:rn, e:rm, b:ra +smlad32 11111011 0010aaaa bbbbcccc ddddeeee, a:rn, b:racc, c:rd, d:opcode2, e:rm +smlal32 11111011 1100aaaa bbbbcccc 0000dddd, a:rn, b:rdlo, c:rdhi, d:rm +smlalbb32 11111011 1100aaaa bbbbcccc 1000ffff, b:rdlo, c:rdhi, a:rn, f:rm +smlalbt32 11111011 1100aaaa bbbbcccc 1001ffff, b:rdlo, c:rdhi, a:rn, f:rm +smlaltb32 11111011 1100aaaa bbbbcccc 1010ffff, b:rdlo, c:rdhi, a:rn, f:rm +smlaltt32 11111011 1100aaaa bbbbcccc 1011ffff, b:rdlo, c:rdhi, a:rn, f:rm +smlald32 11111011 1100aaaa bbbbcccc 110deeee, a:rn, b:rdlo, c:rdhi, d:m_swap, e:rm +smlawb32 11111011 0011aaaa bbbbcccc 0000dddd, c:rd, a:rn, d:rm, b:ra +smlawt32 11111011 0011aaaa bbbbcccc 0001dddd, c:rd, a:rn, d:rm, b:ra +smlsd32 11111011 0100aaaa bbbbcccc ddddeeee, a:rn, b:racc, c:rd, d:opcode2, e:rm +smlsld32 11111011 1101aaaa bbbbcccc 110deeee, a:rn, b:rdlo, c:rdhi, d:m_swap, e:rm +smmla32 11111011 0101aaaa bbbbcccc ddddeeee, a:rn, b:racc, c:rd, d:opcode2, e:rm +smmls32 11111011 0110aaaa bbbbcccc ddddeeee, a:rn, b:racc, c:rd, d:opcode2, e:rm +smmul32 11111011 0101aaaa 1111bbbb ccccdddd, a:rn, b:rd, c:opcode2, d:rm +smuad32 11111011 0010aaaa 1111bbbb ccccdddd, a:rn, b:rd, c:opcode2, d:rm +smulbb32 11111011 0001aaaa 1111bbbb 0000dddd, b:rd, a:rn, d:rm +smulbt32 11111011 0001aaaa 1111bbbb 0001dddd, b:rd, a:rn, d:rm +smultb32 11111011 0001aaaa 1111bbbb 0010dddd, b:rd, a:rn, d:rm +smultt32 11111011 0001aaaa 1111bbbb 0011dddd, b:rd, a:rn, d:rm +smull32 11111011 1000aaaa bbbbcccc 0000dddd, a:rn, b:rdlo, c:rdhi, d:rm +smulwb32 11111011 0011aaaa 1111bbbb 0000dddd, a:rn, b:rd, d:rm +smulwt32 11111011 0011aaaa 1111bbbb 0001dddd, a:rn, b:rd, d:rm +smusd32 11111011 0100aaaa 1111bbbb ccccdddd, a:rn, b:rd, c:opcode2, d:rm +ssat1632 11110011 001aaaaa 0000bbbb 00000000, a:rn, b:rd +ssat_asr32 11110011 001aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +ssat_lsl32 11110011 000aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +ssax32 11111010 1110aaaa 1111bbbb 0000cccc, b:rd, a:rn, c:rm +ssub1632 11111010 1101aaaa 1111bbbb 0000cccc, b:rd, a:rn, c:rm +ssub832 11111010 1100aaaa 1111bbbb 0000cccc, b:rd, a:rn, c:rm +stc32 1110110p udw0aaaa bbbbcccc eeeeeeee, c:coproc, d:d, b:crd, a:rn, p:pre_index, u:upwards, w:writeback, e:imm8 +stc232 1111110p udw0aaaa bbbbcccc eeeeeeee, c:coproc, d:d, b:crd, a:rn, p:pre_index, u:upwards, w:writeback, e:imm8 +stmea32 11101000 10a0bbbb cccccccc cccccccc, a:writeback, b:rn, c:reglist +stmfd32 11101001 00a0bbbb cccccccc cccccccc, a:writeback, b:rn, c:reglist +str32 11111000 0100aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +strb32 11111000 0000aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +strbi32 11111000 0000cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +strbwi32 11111000 1000cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +strbt32 11111000 0000aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +strd32 1110100a b1c0dddd eeeeffff gggggggg, a:pre_index, b:upwards, c:writeback, d:rn, e:rt, f:rd, g:imm8 +strex32 11101000 0100aaaa bbbbcccc dddddddd, a:rn, b:rt, c:rd, d:imm8 +strexb32 11101000 1100aaaa bbbb1111 0100dddd, a:rn, b:rt, d:rd +strexd32 11101000 1100aaaa bbbbcccc 0111dddd, a:rn, b:rt, c:rt2, d:rd +strexh32 11101000 1100aaaa bbbb1111 0101dddd, a:rn, b:rt, d:rd +strh32 11111000 0010aaaa bbbb0000 00ccdddd, a:rn, b:rt, c:shift, d:rm +strhi32 11111000 0010cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +strhwi32 11111000 1010cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +strht32 11111000 0010aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +stri32 11111000 0100cccc dddd1puw eeeeeeee, d:rt, c:rn, e:imm8, p:pre_index, u:upwards, w:writeback +strt32 11111000 0100aaaa bbbb1110 cccccccc, b:rt, a:rn, c:imm8 +strwi32 11111000 1100cccc ddddeeee eeeeeeee, d:rt, c:rn, e:imm12 +sub32 11101011 101abbbb 0cccdddd eeffgggg, a:set_flags, b:rn, c:imm3, d:rd, e:imm2, f:shift_type, g:rm +subi32 11110a01 101bcccc 0dddeeee ffffffff, a:imm1, b:set_condition, c:rn, d:imm3, e:rd, f:imm8 +subwi32 11110a10 1010bbbb 0cccdddd eeeeeeee, a:imm1, b:rn, c:imm3, d:rd, e:imm8 +sxtab1632 11111010 0010aaaa 1111bbbb 10ccdddd, a:rn, b:rd, c:rotate, d:rm +sxtab32 11111010 0100aaaa 1111bbbb 10ccdddd, a:rn, b:rd, c:rotate, d:rm +sxtah32 11111010 0000aaaa 1111bbbb 10ccdddd, a:rn, b:rd, c:rotate, d:rm +sxtb1632 11111010 00101111 1111aaaa 10bbcccc, a:rd, b:rotate, c:rm +sxtb32 11111010 01001111 1111aaaa 10bbcccc, a:rd, b:rotate, c:rm +sxth32 11111010 00001111 1111aaaa 10bbcccc, a:rd, b:rotate, c:rm +tbb32 11101000 1101aaaa 11110000 0000bbbb, a:rn, b:rm +tbh32 11101000 1101aaaa 11110000 0001bbbb, a:rn, b:rm +teq32 11101010 1001aaaa 0bbb1111 ccddeeee, a:rn, b:imm3, c:imm2, d:shift_type, e:rm +teqi32 11110a00 1001bbbb 0ccc1111 dddddddd, a:imm1, b:rn, c:imm3, d:imm8 +tst32 11101010 0001aaaa 0bbb1111 ccddeeee, a:rn, b:imm3, c:imm2, d:shift_type, e:rm +tsti32 11110a00 0001bbbb 0ccc1111 dddddddd, a:imm1, b:rn, c:imm3, d:imm8 +uadd1632 11111010 1001aaaa 1111bbbb 0100cccc, b:rd, a:rn, c:rm +uadd832 11111010 1000aaaa 1111bbbb 0100cccc, b:rd, a:rn, c:rm +uasx32 11111010 1010aaaa 1111bbbb 0100cccc, b:rd, a:rn, c:rm +ubfx32 11110011 110aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +udf32 11110111 1111aaaa 1010bbbb bbbbbbbb, a:imm4, b:imm12 +udiv32 11111011 1011aaaa 1111bbbb 1111cccc, a:rn, b:rdhi, c:rm +uhadd1632 11111010 1001aaaa 1111bbbb 0110cccc, b:rd, a:rn, c:rm +uhadd832 11111010 1000aaaa 1111bbbb 0110cccc, b:rd, a:rn, c:rm +uhasx32 11111010 1010aaaa 1111bbbb 0110cccc, b:rd, a:rn, c:rm +uhsax32 11111010 1110aaaa 1111bbbb 0110cccc, b:rd, a:rn, c:rm +uhsub1632 11111010 1101aaaa 1111bbbb 0110cccc, b:rd, a:rn, c:rm +uhsub832 11111010 1100aaaa 1111bbbb 0110cccc, b:rd, a:rn, c:rm +umaal32 11111011 1110aaaa bbbbcccc 0110dddd, a:rn, b:rdlo, c:rdhi, d:rm +umlal32 11111011 1110aaaa bbbbcccc 0000dddd, a:rn, b:rdlo, c:rdhi, d:rm +umull32 11111011 1010aaaa bbbbcccc 0000dddd, a:rn, b:rdlo, c:rdhi, d:rm +uqadd1632 11111010 1001aaaa 1111bbbb 0101cccc, b:rd, a:rn, c:rm +uqadd832 11111010 1000aaaa 1111bbbb 0101cccc, b:rd, a:rn, c:rm +uqasx32 11111010 1010aaaa 1111bbbb 0101cccc, b:rd, a:rn, c:rm +uqsax32 11111010 1110aaaa 1111bbbb 0101cccc, b:rd, a:rn, c:rm +uqsub1632 11111010 1101aaaa 1111bbbb 0101cccc, b:rd, a:rn, c:rm +uqsub832 11111010 1100aaaa 1111bbbb 0101cccc, b:rd, a:rn, c:rm +usad832 11111011 0111aaaa 1111bbbb ccccdddd, a:rn, b:rd, c:opcode2, d:rm +usada832 11111011 0111aaaa bbbbcccc ddddeeee, a:rn, b:racc, c:rd, d:opcode2, e:rm +usat1632 11110011 101aaaaa 0000bbbb 00000000, a:rn, b:rd +usat_asr32 11110011 101aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +usat_lsl32 11110011 100aaaaa 0bbbcccc dd0eeeee, a:rn, b:imm3, c:rd, d:imm2, e:imm5 +usax32 11111010 1110aaaa 1111bbbb 0100cccc, b:rd, a:rn, c:rm +usub1632 11111010 1101aaaa 1111bbbb 0100cccc, b:rd, a:rn, c:rm +usub832 11111010 1100aaaa 1111bbbb 0100cccc, b:rd, a:rn, c:rm +uxtab1632 11111010 0011aaaa 1111bbbb 10ccdddd, a:rn, b:rd, c:rotate, d:rm +uxtab32 11111010 0101aaaa 1111bbbb 10ccdddd, a:rn, b:rd, c:rotate, d:rm +uxtah32 11111010 0001aaaa 1111bbbb 10ccdddd, a:rn, b:rd, c:rotate, d:rm +uxtb1632 11111010 00111111 1111aaaa 10bbcccc, a:rd, b:rotate, c:rm +uxtb32 11111010 01011111 1111aaaa 10bbcccc, a:rd, b:rotate, c:rm +uxth32 11111010 00011111 1111aaaa 10bbcccc, a:rd, b:rotate, c:rm +wfe32 11110011 10101111 10000000 00000010 +wfi32 11110011 10101111 10000000 00000011 +yield32 11110011 10101111 10000000 00000001 +# +# +# VFP, NEON +# +# naming rules: if there are separate encodings for integer and fp, add _i, _f suffxies +# neon_, vfp_ prefixes +## _scal = scalar +## _hp = half precision +## _sp = single precision +## _dp = double precision +# _i = integer +# _f = floating point +## _fp = fixed point +# _core = arm core register +# i = immediate +# z = compare with immediate #0 +# +# Ordering of operands: op, is_float, unsign, size, q +# +neon_vaba 111u1111 0dssaaaa bbbb0111 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vabal 111u1111 1dssaaaa bbbb0101 n0m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vabd_i 111a1111 0bccdddd eeee0111 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vabd_f 11111111 0d1saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vabdl 111a1111 1bccdddd eeee0111 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vabs 11111111 1d11ss01 aaaa0f11 0qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm + vfp_vabs 11101110 1a110000 cccc101s 11d0eeee, s:size, a:d, c:vd, d:m, e:vm +neon_vacge 11111111 0d0saaaa bbbb1110 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vacgt 11111111 0d1saaaa bbbb1110 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vadd_i 11101111 0dssaaaa bbbb1000 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vadd_f 11101111 0d0saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vadd 11101110 0a11bbbb cccc101s d0e0ffff, s:size, a:d, c:vd, d:n, b:vn, e:m, f:vm +neon_vaddhn 11101111 1abbcccc dddd0100 e0f0gggg, b:size:!:11, a:d, e:n, d:vd, c:vn, f:m, g:vm +neon_vaddl 111a1111 1bccdddd eeee0000 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vaddw 111a1111 1bccdddd eeee0001 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vand 11101111 0a00bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vbic 11101111 0a01bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vbici 111i1111 1d000aaa bbbbcccc 0q11eeee, q:q, d:d, b:vd, c:cmode, i:i, a:imm3, e:imm4 +neon_vbif 11111111 0a11bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vbit 11111111 0a10bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vbsl 11111111 0a01bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vceq_i 11111111 0dssaaaa bbbb1000 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vceq_f 11101111 0d0saaaa bbbb1110 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vceqz 11111111 1d11ss01 aaaa0f01 0qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcge_i 111u1111 0dssaaaa bbbb0011 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcge_f 11111111 0d0saaaa bbbb1110 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcgez 11111111 1d11ss01 aaaa0f00 1qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcgt_i 111u1111 0dssaaaa bbbb0011 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcgt_f 11111111 0d1saaaa bbbb1110 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vcgtz 11111111 1d11ss01 aaaa0f00 0qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vclez 11111111 1d11ss01 aaaa0f01 1qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcls 11111111 1d11ss00 aaaa0100 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcltz 11111111 1d11ss01 aaaa0f10 0qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vclz 11111111 1d11ss00 aaaa0100 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm + vfp_vcmp 11101110 1a110100 bbbb101c 01e0ffff, c:size, a:d, b:vd, e:m, f:vm + vfp_vcmpz 11101110 1a110101 bbbb101c 01000000, c:size, a:d, b:vd + vfp_vcmpe 11101110 1a110100 bbbb101c 11e0ffff, c:size, a:d, b:vd, e:m, f:vm + vfp_vcmpez 11101110 1a110101 bbbb101c 11000000, c:size, a:d, b:vd +neon_vcnt 11111111 1d11ss00 aaaa0101 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcvt_f_i 11111111 1d11ss11 aaaa011o oqm0bbbb, o:op, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vcvt_f_fp 111u1111 1daaaaaa bbbb111o 0qm1bbbb, o:op, u:unsign, q:q, d:d, b:vd, m:m, b:vm, a:imm6:!:000000:000001:000010:000011:000100:000101:000110:000111 +neon_vcvt_hp_sp 11111111 1d11ss10 aaaa011o 00m0bbbb, o:op, s:size, d:d, a:vd, m:m, b:vm + vfp_vcvt_f_i 11101110 1d111aaa bbbb101s o1m0cccc, o:op, a:op2, s:size, d:d, b:vd, m:m, c:vm + vfp_vcvt_f_fp 11101110 1d111o1u aaaa101b c1i0eeee, o:op, u:unsign, b:sf, c:sx, d:d, a:vd, e:imm4, i:i + vfp_vcvt_dp_sp 11101110 1d110111 aaaa101s 11m0bbbb, s:size, d:d, a:vd, m:m, b:vm + vfp_vcvtb 11101110 1d11001o aaaa1010 01m0bbbb, o:op, d:d, a:vd, m:m, b:vm + vfp_vcvtt 11101110 1d11001o aaaa1010 11m0bbbb, o:op, d:d, a:vd, m:m, b:vm + vfp_vdiv 11101110 1a00bbbb cccc101s d0e0ffff, s:size, a:d, c:vd, d:n ,b:vn, e:m, f:vm +neon_vdup_scal 11111111 1a11bbbb cccc1100 0de0ffff, d:q, b:imm4, a:d, c:vd, e:m, f:vm +neon_vdup_core 11101110 1bq0aaaa cccc1011 d0e10000, b:b, e:e, q:q, d:d, a:vd, c:rt +neon_veor 11111111 0a00bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vext 11101111 1a11bbbb ccccdddd efg0hhhh, f:q, a:d, c:vd, e:n, b:vn, g:m, h:vm, d:imm4 +neon_vfma 11101111 0a0sbbbb cccc1100 nqm1dddd, s:size, q:q, a:d, c:vd, n:n, b:vn, m:m, d:vm +neon_vfmal 11111100 0a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vfmal_scal 11111110 0a00bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vfms 11101111 0a1sbbbb cccc1100 nqm1dddd, s:size, q:q, a:d, c:vd, n:n, b:vn, m:m, d:vm + vfp_vfma 11101110 1d10aaaa bbbb101s n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vfms 11101110 1d10aaaa bbbb101s n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vfmsl 11111100 1a10bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vfmsl_scal 11111110 0a01bbbb cccc1000 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm + vfp_vfnma 11101110 1d01aaaa bbbb101s n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vfnms 11101110 1d01aaaa bbbb101s n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vhadd 111a1111 0bccdddd eeee0000 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vhsub 111a1111 0bccdddd eeee0010 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm + vfp_vins 11111110 1a110000 bbbb1010 11c0dddd, a:d, b:vd, c:m, d:vm +neon_vldx_m 11111001 0a10bbbb ccccdddd eeffgggg, d:opcode, e:size, a:d, c:vd, b:rn, f:align, g:rm +neon_vldx_s_o 11111001 1a10bbbb ccccddee ffffgggg, e:opcode, d:size, a:d, c:vd, b:rn, f:index_align, g:rm +neon_vldx_s_a 11111001 1a10bbbb cccc11dd eetgffff, d:opcode, e:size, a:d, c:vd, t:inc, b:rn, g:align, f:rm + vfp_vldm_dp 1110110p udw1aaaa bbbb1011 cccccccc, p:p, u:upwards, w:writeback, a:rn, d:d, b:vd, c:imm8 + vfp_vldm_sp 1110110p udw1aaaa bbbb1010 cccccccc, p:p, u:upwards, w:writeback, a:rn, d:d, b:vd, c:imm8 + vfp_vldr_dp 11101101 ud01aaaa bbbb1011 cccccccc, u:upwards, a:rn, d:d, b:vd, c:imm8 + vfp_vldr_sp 11101101 ud01aaaa bbbb1010 cccccccc, u:upwards, a:rn, d:d, b:vd, c:imm8 +neon_vmax_i 111a1111 0bccdddd eeee0110 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vmin_i 111a1111 0bccdddd eeee0110 fgh1iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vmax_f 11101111 0d0saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmin_f 11101111 0d1saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmla_i 11101111 0abbcccc dddd1001 efg0hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vmls_i 11111111 0abbcccc dddd1001 efg0hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vmlal_i 111a1111 1bccdddd eeee1000 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vmlsl_i 111a1111 1bccdddd eeee1010 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vmla_f 11101111 0a0sbbbb cccc1101 def1gggg, s:size, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vmls_f 11101111 0a1sbbbb cccc1101 def1gggg, s:size, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm + vfp_vmla_f 11101110 0a00bbbb cccc101s d0e0ffff, s:size, a:d, c:vd, d:n, b:vn, e:m, f:vm + vfp_vmls_f 11101110 0a00bbbb cccc101s d1e0ffff, s:size, a:d, c:vd, d:n, b:vn, e:m, f:vm +neon_vmla_scal 111a1111 1bccdddd eeee000f g1h0iiii, f:is_float, c:size:!:11, a:q, b:d, e:vd, g:n, d:vn, h:m, i:vm +neon_vmls_scal 111a1111 1bccdddd eeee010f g1h0iiii, f:is_float, c:size:!:11, a:q, b:d, e:vd, g:n, d:vn, h:m, i:vm +neon_vmlal_scal 111a1111 1bccdddd eeee0010 f1g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vmlsl_scal 111a1111 1bccdddd eeee0110 f1g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vmovi 111a1111 1b000ccc ddddeeee 0fg1hhhh, f:q, b:d, d:vd, g:op, e:cmode, a:i, c:imm3, h:imm4 + vfp_vmovi 11101110 1d11aaaa bbbb101s 0000cccc, s:size, d:d, b:vd, a:imm4h, c:imm4l + vfp_vmov 11101110 1a110000 bbbb101s 01c0dddd, s:size, a:d, b:vd, c:m, d:vm + vfp_vmov_core_scal 11101110 0ooaaaaa bbbb1011 dcc10000, d:d, a:vd, o:opc1, c:opc2, b:rt + vfp_vmov_scal_core 11101110 uaa1bbbb cccc1011 ndd10000, u:unsign, c:rt, n:n, b:vn, a:opc1, d:opc2 + vfp_vmov_core_sp 11101110 000oaaaa bbbb1010 n0010000, o:op, b:rt, n:n, a:vn + vfp_vmov_2core_2sp 11101100 010abbbb cccc1010 00d1eeee, a:to_arm, c:rt, b:rt2, d:m, e:vm + vfp_vmov_2core_dp 11101100 010abbbb cccc1011 00d1eeee, a:to_arm, c:rt, b:rt2, d:m, e:vm + vfp_vmov_hp 11101110 000abbbb cccc1001 d0010000, a:op, c:rt, d:n, b:vn +neon_vmovl 111u1111 1daaa000 bbbb1010 00m1cccc, a:op:!:000, u:unsign, d:d, b:vd, m:m, c:vm +neon_vmovn 11111111 1d11ss10 aaaa0010 00m0bbbb, s:size, d:d, a:vd, m:m, b:vm + vfp_vmovx 11111110 1a110000 bbbb1010 01c0dddd, a:d, b:vd, c:m, d:vm + vfp_vmrs 11101110 11110001 aaaa1010 00010000, a:rt + vfp_vmsr 11101110 11100001 aaaa1010 00010000, a:rt +neon_vmul_i 111o1111 0dssaaaa bbbb1001 nqm1cccc, o:op, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmull_i 111a1111 1bccdddd eeee11f0 g0h0iiii, f:op, a:unsign, c:size:!:11, b:d, e:vd, g:n, d:vn, h:m, i:vm +neon_vmul_f 11111111 0d0saaaa bbbb1101 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vmul 11101110 0d10aaaa bbbb101s n0m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmul_scal 111q1111 1dssaaaa bbbb100f n1m0cccc, f:is_float, s:size:!:11, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmull_scal 111u1111 1dssaaaa bbbb1010 n1m0cccc, u:unsign, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vmvni 111i1111 1d000aaa bbbbcccc 0q11eeee, q:q, d:d, b:vd, c:cmode, i:i, a:imm3, e:imm4 +neon_vmvn 11111111 1d11ss00 aaaa0101 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vneg 11111111 1d11ss01 aaaa0f11 1qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm + vfp_vneg 11101110 1d110001 aaaa101s 01m0bbbb, s:size, d:d, a:vd, m:m, b:vm + vfp_vnmla 11101110 0a01bbbb cccc101s d1e0ffff, s:size, a:d, c:vd, d:n, b:vn, e:m, f:vm + vfp_vnmls 11101110 0a01bbbb cccc101s d0e0ffff, s:size, a:d, c:vd, d:n, b:vn, e:m, f:vm + vfp_vnmul 11101110 0a10bbbb cccc101s d1e0ffff, s:size, a:d, c:vd, d:n, b:vn, e:m, f:vm +neon_vorn 11101111 0a11bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vorri 111i1111 1d000aaa bbbbcccc 0q01eeee, q:q, d:d, b:vd, c:cmode:=:0001:0011:0101:0111:1001:1011, i:i, a:imm3, e:imm4 +neon_vorr 11101111 0a10bbbb cccc0001 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vpadal 11111111 1d11ss00 aaaa0110 oqm0bbbb, o:unsign, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vpadd_i 11101111 0dssaaaa bbbb1011 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpadd_f 11111111 0d0saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpaddl 11111111 1d11ss00 aaaa0010 oqm0bbbb, o:unsign, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vpmax_i 111u1111 0dssaaaa bbbb1010 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpmin_i 111u1111 0dssaaaa bbbb1010 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpmax_f 11111111 0d0saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vpmin_f 11111111 0d1saaaa bbbb1111 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vpop 11101100 1d111101 aaaa101s bbbbbbbb, s:size, d:d, a:vd, b:regs + vfp_vpush 11101101 0d101101 aaaa101s bbbbbbbb, s:size, d:d, a:vd, b:regs +neon_vqabs 11111111 1d11ss00 aaaa0111 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vqadd 111a1111 0bccdddd eeee0000 fgh1iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vqdmlal_i 11101111 1dssaaaa bbbb1001 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmlsl_i 11101111 1dssaaaa bbbb1011 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmlal_scal 11101111 1dssaaaa bbbb0011 n1m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmlsl_scal 11101111 1dssaaaa bbbb0111 n1m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmulh_i 11101111 0dssaaaa bbbb1011 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmulh_scal 111q1111 1dssaaaa bbbb1100 n1m0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmull_i 11101111 1dssaaaa bbbb1101 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqdmull_scal 11101111 1dssaaaa bbbb1011 n1m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqmovn 11111111 1a11bb10 cccc0010 1de0ffff, d:unsign, b:size, a:d, c:vd, e:m, f:vm +neon_vqmovun 11111111 1a11bb10 cccc0010 01d0ffff, b:size, a:d, c:vd, d:m, f:vm +neon_vqneg 11111111 1d11ss00 aaaa0111 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vqrdmlaht1 11111111 0abbcccc dddd1011 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vqrdmlaht2 111a1111 1bccdddd eeee1110 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vqrdmlsht1 11111111 0abbcccc dddd1100 efg1hhhh, b:size, f:q, a:d, d:vd, e:n, c:vn, g:m, h:vm +neon_vqrdmlsht2 111a1111 1bccdddd eeee1111 f1g0hhhh, c:size, a:q, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vqrdmulh_i 11111111 0dssaaaa bbbb1011 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqrdmulh_scal 111q1111 1dssaaaa bbbb1101 n1m0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqrshl 111u1111 0dssaaaa bbbb0101 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vqrshrn 111a1111 1bcccccc dddd1001 01e1ffff, a:unsign, b:d, d:vd, e:m, f:vm, c:imm6 +neon_vqrshrun 11111111 1abbbbbb cccc1000 01d1eeee, a:d, c:vd, d:m, e:vm, b:imm6 +neon_vqshl 111u1111 0dssaaaa bbbb0100 nqm1cccc, u:unsign, s:size, q:q, d:d, b:vd, m:m, c:vm, n:n, a:vn +neon_vqshli 111u1111 1daaaaaa bbbb0111 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vqshlui 11111111 1daaaaaa bbbb0110 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vqshrn 111u1111 1daaaaaa bbbb1001 00m1cccc, u:unsign, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vqshrun 11111111 1daaaaaa bbbb1000 00m1cccc, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vqsub 111a1111 0bccdddd eeee0010 fgh1iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vraddhn 11111111 1dssaaaa bbbb0100 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrecpe 11111111 1d11ss11 aaaa010f 0qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrecps 11101111 0d0saaaa bbbb1111 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrev16 11111111 1d11ss00 aaaa0001 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrev32 11111111 1d11ss00 aaaa0000 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrev64 11111111 1d11ss00 aaaa0000 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrhadd 111u1111 0bccdddd eeee0001 fgh0iiii, u:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vrshl 111u1111 0dssaaaa bbbb0101 nqm0cccc, u:unsign, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrshr 111a1111 1bcccccc dddd0010 efg1hhhh, a:unsign, f:q, b:d, d:vd, g:m, h:vm, e:l, c:imm6 +neon_vrshrn 11101111 1abbbbbb cccc1000 01d1eeee, a:d, c:vd, d:m, e:vm, b:imm6:!:000000:000001:000010:000011:000100:000101:000110:000111 +neon_vrsqrte 11111111 1d11ss11 aaaa010f 1qm0bbbb, f:is_float, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vrsqrts 11101111 0d1saaaa bbbb1111 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vrsra 111u1111 1daaaaaa bbbb0011 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vrsubhn 11111111 1dssaaaa bbbb0110 n0m0cccc, s:size:!:11, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsdot 11111100 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm +neon_vsdot_scal 11111110 0a10bbbb cccc1101 defghhhh, g:u, e:q, a:d, c:vd, d:n, b:vn, f:m, h:vm +neon_vshl 111a1111 0bccdddd eeee0100 fgh0iiii, a:unsign, c:size, g:q, b:d, e:vd, f:n, d:vn, h:m, i:vm +neon_vshli 11101111 1abbbbbb cccc0101 def1gggg, e:q, a:d, c:vd, f:m, g:vm, d:l, b:imm6 +neon_vshll 111a1111 1bcccccc dddd1010 00e1ffff, a:unsign, b:d, d:vd, e:m, f:vm, c:imm6:!:000000:000001:000010:000011:000100:000101:000110:000111 +neon_vshll2 11111111 1d11ss10 aaaa0011 00m0bbbb, s:size, d:d, a:vd, m:m, b:vm +neon_vshr 111a1111 1bcccccc dddd0000 efg1hhhh, a:unsign, f:q, b:d, d:vd, g:m, h:vm, e:l, c:imm6 +neon_vshrn 11101111 1daaaaaa bbbb1000 00m1cccc, d:d, b:vd, m:m, c:vm, a:imm6 +neon_vsli 11111111 1abbbbbb cccc0101 def1gggg, e:q, a:d, c:vd, f:m, g:vm, d:l, b:imm6 + vfp_vsqrt 11101110 1d110001 aaaa101s 11m0bbbb, s:size, d:d, a:vd, m:m, b:vm +neon_vsra 111u1111 1daaaaaa bbbb0001 lqm1cccc, u:unsign, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vsri 11111111 1daaaaaa bbbb0100 lqm1cccc, q:q, d:d, b:vd, m:m, c:vm, l:l, a:imm6 +neon_vstx_m 11111001 0a00bbbb ccccdddd eeffgggg, d:opcode, e:size, a:d, c:vd, b:rn, f:align, g:rm +neon_vstx_s_o 11111001 1a00bbbb ccccddee ffffgggg, e:opcode, d:size:!:11, a:d, c:vd, b:rn, f:index_align, g:rm + vfp_vstm_dp 1110110p udw0aaaa bbbb1011 cccccccc, p:p, u:upwards, w:writeback, a:rn, d:d, b:vd, c:imm8 + vfp_vstm_sp 1110110p udw0aaaa bbbb1010 cccccccc, p:p, u:upwards, w:writeback, a:rn, d:d, b:vd, c:imm8 + vfp_vstr_dp 11101101 ud00aaaa bbbb1011 cccccccc, u:upwards, a:rn, d:d, b:vd, c:imm8 + vfp_vstr_sp 11101101 ud00aaaa bbbb1010 cccccccc, u:upwards, a:rn, d:d, b:vd, c:imm8 +neon_vsub_i 11111111 0dssaaaa bbbb1000 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsub_f 11101111 0d1saaaa bbbb1101 nqm0cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm + vfp_vsub 11101110 0d11aaaa bbbb101s n1m0cccc, s:size, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vsubhn 11101111 1abbcccc dddd0110 e0f0gggg, b:size:!:11, a:d, d:vd, e:n, c:vn, f:m, g:vm +neon_vsubl 111a1111 1bccdddd eeee0010 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vsubw 111a1111 1bccdddd eeee0011 f0g0hhhh, a:unsign, c:size:!:11, b:d, e:vd, f:n, d:vn, g:m, h:vm +neon_vsudot 11111110 1a00bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vswp 11111111 1d11ss10 aaaa0000 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vtbl 11111111 1d11aaaa bbbb10cc n0m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm +neon_vtbx 11111111 1d11aaaa bbbb10cc n1m0eeee, d:d, b:vd, n:n, a:vn, c:len, m:m, e:vm +neon_vtrn 11111111 1a11bb10 cccc0000 1de0ffff, b:size, d:q, a:d, c:vd, e:m, f:vm +neon_vtst 11101111 0dssaaaa bbbb1000 nqm1cccc, s:size, q:q, d:d, b:vd, n:n, a:vn, m:m, c:vm +neon_vudot 11111100 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vudot_scal 11111110 0a10bbbb cccc1101 def1gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vusdot 11111100 1a10bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vusdot_scal 11111110 1a00bbbb cccc1101 def0gggg, e:q, a:d, c:vd, d:n, b:vn, f:m, g:vm +neon_vuzp 11111111 1d11ss10 aaaa0001 0qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +neon_vzip 11111111 1d11ss10 aaaa0001 1qm0bbbb, s:size, q:q, d:d, a:vd, m:m, b:vm +# +# New ARMv8 instructions +# +# ARMv8 VFP, NEON +# + vfp_vsel 11111110 0abbcccc dddd101s n0m0eeee, s:size, b:cond, a:d, d:vd, n:n, c:vn, m:m, e:vm + +# +# Generic field decoders +# +shift_i_mov_16 000aabbb bbcccddd, a:opcode, b:imm5, c:rm, d:rd +add_sub_16 000110ab bbcccddd, a:opcode, b:rm, c:rn, d:rd +add_sub_i_16 000111ab bbcccddd, a:opcode, b:imm3, c:rn, d:rd +add_sub_comp_mov_i_16 001aabbb cccccccc, a:opcode, b:rdn, c:imm8 +data_proc_16 010000aa aabbbccc, a:opcode, b:rm, c:rdn +special_data_proc_16 010001aa bccccddd, a:opcode, b:dn, c:rm, d:rdn +bx_16 01000111 abbbb000, a:link, b:rm +load_lit_16 01001aaa bbbbbbbb, a:rd, b:imm8 +load_store_reg_offset_16 0101aaab bbcccddd, a:opcode, b:rm, c:rn, d:rd +load_store_byte_word_i_16 011abccc ccdddeee, a:byte, b:load, c:imm5, d:rn, e:rd +load_store_halfword_i_16 1000abbb bbcccddd, a:load, b:imm5, c:rn, d:rd +load_store_stack_16 1001abbb cccccccc, a:load, b:rd, c:imm8 +add_sp_pc_16 1010abbb cccccccc, a:sp, b:rd, c:imm8 +misc_add_sub_sp_i_16 10110000 abbbbbbb, a:opcode, b:imm7 +misc_sign_zero_extend_16 10110010 aabbbccc, a:opcode, b:rm, c:rd +misc_cbz_16 1011a0b1 cccccddd, a:n, b:imm1, c:imm5, d:rn +misc_push_pop_16 1011aaab bbbbbbbb, a:opcode, b:reg +misc_rev_16 10111010 aabbbccc, a:opcode, b:rn, c:rd +misc_if_then_16 10111111 aaaabbbb, a:cond, b:mask +misc_nop_16 10111111 aaaa0000, a:hint +load_store_multiple_16 1100abbb cccccccc, a:load, b:rn, c:reglist +cond_branch_16 1101aaaa bbbbbbbb, a:condition, b:imm8 +svc_16 11011111 aaaaaaaa, a:imm8 +uncond_branch_16 11100aaa aaaaaaaa, a:imm11 +data_proc_12bit_i_32 11110abb bbbcdddd 0eeeffff gggggggg, a:imm1, b:opcode, c:set_condition, d:rn, e:imm3, f:rd, g:imm8 +data_proc_12bit_i_plain_32 11110a10 bbbbcccc 0dddeeee ffffffff, a:imm1, b:opcode, c:rn, d:imm3, e:rd, f:imm8 +data_proc_16bit_i_32 11110abb bbbbcccc 0dddeeee ffffffff, a:imm1, b:opcode, c:imm4, d:imm3, e:rd, f:imm8 +data_proc_bit_field 11110011 aaabbbbb 0cccdddd ee0fffff, a:opcode, b:rn, c:imm3, d:rd, e:imm2, f:imm5 +data_proc_const_shift 1110101a aaabcccc 0dddeeee ffgghhhh, a:opcode, b:set_flags, c:rn, d:imm3, e:rd, f:imm2, g:shift_type, h:rm +data_proc_reg_shift 11111010 0aabcccc 1111dddd 0eeeffff, a:opcode, b:set_flags, c:rn, d:rd, e:opcode2, f:rm +data_proc_sign_zero_ext 11111010 0aaabbbb 1111cccc 10ddeeee, a:opcode, b:rn, c:rd, d:rotate, e:rm +data_proc_simd_add_sub 11111010 1aaabbbb 1111cccc 0dddeeee, a:opcode, b:rn, c:rd, d:pref, e:rm +data_proc_other_3reg 11111010 1aaabbbb 1111cccc 1dddeeee, a:opcode, b:rn, c:rd, d:opcode2, e:rm +data_proc_32_mult 11111011 0aaabbbb ccccdddd eeeeffff, a:opcode, b:rn, c:racc, d:rd, e:opcode2, f:rm +data_proc_64_mult 11111011 1aaabbbb ccccdddd eefghhhh, a:opcode, b:rn, c:rdlo, d:rdhi, e:opcode2, f:n_high, g:m_swap, h:rm +load_store_single_reg_imm12_32 1111100a bccdeeee ffffgggg gggggggg, a:sign_ext, b:upwards, c:size, d:load_store, e:rn, f:rt, g:imm12 +load_store_single_reg_off_32 1111100a 0bbcdddd eeee0000 00ffgggg, a:sign_ext, b:size, c:load_store, d:rn, e:rt, f:shift, g:rm +pld_t2_32 1111100a 0bbcdddd eeeeffff gggggggg, a:sign_ext, b:size, c:load_store, d:rn, e:rt, f:opcode, g:imm8 +load_store_double_ex 1110100a b1cdeeee ffffgggg hhhhhhhh, a:pre_index, b:upwards, c:writeback, d:load_store, e:rn, f:rt, g:rd, h:imm8 +load_store_ex_tb_branch 1110100a b1cdeeee ffffgggg hhhhiiii, a:pre_index, b:upwards, c:writeback, d:load_store, e:rn, f:rt, g:rd, h:opcode, i:rm +load_store_multiple32 1110100a aabcdddd eeeeeeee eeeeeeee, a:opcode, b:writeback, c:load, d:rn, e:reglist +branch32 11110abb bbbbbbbb 1cdefggg gggggggg, a:sign_bit, b:offset_high, c:link, d:j1, e:thumb_mode, f:j2, g:offset_low +branch_cond32 11110abb bbcccccc 10d0efff ffffffff, a:sign_bit, b:condition, c:offset_high, d:j1, e:j2, f:offset_low +special_control 11110011 10111111 10001111 aaaabbbb, a:opcode, b:option +status_reg_access 11110011 1aabcccc 1000dddd 00000000, a:opcode, b:s_or_c, c:rn, d:rd +coproc_proc 11101110 aaaabbbb ccccdddd eee0ffff, a:opc1, b:crn, c:crd, d:coproc, e:opc2, f:crm +coproc_trans 11101110 aaabcccc ddddeeee fff1gggg, a:opc1, b:load, c:crn, d:rt, e:coproc, f:opc2, g:crm +vmov_arm 111011aa aaabcccc dddd101e fgh1iiii, a:opcode, b:to_arm, c:rt2, d:rt, e:double_single, f:n, g:f2, h:m, i:vm +vmov 1110111a abccdddd eeeeffff ghijkkkk, a:type, b:d, c:opcode, d:vm2, e:vd, f:opcode2, g:m2, h:q, i:m, j:opcode3, k:vm +vmovi_neon 111a1111 1b000ccc ddddeeee 0fg1hhhh, a:i, b:d, c:imm3, d:vd, e:cmode, f:q, g:op, h:imm4 +vmovi 11101110 1a11bbbb cccc101d 0000eeee, a:d, b:immh, c:vd, d:sz, e:imml +vfp_ldr_str 11101101 ab0cdddd eeee101f gggggggg, a:upwards, b:d, c:load_store, d:rn, e:vd, f:double_reg, g:imm8 +vcmp 11101110 1a11010b cccc101d e1f0gggg, a:d, b:empty, c:vd, d:sz, e:e, f:m, g:vm +v_s_ldm 1110110a bcdeffff gggg101h iiiiiiii, a:p, b:upwards, c:d, d:writeback, e:load_store, f:rn, g:vd, h:double_prec, i:imm8 +vadd 111a111b 0cddeeee ffffgggg hij0kkkk, a:sub_add, b:single_prec, c:d, d:sz, e:vn, f:vd, g:opcode, h:n, i:q, j:m, k:vm +vneg 1110111a 1b11cc01 ddddef1g hij0kkkk, a:single_prec, b:d, c:size, d:vd, e:double_prec, f:f, g:f5, h:sz, i:q, j:m, k:vm +vml 111a111b cdeeffff gggghijk lmnopppp, a:op, b:opcode2, c:scalar, d:d, e:size, f:vn, g:vd, h:f2, i:opcode3, j:f3, k:f, l:n, m:q, n:m, o:f4, p:vm +vcvt 111a111b 1c11dddd eeeeffff ghi0jjjj, a:u, b:opcode2, c:d, d:opcode3, e:vd, f:opcode4, g:op, h:q, i:m, j:vm +vdiv 11101110 1a00bbbb cccc101d e0f0gggg, a:d, b:vn, c:vd, d:sz, e:n, f:m, g:vm +fpv_op 11101110 1abbcccc ddddeeef ghijkkkk, a:d, b:opcode, c:vn, d:vd, e:opcode2, f:sz, g:n, h:q, i:m, j:z, k:vm +simd_op 11101111 0abbcccc ddddeeee fghijjjj, a:d, b:sz, c:vn, d:vd, e:opcode, f:n, g:q, h:m, i:z, j:vm +neon_imm6 111a1111 1bcccccc ddddeeef ghi1jjjj, a:u, b:d, c:imm6, d:vd, e:opcode3, f:opcode4, g:l, h:q, i:m, j:vm +neon_trans_mult_lane 11111001 abccdddd eeeeffgg hhiijjjj, a:opcode, b:d, c:opcode2, d:rn, e:vd, f:size, g:element_size, h:sz, i:align, j:rm +neon_imm4_2reg 11111111 1a11bbbb ccccdddd efg0hhhh, a:d, b:imm4, c:vd, d:opcode, e:opcode2, f:q, g:m, h:vm +neon_imm4_3reg 11101111 1a11bbbb ccccdddd efg0hhhh, a:d, b:vn, c:vd, d:imm4, e:n, f:q, g:m, h:vm +data_proc_rd_rn_rm 00000000 0000aaaa 0000bbbb 0000cccc, b:rd, a:rn, c:rm +data_proc_rd_rn_rm_ra 00000000 0000aaaa bbbbcccc 0000dddd, c:rd, a:rn, d:rm, b:ra +vfp_ld_st_m 0000000p udw0aaaa bbbb0000 cccccccc, p:p, u:upwards, w:writeback, a:rn, d:d, b:vd, c:imm8 +vfp_vldr_vstr 00000000 ud00aaaa bbbb0000 cccccccc, u:upwards, a:rn, d:d, b:vd, c:imm8