From 587ac54a0b91bf14f92f9b44d08392955ac450bb Mon Sep 17 00:00:00 2001 From: jzlv Date: Fri, 3 Nov 2023 17:09:46 +0800 Subject: [PATCH] [feat] add bl702l driver and board --- bsp/board/bl702ldk/CMakeLists.txt | 8 + bsp/board/bl702ldk/bl702l_flash.ld | 257 + bsp/board/bl702ldk/board.c | 318 + bsp/board/bl702ldk/board.h | 20 + bsp/board/bl702ldk/config/.gitkeep | 0 bsp/board/bl702ldk/fw_header.c | 122 + bsp/board/bl702ldk/fw_header.h | 171 + drivers/lhal/config/bl702l/bl702l_irq.h | 84 + drivers/lhal/config/bl702l/bl702l_memorymap.h | 82 + drivers/lhal/config/bl702l/device_table.c | 197 + drivers/soc/bl702l/std/CMakeLists.txt | 42 + drivers/soc/bl702l/std/include/bl702l_aon.h | 119 + drivers/soc/bl702l/std/include/bl702l_clock.h | 150 + .../soc/bl702l/std/include/bl702l_common.h | 224 + .../soc/bl702l/std/include/bl702l_ef_cfg.h | 102 + .../soc/bl702l/std/include/bl702l_ef_ctrl.h | 291 + drivers/soc/bl702l/std/include/bl702l_glb.h | 885 +++ .../soc/bl702l/std/include/bl702l_glb_gpio.h | 138 + drivers/soc/bl702l/std/include/bl702l_gpio.h | 139 + drivers/soc/bl702l/std/include/bl702l_hbn.h | 730 ++ drivers/soc/bl702l/std/include/bl702l_kys.h | 179 + drivers/soc/bl702l/std/include/bl702l_l1c.h | 210 + drivers/soc/bl702l/std/include/bl702l_pds.h | 710 ++ drivers/soc/bl702l/std/include/bl702l_pm.h | 64 + .../bl702l/std/include/bl702l_romapi_patch.h | 42 + .../soc/bl702l/std/include/bl702l_romdriver.h | 2020 +++++ .../soc/bl702l/std/include/bl702l_tzc_sec.h | 92 + .../soc/bl702l/std/include/hardware/aon_reg.h | 1103 +++ .../soc/bl702l/std/include/hardware/bl702l.h | 237 + .../bl702l/std/include/hardware/ef_ctrl_reg.h | 812 ++ .../bl702l/std/include/hardware/ef_data_reg.h | 762 ++ .../soc/bl702l/std/include/hardware/glb_reg.h | 6720 +++++++++++++++++ .../soc/bl702l/std/include/hardware/hbn_reg.h | 885 +++ .../soc/bl702l/std/include/hardware/kys_reg.h | 276 + .../soc/bl702l/std/include/hardware/l1c_reg.h | 331 + .../soc/bl702l/std/include/hardware/pdm_reg.h | 351 + .../soc/bl702l/std/include/hardware/pds_reg.h | 1826 +++++ .../bl702l/std/include/hardware/sf_ctrl_reg.h | 3371 +++++++++ .../std/include/hardware/tzc_nsec_reg.h | 251 + .../bl702l/std/include/hardware/tzc_sec_reg.h | 251 + drivers/soc/bl702l/std/port/bl702l_clock.c | 19 + drivers/soc/bl702l/std/src/bl702l_aon.c | 599 ++ drivers/soc/bl702l/std/src/bl702l_clock.c | 1167 +++ drivers/soc/bl702l/std/src/bl702l_common.c | 202 + drivers/soc/bl702l/std/src/bl702l_ef_cfg.c | 429 ++ drivers/soc/bl702l/std/src/bl702l_glb.c | 2628 +++++++ drivers/soc/bl702l/std/src/bl702l_glb_gpio.c | 719 ++ drivers/soc/bl702l/std/src/bl702l_hbn.c | 1738 +++++ drivers/soc/bl702l/std/src/bl702l_kys.c | 456 ++ drivers/soc/bl702l/std/src/bl702l_l1c.c | 646 ++ drivers/soc/bl702l/std/src/bl702l_pds.c | 1215 +++ drivers/soc/bl702l/std/src/bl702l_pm.c | 511 ++ drivers/soc/bl702l/std/src/bl702l_romapi.c | 2342 ++++++ .../soc/bl702l/std/src/bl702l_romapi_patch.c | 246 + drivers/soc/bl702l/std/src/bl702l_romdriver.c | 599 ++ drivers/soc/bl702l/std/src/bl702l_tzc_sec.c | 237 + drivers/soc/bl702l/std/startup/interrupt.c | 212 + drivers/soc/bl702l/std/startup/start.S | 96 + drivers/soc/bl702l/std/startup/start_load.c | 114 + .../soc/bl702l/std/startup/system_bl702l.c | 80 + 60 files changed, 38827 insertions(+) create mode 100644 bsp/board/bl702ldk/CMakeLists.txt create mode 100644 bsp/board/bl702ldk/bl702l_flash.ld create mode 100644 bsp/board/bl702ldk/board.c create mode 100644 bsp/board/bl702ldk/board.h create mode 100644 bsp/board/bl702ldk/config/.gitkeep create mode 100644 bsp/board/bl702ldk/fw_header.c create mode 100644 bsp/board/bl702ldk/fw_header.h create mode 100644 drivers/lhal/config/bl702l/bl702l_irq.h create mode 100644 drivers/lhal/config/bl702l/bl702l_memorymap.h create mode 100644 drivers/lhal/config/bl702l/device_table.c create mode 100644 drivers/soc/bl702l/std/CMakeLists.txt create mode 100644 drivers/soc/bl702l/std/include/bl702l_aon.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_clock.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_common.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_ef_cfg.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_ef_ctrl.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_glb.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_glb_gpio.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_gpio.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_hbn.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_kys.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_l1c.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_pds.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_pm.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_romapi_patch.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_romdriver.h create mode 100644 drivers/soc/bl702l/std/include/bl702l_tzc_sec.h create mode 100644 drivers/soc/bl702l/std/include/hardware/aon_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/bl702l.h create mode 100644 drivers/soc/bl702l/std/include/hardware/ef_ctrl_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/ef_data_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/glb_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/hbn_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/kys_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/l1c_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/pdm_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/pds_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/sf_ctrl_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/tzc_nsec_reg.h create mode 100644 drivers/soc/bl702l/std/include/hardware/tzc_sec_reg.h create mode 100644 drivers/soc/bl702l/std/port/bl702l_clock.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_aon.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_clock.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_common.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_ef_cfg.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_glb.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_glb_gpio.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_hbn.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_kys.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_l1c.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_pds.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_pm.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_romapi.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_romapi_patch.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_romdriver.c create mode 100644 drivers/soc/bl702l/std/src/bl702l_tzc_sec.c create mode 100644 drivers/soc/bl702l/std/startup/interrupt.c create mode 100644 drivers/soc/bl702l/std/startup/start.S create mode 100644 drivers/soc/bl702l/std/startup/start_load.c create mode 100644 drivers/soc/bl702l/std/startup/system_bl702l.c diff --git a/bsp/board/bl702ldk/CMakeLists.txt b/bsp/board/bl702ldk/CMakeLists.txt new file mode 100644 index 000000000..786b021f0 --- /dev/null +++ b/bsp/board/bl702ldk/CMakeLists.txt @@ -0,0 +1,8 @@ +sdk_add_include_directories(.) + +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) +target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c) + +sdk_set_linker_script(bl702l_flash.ld) + +sdk_add_link_options(-ufw_header) \ No newline at end of file diff --git a/bsp/board/bl702ldk/bl702l_flash.ld b/bsp/board/bl702ldk/bl702l_flash.ld new file mode 100644 index 000000000..3abc4716e --- /dev/null +++ b/bsp/board/bl702ldk/bl702l_flash.ld @@ -0,0 +1,257 @@ +/**************************************************************************************** +* @file bl702l_flash.ld +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) + +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x1000; /* 4KB */ +HeapMinSize = 0x1000; /* 4KB */ + +MEMORY +{ + fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K + itcm_memory (rx) : ORIGIN = 0x22020000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42024000, LENGTH = 4K + ram_memory (!rx) : ORIGIN = 0x42025000, LENGTH = 60K + hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 0xE00 /* hbn ram 4K used 3.5K*/ +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory + + .init : + { + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + + } > xip_memory + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + *(.text) + *(.text.*) + + /* section information for shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl702l_glb*.o* \ + *bl702l_pds*.o* \ + *bl702l_common*.o* \ + *bl702l_sf_cfg*.o* \ + *bl702l_sf_cfg_ext*.o* \ + *bl702l_sf_ctrl*.o* \ + *bl702l_sflash*.o* \ + *bl702l_sflash_ext*.o* \ + *bl702l_xip_sflash*.o* \ + *bl702l_xip_sflash_ext*.o* \ + *bl702l_ef_ctrl*.o*) .rodata*) + + *(.srodata) + *(.srodata.*) + + /* _dump_sections for bflb_coredump.c*/ + . = ALIGN(4); + PROVIDE( _dump_sections = ABSOLUTE(.)); + LONG(ORIGIN(itcm_memory)); + LONG(LENGTH(itcm_memory)); + LONG(ORIGIN(dtcm_memory)); + LONG(LENGTH(dtcm_memory)); + LONG(ORIGIN(ram_memory)); + LONG(LENGTH(ram_memory)); + LONG(ORIGIN(hbn_memory)); + LONG(LENGTH(hbn_memory)); + LONG(0xffffffff); + LONG(0xffffffff); + /* _dump_sections for bl_coredump.c*/ + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + + *bl702l_glb*.o*(.rodata*) + *bl702l_pds*.o*(.rodata*) + *bl702l_common*.o*(.rodata*) + *bl702l_sf_cfg*.o*(.rodata*) + *bl702l_sf_cfg_ext*.o*(.rodata*) + *bl702l_sf_ctrl*.o*(.rodata*) + *bl702l_sflash*.o*(.rodata*) + *bl702l_sflash_ext*.o*(.rodata*) + *bl702l_xip_sflash*.o*(.rodata*) + *bl702l_xip_sflash_ext*.o*(.rodata*) + *bl702l_ef_ctrl*.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .hbn_ram_region : AT (__hbn_load_addr) + { + . = ALIGN(4); + __hbn_ram_start__ = .; + *(.hbn_code.*) + *(.hbn_data.*) + . = ALIGN(4); + __hbn_ram_end__ = .; + } > hbn_memory + + __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + PROVIDE( _sp_main = __StackTop); + PROVIDE( _sp_base = __StackTop - StackSize); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + *(.nocache_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + + ASSERT((__HeapLimit - __HeapBase ) >= HeapMinSize, "heap size is too short.") + +} + diff --git a/bsp/board/bl702ldk/board.c b/bsp/board/bl702ldk/board.c new file mode 100644 index 000000000..f2a3f56ba --- /dev/null +++ b/bsp/board/bl702ldk/board.c @@ -0,0 +1,318 @@ +#include "bflb_uart.h" +#include "bflb_gpio.h" +#include "bflb_clock.h" +#include "bflb_rtc.h" +#include "bflb_flash.h" +#include "bl702l_glb.h" +#include "bl702l_clock.h" +#include "board.h" + +#include "mem.h" + +extern void log_start(void); + +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +static struct bflb_device_s *uart0; + +#if defined(CONFIG_BFLOG) +static struct bflb_device_s *rtc; +#endif + +static void system_clock_init(void) +{ + GLB_Set_System_CLK(GLB_DLL_XTAL_32M, GLB_SYS_CLK_DLL128M); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1); + HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL); + // HBN_Power_On_Xtal_32K(); + // HBN_32K_Sel(HBN_32K_XTAL); +} + +static void peripheral_clock_init(void) +{ + PERIPHERAL_CLOCK_ADC_DAC_ENABLE(); + PERIPHERAL_CLOCK_SEC_ENABLE(); + PERIPHERAL_CLOCK_DMA0_ENABLE(); + PERIPHERAL_CLOCK_UART0_ENABLE(); + PERIPHERAL_CLOCK_SPI0_ENABLE(); + PERIPHERAL_CLOCK_I2C0_ENABLE(); + PERIPHERAL_CLOCK_PWM0_ENABLE(); + PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE(); + PERIPHERAL_CLOCK_IR_ENABLE(); + + GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_CHECKSUM); + + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0); + GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_SRC_XCLK, 0); + GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_SRC_XCLK, 0); + GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_SRC_XCLK, 1); + GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 15); + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_SRC_DLL128M); +} + +void bl_show_log(void) +{ + printf("\r\n"); + printf(" ____ __ __ _ _ _ \r\n"); + printf(" | _ \\ / _|/ _| | | | | | | \r\n"); + printf(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n"); + printf(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n"); + printf(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n"); + printf(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n"); + printf("\r\n"); + printf("Build:%s,%s\r\n", __TIME__, __DATE__); + printf("Copyright (c) 2022 Bouffalolab team\r\n"); +} + +void bl_show_flashinfo(void) +{ + spi_flash_cfg_type flashCfg; + uint8_t *pFlashCfg = NULL; + uint32_t flashSize = 0; + uint32_t flashCfgLen = 0; + uint32_t flashJedecId = 0; + + flashJedecId = bflb_flash_get_jedec_id(); + flashSize = bflb_flash_get_size(); + bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen); + arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen); + printf("======== flash cfg ========\r\n"); + printf("flash size 0x%08X\r\n", flashSize); + printf("jedec id 0x%06X\r\n", flashJedecId); + printf("mid 0x%02X\r\n", flashCfg.mid); + printf("iomode 0x%02X\r\n", flashCfg.io_mode); + printf("clk delay 0x%02X\r\n", flashCfg.clk_delay); + printf("clk invert 0x%02X\r\n", flashCfg.clk_invert); + printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); + printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); + printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); + printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); + printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); + printf("cread support 0x%02X\r\n", flashCfg.c_read_support); + printf("cread code 0x%02X\r\n", flashCfg.c_read_mode); + printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); + printf("===========================\r\n"); +} + +extern void bflb_uart_set_console(struct bflb_device_s *dev); + +static void console_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX); + + struct bflb_uart_config_s cfg; + cfg.baudrate = 2000000; + cfg.data_bits = UART_DATA_BITS_8; + cfg.stop_bits = UART_STOP_BITS_1; + cfg.parity = UART_PARITY_NONE; + cfg.flow_ctrl = 0; + cfg.tx_fifo_threshold = 15; + cfg.rx_fifo_threshold = 15; + + uart0 = bflb_device_get_by_name("uart0"); + + bflb_uart_init(uart0, &cfg); + bflb_uart_set_console(uart0); +} + +void board_init(void) +{ + int ret = -1; + uintptr_t flag; + + flag = bflb_irq_save(); + + ret = bflb_flash_init(); + + system_clock_init(); + peripheral_clock_init(); + bflb_irq_initialize(); + + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + + console_init(); + + bl_show_log(); + if (ret != 0) { + printf("flash init fail!!!\r\n"); + } + bl_show_flashinfo(); + + printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); + + printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); +#if defined(CONFIG_BFLOG) + rtc = bflb_device_get_by_name("rtc"); +#endif + bflb_irq_restore(flag); +} + +void board_uartx_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* just use console uart pin */ + bflb_gpio_uart_init(gpio, GPIO_PIN_0, GPIO_UART_FUNC_UART0_CTS); + bflb_gpio_uart_init(gpio, GPIO_PIN_1, GPIO_UART_FUNC_UART0_RTS); +} + +void board_i2c0_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* I2C0_SDA */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* I2C0_SCL */ + bflb_gpio_init(gpio, GPIO_PIN_10, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_spi0_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* spi mosi */ + bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* spi miso */ + bflb_gpio_init(gpio, GPIO_PIN_9, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* spi cs */ + bflb_gpio_init(gpio, GPIO_PIN_10, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* spi clk */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_pwm_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* pwm0 ch 0 */ + bflb_gpio_init(gpio, GPIO_PIN_0, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* pwm1 ch 0 */ + /* pwm1 ch 1 */ + /* pwm1 ch 2 */ + /* pwm1 ch 3 */ + bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_FUNC_PWM1 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_FUNC_PWM1 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_FUNC_PWM1 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_9, GPIO_FUNC_PWM1 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +void board_adc_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + /* ch0 and ch1 is for uart log */ + /* adc ch 0 */ + // bflb_gpio_init(gpio, GPIO_PIN_14, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + // /* adc ch 1 */ + // bflb_gpio_init(gpio, GPIO_PIN_15, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* adc ch 2 */ + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* adc ch 3 */ + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + + /* ch4~ch6 are only for BL704L */ + // /* adc ch 4 */ + // bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + // /* adc ch 5 */ + // bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + // /* adc ch 6 */ + // bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* adc ch 7 */ + bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* adc ch 8 */ + bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* adc ch 9 */ + bflb_gpio_init(gpio, GPIO_PIN_9, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + /* adc ch 10 */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + + /* ch11 is only for BL704L */ + // /* adc ch 11 */ + // bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); +} + +void board_ir_gpio_init(void) +{ + struct bflb_device_s *gpio; + + /* Can only use GPIO18 or GPIO22 */ + uint32_t pin = GPIO_PIN_22; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, pin, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0); + + GLB_IR_LED_Driver_Enable(); + + if (pin == GPIO_PIN_22) { + GLB_IR_LED_Driver_Output_Enable(GLB_IR_LED0); + } else if (pin == GPIO_PIN_18) { + GLB_IR_LED_Driver_Output_Enable(GLB_IR_LED1); + } +} + +void board_keyscan_gpio_init(void) +{ + struct bflb_device_s *gpio; + + HBN_AON_PAD_CFG_Type aonPadCfg = { + .ctrlEn = 0, + .ie = 0, + .pullUp = 0, + .pullDown = 0, + .oe = 0, + }; + HBN_Aon_Pad_Cfg(1, HBN_AON_PAD_GPIO30, &aonPadCfg); + HBN_Aon_Pad_Cfg(1, HBN_AON_PAD_GPIO31, &aonPadCfg); + HBN_Hw_Pu_Pd_Cfg(0); + + gpio = bflb_device_get_by_name("gpio"); + /* keyscan driver io init // col */ + bflb_gpio_init(gpio, GPIO_PIN_3, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_9, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_10, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_29, GPIO_FUN_KEY_SCAN_DRIVE | GPIO_ALTERNATE | GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + GLB_Set_Kys_Drv_Col(0); // GPIO output value + /* keyscan input io init // row */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_30, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // + bflb_gpio_init(gpio, GPIO_PIN_31, GPIO_FUN_KEY_SCAN_IN | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_1); // +} + +#ifdef CONFIG_BFLOG +__attribute__((weak)) uint64_t bflog_clock(void) +{ + return bflb_mtimer_get_time_us(); +} + +__attribute__((weak)) uint32_t bflog_time(void) +{ + return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)); +} + +__attribute__((weak)) char *bflog_thread(void) +{ + return ""; +} +#endif \ No newline at end of file diff --git a/bsp/board/bl702ldk/board.h b/bsp/board/bl702ldk/board.h new file mode 100644 index 000000000..daa93e45a --- /dev/null +++ b/bsp/board/bl702ldk/board.h @@ -0,0 +1,20 @@ +#ifndef _BOARD_H +#define _BOARD_H + +void board_init(void); + +void board_uartx_gpio_init(); +void board_i2c0_gpio_init(); +void board_spi0_gpio_init(); +void board_adc_gpio_init(); +void board_pwm_gpio_init(); +void board_ir_gpio_init(void); +void board_keyscan_gpio_init(void); + +#define DEFAULT_TEST_UART "uart0" +#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART0_TX +#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART0_RX +#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART0_TDR +#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART0_RDR + +#endif \ No newline at end of file diff --git a/bsp/board/bl702ldk/config/.gitkeep b/bsp/board/bl702ldk/config/.gitkeep new file mode 100644 index 000000000..e69de29bb diff --git a/bsp/board/bl702ldk/fw_header.c b/bsp/board/bl702ldk/fw_header.c new file mode 100644 index 000000000..6a04a11fd --- /dev/null +++ b/bsp/board/bl702ldk/fw_header.c @@ -0,0 +1,122 @@ +#include "fw_header.h" + +__attribute__((section(".fw_header"))) struct bootheader_t fw_header = { + .magiccode = 0x504e4642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x01, /*!< 0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M */ + .clk_cfg.cfg.pll_clk = 0x05, /*!< mcu_clk #0:RC32M, 1:XTAL, 2:DLL 26.6M, 3:DLL 42.67M, 4:DLL 64M, 5:DLL 128M */ + .clk_cfg.cfg.hclk_div = 0x00, + .clk_cfg.cfg.bclk_div = 0x01, + .clk_cfg.cfg.flash_clk_type = 0x00, /*!< #0:XCLK(RC32M or XTAL), 1:64M, 2:BCLK, 3:42.67M */ + .clk_cfg.cfg.flash_clk_div = 0x00, + .clk_cfg.crc32 = 0xdeadbeef, + + /* boot cfg */ + .boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/ + .boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .boot_cfg.bval.key_sel = 0x01, /* [5: 4] for key sel in boot interface*/ + .boot_cfg.bval.rsvd_7_6 = 0x0, /* [7: 6] for encrypt*/ + .boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */ + .boot_cfg.bval.cache_select = 0x1, /* [9] for cache */ + .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */ + .boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */ + .boot_cfg.bval.cache_way_disable = 0x0, /* [15: 12] cache way disable info*/ + .boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */ + .boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */ + .boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */ + .boot_cfg.bval.boot2_enable = 0x00, /* [19] boot2 enable */ + .boot_cfg.bval.boot2_rollback = 0x00, /* [20] boot2 rollback */ + .boot_cfg.bval.rsvd_31_21 = 0x0, /* [31:21] rsvd */ + + .img_segment_info.img_len = 0x00010000, /* image length or segment count */ + .rsvd0 = 0x00000000, + .img_start.flashoffset = 0x00001000, /* flash controller offset */ + .hash = { 0xdeadbeef }, /* hash of the image */ + + .boot2_pt_table_0 = 0x1000, /* address of partition table 0 */ + .boot2_pt_table_1 = 0x2000, /* address of partition table 1 */ + .crc32 = 0xdeadbeef /* 4 */ +}; diff --git a/bsp/board/bl702ldk/fw_header.h b/bsp/board/bl702ldk/fw_header.h new file mode 100644 index 000000000..d26d05bdc --- /dev/null +++ b/bsp/board/bl702ldk/fw_header.h @@ -0,0 +1,171 @@ +#ifndef __FW_HEADER_H__ +#define __FW_HEADER_H__ + +#include "stdint.h" +#include "stdio.h" + +struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ + uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}; + +struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { + uint32_t magiccode; + struct spi_flash_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +}; + +struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { + uint32_t magiccode; + struct sys_clk_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) aesiv_cfg_t { + uint8_t aesiv[16]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) pkey_cfg_t { + uint8_t eckeyx[32]; /* ec key in boot header */ + uint8_t eckeyy[32]; /* ec key in boot header */ + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sign_cfg_t { + uint32_t sig_len; + uint8_t signature[32]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) bootheader_t { + uint32_t magiccode; /*'BFXP'*/ + uint32_t rivison; + struct boot_flash_cfg_t flash_cfg; + struct boot_clk_cfg_t clk_cfg; + union __attribute__((packed, aligned(1))) { + struct __attribute__((packed, aligned(1))) { + uint32_t sign : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface */ + uint32_t rsvd_7_6 : 2; /* [7: 6] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t cache_select : 1; /* [9] cache enable */ + uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */ + uint32_t aes_region_lock : 1; /* [11] aes region lock */ + uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] ignore hash */ + uint32_t halt_ap : 1; /* [18] halt ap */ + uint32_t boot2_enable : 1; /* [19] boot2 enable */ + uint32_t boot2_rollback : 1; /* [20] boot2 rollback */ + uint32_t rsvd_31_21 : 11; /* [31: 21] rsvd */ + } bval; + uint32_t wval; + } boot_cfg; + + union __attribute__((packed, aligned(1))) { + uint32_t segment_cnt; + uint32_t img_len; + } img_segment_info; + + uint32_t rsvd0; /* rsvd */ + + union __attribute__((packed, aligned(1))) { + uint32_t ramaddr; + uint32_t flashoffset; + } img_start; + + uint32_t hash[32 / 4]; /*hash of the image*/ + + uint32_t boot2_pt_table_0; /* address of partition table 0 */ + uint32_t boot2_pt_table_1; /* address of partition table 1 */ + uint32_t rsvd[16]; + uint32_t crc32; +}; + +#define BFLB_FW_LENGTH_OFFSET 120 +#define BFLB_FW_HASH_OFFSET 132 + +#endif \ No newline at end of file diff --git a/drivers/lhal/config/bl702l/bl702l_irq.h b/drivers/lhal/config/bl702l/bl702l_irq.h new file mode 100644 index 000000000..c11a353fd --- /dev/null +++ b/drivers/lhal/config/bl702l/bl702l_irq.h @@ -0,0 +1,84 @@ +#ifndef __BL702L_IRQ_H +#define __BL702L_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BL702L_IRQ_NUM_BASE 16 + +#define BL702L_IRQ_MSOFT 3 +#define BL702L_IRQ_MTIME 7 +#define BL702L_IRQ_MEXT 11 +#define BL702L_IRQ_CLIC_SOFT_PEND 12 + +#define BL702L_IRQ_BMX_MCU_BUS_ERR (BL702L_IRQ_NUM_BASE + 0) +#define BL702L_IRQ_BMX_MCU_TO (BL702L_IRQ_NUM_BASE + 1) +#define BL702L_IRQ_L1C_BMX_ERR (BL702L_IRQ_NUM_BASE + 2) +#define BL702L_IRQ_L1C_BMX_TO (BL702L_IRQ_NUM_BASE + 3) +#define BL702L_IRQ_SEC_BMX_ERR (BL702L_IRQ_NUM_BASE + 4) +#define BL702L_IRQ_RF_TOP_INT0 (BL702L_IRQ_NUM_BASE + 5) +#define BL702L_IRQ_RF_TOP_INT1 (BL702L_IRQ_NUM_BASE + 6) +#define BL702L_IRQ_RESERVED0 (BL702L_IRQ_NUM_BASE + 7) +#define BL702L_IRQ_DMA_BMX_ERR (BL702L_IRQ_NUM_BASE + 8) +#define BL702L_IRQ_SEC_GMAC (BL702L_IRQ_NUM_BASE + 9) +#define BL702L_IRQ_SEC_CDET (BL702L_IRQ_NUM_BASE + 10) +#define BL702L_IRQ_SEC_PKA (BL702L_IRQ_NUM_BASE + 11) +#define BL702L_IRQ_SEC_TRNG (BL702L_IRQ_NUM_BASE + 12) +#define BL702L_IRQ_SEC_AES (BL702L_IRQ_NUM_BASE + 13) +#define BL702L_IRQ_SEC_SHA (BL702L_IRQ_NUM_BASE + 14) +#define BL702L_IRQ_DMA0_ALL (BL702L_IRQ_NUM_BASE + 15) +#define BL702L_IRQ_RESERVED1 (BL702L_IRQ_NUM_BASE + 16) +#define BL702L_IRQ_AUADC (BL702L_IRQ_NUM_BASE + 17) +#define BL702L_IRQ_RESERVED2 (BL702L_IRQ_NUM_BASE + 18) +#define BL702L_IRQ_IRTX (BL702L_IRQ_NUM_BASE + 19) +#define BL702L_IRQ_RESERVED3 (BL702L_IRQ_NUM_BASE + 20) +#define BL702L_IRQ_RESERVED4 (BL702L_IRQ_NUM_BASE + 21) +#define BL702L_IRQ_RESERVED5 (BL702L_IRQ_NUM_BASE + 22) +#define BL702L_IRQ_SF_CTRL (BL702L_IRQ_NUM_BASE + 23) +#define BL702L_IRQ_RESERVED6 (BL702L_IRQ_NUM_BASE + 24) +#define BL702L_IRQ_GPADC_DMA (BL702L_IRQ_NUM_BASE + 25) +#define BL702L_IRQ_EFUSE (BL702L_IRQ_NUM_BASE + 26) +#define BL702L_IRQ_SPI0 (BL702L_IRQ_NUM_BASE + 27) +#define BL702L_IRQ_RESERVED7 (BL702L_IRQ_NUM_BASE + 28) +#define BL702L_IRQ_UART0 (BL702L_IRQ_NUM_BASE + 29) +#define BL702L_IRQ_RESERVED8 (BL702L_IRQ_NUM_BASE + 30) +#define BL702L_IRQ_RESERVED9 (BL702L_IRQ_NUM_BASE + 31) +#define BL702L_IRQ_I2C0 (BL702L_IRQ_NUM_BASE + 32) +#define BL702L_IRQ_RESERVED10 (BL702L_IRQ_NUM_BASE + 33) +#define BL702L_IRQ_PWM (BL702L_IRQ_NUM_BASE + 34) +#define BL702L_IRQ_RESERVED11 (BL702L_IRQ_NUM_BASE + 35) +#define BL702L_IRQ_TIMER0 (BL702L_IRQ_NUM_BASE + 36) +#define BL702L_IRQ_TIMER1 (BL702L_IRQ_NUM_BASE + 37) +#define BL702L_IRQ_WDT (BL702L_IRQ_NUM_BASE + 38) +#define BL702L_IRQ_KYS (BL702L_IRQ_NUM_BASE + 39) +#define BL702L_IRQ_RESERVED12 (BL702L_IRQ_NUM_BASE + 40) +#define BL702L_IRQ_RESERVED13 (BL702L_IRQ_NUM_BASE + 41) +#define BL702L_IRQ_RESERVED14 (BL702L_IRQ_NUM_BASE + 42) +#define BL702L_IRQ_RESERVED15 (BL702L_IRQ_NUM_BASE + 43) +#define BL702L_IRQ_GPIO_INT0 (BL702L_IRQ_NUM_BASE + 44) +#define BL702L_IRQ_RESERVED16 (BL702L_IRQ_NUM_BASE + 45) +#define BL702L_IRQ_RESERVED17 (BL702L_IRQ_NUM_BASE + 46) +#define BL702L_IRQ_M154_REQ_ENH_ACK (BL702L_IRQ_NUM_BASE + 47) +#define BL702L_IRQ_M154 (BL702L_IRQ_NUM_BASE + 48) +#define BL702L_IRQ_M154_AES (BL702L_IRQ_NUM_BASE + 49) +#define BL702L_IRQ_PDS_WAKEUP (BL702L_IRQ_NUM_BASE + 50) +#define BL702L_IRQ_HBN_OUT0 (BL702L_IRQ_NUM_BASE + 51) +#define BL702L_IRQ_HBN_OUT1 (BL702L_IRQ_NUM_BASE + 52) +#define BL702L_IRQ_BOR (BL702L_IRQ_NUM_BASE + 53) +#define BL702L_IRQ_WIFI (BL702L_IRQ_NUM_BASE + 54) +#define BL616_IRQ_BZ_PHY_INT (BL702L_IRQ_NUM_BASE + 55) +#define BL702L_IRQ_BLE (BL702L_IRQ_NUM_BASE + 56) +#define BL702L_IRQ_RESERVED19 (BL702L_IRQ_NUM_BASE + 57) +#define BL702L_IRQ_RESERVED20 (BL702L_IRQ_NUM_BASE + 58) +#define BL702L_IRQ_RESERVED21 (BL702L_IRQ_NUM_BASE + 59) +#define BL702L_IRQ_RESERVED22 (BL702L_IRQ_NUM_BASE + 60) +#define BL702L_IRQ_RESERVED23 (BL702L_IRQ_NUM_BASE + 61) +#define BL702L_IRQ_24 (BL702L_IRQ_NUM_BASE + 62) +#define BL702L_IRQ_RESERVED25 (BL702L_IRQ_NUM_BASE + 63) + +#endif diff --git a/drivers/lhal/config/bl702l/bl702l_memorymap.h b/drivers/lhal/config/bl702l/bl702l_memorymap.h new file mode 100644 index 000000000..be28823d1 --- /dev/null +++ b/drivers/lhal/config/bl702l/bl702l_memorymap.h @@ -0,0 +1,82 @@ +#ifndef __BL702L_MEMORYMAP_H +#define __BL702L_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +#define BL702L_FLASH_XIP_BASE 0x23000000 +#define BL702L_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#define BL702L_FLASH_XIP_REMAP0_BASE 0x33000000 +#define BL702L_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024) +#define BL702L_FLASH_XIP_REMAP1_BASE 0x43000000 +#define BL702L_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024) +#define BL702L_FLASH_XIP_REMAP2_BASE 0x53000000 +#define BL702L_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024) + +#define BL702L_PSRAM_XIP_BASE 0x24000000 +#define BL702L_PSRAM_XIP_END (0x24000000 + 16 * 1024 * 1024) +#define BL702L_PSRAM_XIP_REMAP0_BASE 0x34000000 +#define BL702L_PSRAM_XIP_REMAP0_END (0x34000000 + 16 * 1024 * 1024) +#define BL702L_PSRAM_XIP_REMAP1_BASE 0x44000000 +#define BL702L_PSRAM_XIP_REMAP1_END (0x44000000 + 16 * 1024 * 1024) +#define BL702L_PSRAM_XIP_REMAP2_BASE 0x54000000 +#define BL702L_PSRAM_XIP_REMAP2_END (0x54000000 + 16 * 1024 * 1024) + +#define BL702L_WRAM_BASE 0x42020000 +#define BL702L_WRAM_END (0x42020000 + 80 * 1024) +#define BL702L_WRAM_REMAP0_BASE 0x22020000 +#define BL702L_WRAM_REMAP0_END (0x22020000 + 80 * 1024) +#define BL702L_WRAM_REMAP1_BASE 0x32020000 +#define BL702L_WRAM_REMAP1_END (0x32020000 + 80 * 1024) +#define BL702L_WRAM_REMAP2_BASE 0x52020000 +#define BL702L_WRAM_REMAP2_END (0x52020000 + 80 * 1024) + +#define BL702L_TCM_BASE 0x2201c000 +#define BL702L_TCM_END (0x2201c000 + 16 * 1024) +#define BL702L_TCM_REMAP0_BASE 0x3201c000 +#define BL702L_TCM_REMAP0_END (0x3201c000 + 16 * 1024) +#define BL702L_TCM_REMAP1_BASE 0x4201c000 +#define BL702L_TCM_REMAP1_END (0x4201c000 + 16 * 1024) +#define BL702L_TCM_REMAP2_BASE 0x5201c000 +#define BL702L_TCM_REMAP2_END (0x5201c000 + 16 * 1024) +/*@} end of group Memory_Map_Section */ + +/* BL702L peripherals base address */ +#define GLB_BASE ((uint32_t)0x40000000) +#define RF_BASE ((uint32_t)0x40001000) +#define BZ_PHY_BASE ((uint32_t)0x40001000) +#define BZ_PHY_AGC_BASE ((uint32_t)0x40001000) +#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */ +#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */ +#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */ +#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */ +#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */ +#define EFUSE_BASE ((uint32_t)0x40007000) +#define EF_DATA_BASE ((uint32_t)0x40007000) +#define EF_CTRL_BASE ((uint32_t)0x40007000) +#define CCI_BASE ((uint32_t)0x40008000) +#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ +#define UART0_BASE ((uint32_t)0x4000A000) +#define SPI_BASE ((uint32_t)0x4000A200) +#define I2C_BASE ((uint32_t)0x4000A300) +#define PWM_BASE ((uint32_t)0x4000A400) +#define TIMER_BASE ((uint32_t)0x4000A500) +#define IR_BASE ((uint32_t)0x4000A600) +#define CKS_BASE ((uint32_t)0x4000A700) +#define KYS_BASE ((uint32_t)0x4000A900) +#define AUADC_BASE ((uint32_t)0x4000AD00) +#define SF_CTRL_BASE ((uint32_t)0x4000B000) +#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B600) +#define DMA_BASE ((uint32_t)0x4000C000) +#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */ +#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */ +#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */ +#define MAC154_BASE ((uint32_t)0x4C000000) /*!< MAC154 module base address */ + +#define HBN_RAM_BASE ((uint32_t)0x40010000) + +#endif \ No newline at end of file diff --git a/drivers/lhal/config/bl702l/device_table.c b/drivers/lhal/config/bl702l/device_table.c new file mode 100644 index 000000000..4d06fbfa8 --- /dev/null +++ b/drivers/lhal/config/bl702l/device_table.c @@ -0,0 +1,197 @@ +#include "bflb_core.h" +#include "bl702l_irq.h" +#include "bl702l_memorymap.h" + +#define DMA_CHANNEL_OFFSET 0x100 + +struct bflb_device_s bl702l_device_table[] = { + { .name = "adc", + .reg_base = 0x40000000 - 0x400, + .irq_num = BL702L_IRQ_GPADC_DMA, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_ADC, + .user_data = NULL }, + { .name = "ef_ctrl", + .reg_base = EF_CTRL_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_EF_CTRL, + .user_data = NULL }, + { .name = "gpio", + .reg_base = GLB_BASE, + .irq_num = BL702L_IRQ_GPIO_INT0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_GPIO, + .user_data = NULL }, + { .name = "uart0", + .reg_base = UART0_BASE, + .irq_num = BL702L_IRQ_UART0, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_UART, + .user_data = NULL }, + { .name = "spi0", + .reg_base = SPI_BASE, + .irq_num = BL702L_IRQ_SPI0, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_SPI, + .user_data = NULL }, + { .name = "pwm_v1", + .reg_base = PWM_BASE + 0x20, + .irq_num = BL702L_IRQ_PWM, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PWM, + .user_data = NULL }, + { .name = "pwm_v2_0", + .reg_base = PWM_BASE + 0x40, + .irq_num = BL702L_IRQ_PWM, + .idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PWM, + .user_data = NULL }, + { .name = "dma0_ch0", + .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET, + .irq_num = BL702L_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch1", + .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET, + .irq_num = BL702L_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 1, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch2", + .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET, + .irq_num = BL702L_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 2, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "dma0_ch3", + .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET, + .irq_num = BL702L_IRQ_DMA0_ALL, + .idx = 0, + .sub_idx = 3, + .dev_type = BFLB_DEVICE_TYPE_DMA, + .user_data = NULL }, + { .name = "i2c0", + .reg_base = I2C_BASE, + .irq_num = BL702L_IRQ_I2C0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_I2C, + .user_data = NULL }, + { .name = "timer0", + .reg_base = TIMER_BASE, + .irq_num = BL702L_IRQ_TIMER0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TIMER, + .user_data = NULL }, + { .name = "timer1", + .reg_base = TIMER_BASE, + .irq_num = BL702L_IRQ_TIMER1, + .idx = 1, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TIMER, + .user_data = NULL }, + { .name = "rtc", + .reg_base = HBN_BASE, + .irq_num = BL702L_IRQ_HBN_OUT0, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_RTC, + .user_data = NULL }, + { .name = "aes", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_AES, + .user_data = NULL }, + { .name = "sha", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_SHA, + .user_data = NULL }, + { .name = "trng", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TRNG, + .user_data = NULL }, + { .name = "pka", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PKA, + .user_data = NULL }, + { .name = "watchdog", + .reg_base = TIMER_BASE, + .irq_num = BL702L_IRQ_WDT, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_TIMER, + .user_data = NULL }, + { .name = "cks", + .reg_base = CKS_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_CKS, + .user_data = NULL }, + { .name = "irtx", + .reg_base = IR_BASE, + .irq_num = BL702L_IRQ_IRTX, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_IR, + .user_data = NULL }, + { .name = "kys0", + .reg_base = KYS_BASE, + .irq_num = BL702L_IRQ_KYS, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_KYS, + .user_data = NULL }, + { .name = "auadc", + .reg_base = AUADC_BASE, + .irq_num = BL702L_IRQ_AUADC, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_AUDIOADC, + .user_data = NULL }, +}; + +struct bflb_device_s *bflb_device_get_by_name(const char *name) +{ + for (uint8_t i = 0; i < sizeof(bl702l_device_table) / sizeof(bl702l_device_table[0]); i++) { + if (strcmp(bl702l_device_table[i].name, name) == 0) { + return &bl702l_device_table[i]; + } + } + return NULL; +} + +struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx) +{ + for (uint8_t i = 0; i < sizeof(bl702l_device_table) / sizeof(bl702l_device_table[0]); i++) { + if ((bl702l_device_table[i].dev_type == type) && (bl702l_device_table[i].idx = idx)) { + return &bl702l_device_table[i]; + } + } + return NULL; +} + +void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data) +{ + device->user_data = user_data; +} \ No newline at end of file diff --git a/drivers/soc/bl702l/std/CMakeLists.txt b/drivers/soc/bl702l/std/CMakeLists.txt new file mode 100644 index 000000000..dc282d98f --- /dev/null +++ b/drivers/soc/bl702l/std/CMakeLists.txt @@ -0,0 +1,42 @@ +sdk_generate_library() + +sdk_library_add_sources(startup/start.S) +sdk_library_add_sources(startup/start_load.c) +sdk_library_add_sources(startup/system_bl702l.c) +sdk_library_add_sources(startup/interrupt.c) + +if(CONFIG_ROMAPI) +sdk_library_add_sources(src/bl702l_romapi.c) +sdk_library_add_sources(src/bl702l_romapi_patch.c) +sdk_add_compile_definitions(-DBFLB_USE_ROM_DRIVER) +else() +sdk_library_add_sources(src/bl702l_aon.c) +sdk_library_add_sources(src/bl702l_clock.c) +sdk_library_add_sources(src/bl702l_common.c) +sdk_library_add_sources(src/bl702l_glb.c) +sdk_library_add_sources(src/bl702l_hbn.c) +sdk_library_add_sources(src/bl702l_l1c.c) +sdk_library_add_sources(src/bl702l_pds.c) +endif() + +sdk_library_add_sources(src/bl702l_ef_cfg.c) +sdk_library_add_sources(src/bl702l_kys.c) +sdk_library_add_sources(src/bl702l_pm.c) +sdk_library_add_sources(src/bl702l_tzc_sec.c) + +sdk_library_add_sources(port/bl702l_clock.c) + +sdk_add_include_directories( +include +include/hardware +) + +SET(MCPU "riscv-e24") +SET(MARCH "rv32imafc") +SET(MABI "ilp32f") + +sdk_add_compile_definitions(-DARCH_RISCV -DBFLB_USE_HAL_DRIVER) +sdk_add_compile_options(-march=${MARCH} -mabi=${MABI}) +sdk_add_link_options(-march=${MARCH} -mabi=${MABI}) + +sdk_add_compile_definitions(-DCONFIG_IRQ_NUM=80) \ No newline at end of file diff --git a/drivers/soc/bl702l/std/include/bl702l_aon.h b/drivers/soc/bl702l/std/include/bl702l_aon.h new file mode 100644 index 000000000..549a6db45 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_aon.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file bl702l_aon.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_AON_H__ +#define __BL702L_AON_H__ + +#include "aon_reg.h" +#include "glb_reg.h" +#include "hbn_reg.h" +#include "pds_reg.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Public_Types + * @{ + */ + +/*@} end of group AON_Public_Types */ + +/** @defgroup AON_Public_Constants + * @{ + */ + +/*@} end of group AON_Public_Constants */ + +/** @defgroup AON_Public_Macros + * @{ + */ + +/*@} end of group AON_Public_Macros */ + +/** @defgroup AON_Public_Functions + * @{ + */ +/*----------*/ +BL_Err_Type AON_Power_On_MBG(void); +BL_Err_Type AON_Power_Off_MBG(void); +/*----------*/ +BL_Err_Type AON_Power_On_XTAL(void); +BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut); +uint8_t AON_Get_Xtal_CapCode(void); +BL_Err_Type AON_Set_Xtal_CapCode_Extra(uint8_t extra); +BL_Err_Type AON_Power_Off_XTAL(void); +/*----------*/ +BL_Err_Type AON_Power_On_BG(void); +BL_Err_Type AON_Power_Off_BG(void); +/*----------*/ +BL_Err_Type AON_Power_On_LDO11_SOC(void); +BL_Err_Type AON_Power_Off_LDO11_SOC(void); +/*----------*/ +BL_Err_Type AON_Power_On_SFReg(void); +BL_Err_Type AON_Power_Off_SFReg(void); +/*----------*/ +BL_Err_Type AON_LowPower_Enter_PDS0(void); +BL_Err_Type AON_LowPower_Exit_PDS0(void); +/*----------*/ +BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay); +/*----------*/ +BL_Err_Type AON_Set_DCDC14_Top_0(uint8_t voutSel, uint8_t vpfm); +/*----------*/ +BL_Err_Type AON_Trim_Ldo11socVoutTrim(void); +BL_Err_Type AON_Trim_Ldo14VoutTrim(void); +BL_Err_Type AON_Trim_Dcdc14VoutTrim(void); +/*----------*/ + +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_AON_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_clock.h b/drivers/soc/bl702l/std/include/bl702l_clock.h new file mode 100644 index 000000000..bb3c97ae5 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_clock.h @@ -0,0 +1,150 @@ +/** + ****************************************************************************** + * @file bl702l_clock.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_CLOCK_H__ +#define __BL702L_CLOCK_H__ + +#include "glb_reg.h" +#include "bl702l_hbn.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup CLOCK + * @{ + */ + +/** @defgroup CLOCK_Public_Types + * @{ + */ + +/** + * @brief System clock type definition + */ +typedef enum { + BL_SYSTEM_CLOCK_ROOT, /*!< ROOT clock */ + BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */ + BL_SYSTEM_CLOCK_HCLK, /*!< HCLK */ + BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */ + BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */ + BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */ + BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */ + BL_SYSTEM_CLOCK_DIG32K, /*!< DIG_32K clock */ + BL_SYSTEM_CLOCK_MTIMER, /*!< MTIMER clock */ + BL_SYSTEM_CLOCK_MAX, /*!< MAX type of system clock */ +} BL_System_Clock_Type; + +typedef enum { + BL_PERIPHERAL_CLOCK_UART0, /*!< UART0 clock */ + BL_PERIPHERAL_CLOCK_SPI0, /*!< SPI0 clock */ + BL_PERIPHERAL_CLOCK_I2C0, /*!< I2C0 clock */ + BL_PERIPHERAL_CLOCK_GPADC, /*!< GPADC clock */ + BL_PERIPHERAL_CLOCK_PWMSC, /*!< PWMSC clock */ + BL_PERIPHERAL_CLOCK_PWM, /*!< PWM clock */ + BL_PERIPHERAL_CLOCK_IR, /*!< IR clock */ + BL_PERIPHERAL_CLOCK_FLASH, /*!< FLASH clock */ + BL_PERIPHERAL_CLOCK_TIMER0_CH0,/*!< TIMER0 channel0 clock */ + BL_PERIPHERAL_CLOCK_TIMER0_CH1,/*!< TIMER0 channel1 clock */ + BL_PERIPHERAL_CLOCK_WDT, /*!< WDT clock */ + BL_PERIPHERAL_CLOCK_AUDIO, /*!< Audio clock */ + BL_PERIPHERAL_CLOCK_CHIPOUT0,/*!< chip out 0 */ + BL_PERIPHERAL_CLOCK_CHIPOUT1,/*!< chip out 1 */ + BL_PERIPHERAL_CLOCK_PKA, /*!< PKA clock */ + BL_PERIPHERAL_CLOCK_KYS, /*!< KYS clock */ + BL_PERIPHERAL_CLOCK_MAX, +} BL_Peripheral_Type; + +/*@} end of group CLOCK_Public_Types */ + +/** @defgroup CLOCK_Public_Constants + * @{ + */ + +/** @defgroup BL_SYSTEM_CLOCK_TYPE + * @{ + */ +#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_ROOT) || \ + ((type) == BL_SYSTEM_CLOCK_FCLK) || \ + ((type) == BL_SYSTEM_CLOCK_HCLK) || \ + ((type) == BL_SYSTEM_CLOCK_BCLK) || \ + ((type) == BL_SYSTEM_CLOCK_F32K) || \ + ((type) == BL_SYSTEM_CLOCK_XCLK) || \ + ((type) == BL_SYSTEM_CLOCK_XTAL) || \ + ((type) == BL_SYSTEM_CLOCK_DIG32K) || \ + ((type) == BL_SYSTEM_CLOCK_MTIMER) || \ + ((type) == BL_SYSTEM_CLOCK_MAX)) + +/*@} end of group CLOCK_Public_Constants */ + +/** @defgroup CLOCK_Public_Macros + * @{ + */ + +/*@} end of group CLOCK_Public_Macros */ + +/** @defgroup CLOCK_Public_Functions + * @{ + */ +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type); +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type); +/*----------*/ +uint32_t SystemCoreClockGet(void); +/*----------*/ +uint32_t CPU_Get_MTimer_Source_Clock(void); +uint32_t CPU_Get_MTimer_Clock(void); +uint64_t CPU_Get_MTimer_Counter(void); +uint64_t CPU_Get_CPU_Cycle(void); +uint64_t CPU_Get_MTimer_US(void); +uint64_t CPU_Get_MTimer_MS(void); +BL_Err_Type CPU_MTimer_Delay_US(uint32_t cnt); +BL_Err_Type CPU_MTimer_Delay_MS(uint32_t cnt); + +/*@} end of group CLOCK_Public_Functions */ + +/*@} end of group CLOCK */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_CLOCK_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_common.h b/drivers/soc/bl702l/std/include/bl702l_common.h new file mode 100644 index 000000000..55fb8de2d --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_common.h @@ -0,0 +1,224 @@ +#ifndef __BL702L_COMMON_H__ +#define __BL702L_COMMON_H__ + +#include "bl702l.h" +#include "bflb_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Memory access macro + */ +#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) +#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) +#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) +#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) +#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) +#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) + +#define BL_WRWD_TO_BYTEP(p, val) \ + { \ + p[0] = val & 0xff; \ + p[1] = (val >> 8) & 0xff; \ + p[2] = (val >> 16) & 0xff; \ + p[3] = (val >> 24) & 0xff; \ + } +/** + * @brief Register access macro + */ +#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) +#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) +#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) +#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) +#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) +#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) +#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) +#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) +#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) +#define BL_DRV_DUMMY \ + { \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + __ASM volatile("nop"); \ + } + +/** @defgroup COMMON_Public_Types + * @{ + */ +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +/** + * @brief Null Type definition + */ +#ifndef NULL +#define NULL 0 +#endif + +/** + * @brief Error type definition + */ +typedef enum { + SUCCESS = 0, + ERROR = 1, + TIMEOUT = 2, + INVALID = 3, /* invalid arguments */ + NORESC = 4 /* no resource or resource temperary unavailable */ +} BL_Err_Type; + +/** + * @brief Functional type definition + */ +typedef enum { + DISABLE = 0, + ENABLE = 1, +} BL_Fun_Type; + +/** + * @brief Status type definition + */ +typedef enum { + RESET = 0, + SET = 1, +} BL_Sts_Type; + +/** + * @brief Mask type definition + */ +typedef enum { + UNMASK = 0, + MASK = 1 +} BL_Mask_Type; + +/** + * @brief Logical status Type definition + */ +typedef enum { + LOGIC_LO = 0, + LOGIC_HI = !LOGIC_LO +} LogicalStatus; + +/** + * @brief Active status Type definition + */ +typedef enum { + DEACTIVE = 0, + ACTIVE = !DEACTIVE +} ActiveStatus; + +/** + * @brief Interrupt callback function type + */ +typedef void(intCallback_Type)(void); +typedef void (*pFunc)(void); + +#ifdef DEBUG +void check_failed(uint8_t *file, uint32_t line); +#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define CHECK_PARAM(expr) ((void)0) +#endif /* DEBUG */ + +#ifndef __NOP +#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */ +#endif +#ifndef __WFI +#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */ +#endif +#ifndef __WFE +#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */ +#endif +#ifndef __SEV +#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */ +#endif +#ifndef __set_MSP +#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp)) +#endif + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + //return __builtin_bswap32(value); + uint32_t res = 0; + + res = (value << 24) | (value >> 24); + res &= 0xFF0000FF; /* only for sure */ + res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000); + + return res; +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + return __builtin_bswap16(value); +} + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by setting the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("csrs mstatus, 8"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by clearing the IE-bit in the PSR. + Can only be executed in Privileged modes. + */ +__ALWAYS_STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("csrc mstatus, 8"); +} + +/** @defgroup COMMON_Public_Constants + * @{ + */ + +/** @defgroup DRIVER_INT_PERIPH + * @{ + */ +#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) + +/*@} end of group DRIVER_INT_PERIPH */ + +/** @defgroup DRIVER_INT_MASK + * @{ + */ +#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) + +/*@} end of group COMMON_Public_Constants */ + +/*@} end of group DRIVER_Public_Macro */ +#define BL702L_MemCpy arch_memcpy +#define BL702L_MemSet arch_memset +#define BL702L_MemCmp arch_memcmp +#define BL702L_MemCpy4 arch_memcpy4 +#define BL702L_MemCpy_Fast arch_memcpy_fast +#define BL702L_MemSet4 arch_memset4 + +#define BL702L_Delay_US arch_delay_us +#define BL702L_Delay_MS arch_delay_ms + +#define BFLB_Soft_CRC32 bflb_soft_crc32 +#define CPU_Interrupt_Enable(irq) +#define CPU_Interrupt_Disable(irq) +#define Interrupt_Handler_Register(irq, callback) + +void BL702L_Delay_US(uint32_t cnt); +void BL702L_Delay_MS(uint32_t cnt); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/soc/bl702l/std/include/bl702l_ef_cfg.h b/drivers/soc/bl702l/std/include/bl702l_ef_cfg.h new file mode 100644 index 000000000..c5a311393 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_ef_cfg.h @@ -0,0 +1,102 @@ +/** + ****************************************************************************** + * @file bl702l_ef_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_EF_CFG_H__ +#define __BL702L_EF_CFG_H__ + +#include "bflb_ef_ctrl.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup EF_CTRL + * @{ + */ + +/** @defgroup EF_CTRL_Public_Types + * @{ + */ +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint32_t rsvd_21_0 : 22; /*!< Reserved */ + uint32_t sf_swap_cfg : 2; /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */ + uint32_t psram_cfg : 2; /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */ + uint32_t flash_cfg : 3; /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1, 5:2MB flash */ + uint32_t rsvd_29 : 1; /*!< Reserved */ + uint32_t pkg_info : 2; /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */ +} bflb_efuse_device_info_type; + +/*@} end of group EF_CTRL_Public_Types */ + +/** @defgroup EF_CTRL_Public_Constants + * @{ + */ + +/*@} end of group EF_CTRL_Public_Constants */ + +/** @defgroup EF_CTRL_Public_Macros + * @{ + */ + +/*@} end of group EF_CTRL_Public_Macros */ + +/** @defgroup EF_CTRL_Public_Functions + * @{ + */ +void bflb_efuse_switch_cpu_clock_save(void); +void bflb_efuse_switch_cpu_clock_restore(void); +void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo); +uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list); + +/*@} end of group EF_CTRL_Public_Functions */ + +/*@} end of group EF_CTRL */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_EF_CFG_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_ef_ctrl.h b/drivers/soc/bl702l/std/include/bl702l_ef_ctrl.h new file mode 100644 index 000000000..ec6fc43c8 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_ef_ctrl.h @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file bl702l_ef_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_EF_CTRL_H__ +#define __BL702L_EF_CTRL_H__ + +#include "ef_ctrl_reg.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup EF_CTRL + * @{ + */ + +/** @defgroup EF_CTRL_Public_Types + * @{ + */ + +/** + * @brief Efuse Ctrl key slot type definition + */ +typedef enum { + EF_CTRL_KEY_SLOT0, /*!< key slot 0 */ + EF_CTRL_KEY_SLOT1, /*!< key slot 1 */ + EF_CTRL_KEY_SLOT2, /*!< key slot 2 */ + EF_CTRL_KEY_SLOT3, /*!< key slot 3 */ + EF_CTRL_KEY_SLOT4, /*!< key slot 4 */ + EF_CTRL_KEY_SLOT5, /*!< key slot 5 */ + EF_CTRL_KEY_MAX, /*!< */ +} EF_Ctrl_Key_Type; + +/** + * @brief Efuse Ctrl sign type definition + */ +typedef enum { + EF_CTRL_SIGN_NONE, /*!< no sign */ + EF_CTRL_SIGN_RSA, /*!< use RSA to sign */ + EF_CTRL_SIGN_ECC, /*!< use ECC to sign */ +} EF_Ctrl_Sign_Type; + +/** + * @brief Efuse Ctrl flash AES type definition + */ +typedef enum { + EF_CTRL_SF_AES_NONE, /*!< No AES */ + EF_CTRL_SF_AES_128, /*!< AES 128 */ + EF_CTRL_SF_AES_192, /*!< AES 192 */ + EF_CTRL_SF_AES_256, /*!< AES 256 */ +} EF_Ctrl_SF_AES_Type; + +/** + * @brief Efuse Ctrl Dbg type definition + */ +typedef enum { + EF_CTRL_DBG_OPEN = 0, /*!< Open debug */ + EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */ + EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */ +} EF_Ctrl_Dbg_Mode_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_EF_CLK, /*!< Select efuse clock */ + EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */ +} EF_Ctrl_CLK_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_PARA_DFT, /*!< Select default cyc parameter */ + EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */ +} EF_Ctrl_CYC_PARA_Type; + +/** + * @brief Efuse Ctrl clock type definition + */ +typedef enum { + EF_CTRL_OP_MODE_AUTO, /*!< Select efuse program auto mode */ + EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */ +} EF_Ctrl_OP_MODE_Type; + +/** + * @brief Efuse Ctrl secure configuration structure type definition + */ +typedef struct +{ + EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */ + uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */ + uint8_t ef_sboot_en; /*!< Secure boot enable config value */ +} EF_Ctrl_Sec_Param_Type; + + +/** + * @brief Efuse analog device info type definition + */ +typedef struct +{ + uint32_t rsvd_21_0 : 22; /*!< Reserved */ + uint32_t sf_swap_cfg : 2; /*!< 0:swap none, 1:swap SF_CS & SF_IO2, 2:swap SF_IO0 & SF_IO3, 3:swap both */ + uint32_t psram_cfg : 2; /*!< 0:no psram or external psram, others:internal psram */ + uint32_t flash_cfg : 3; /*!< 0:external flash, 1:0.5MB flash, 2:1MB flash, 3:2MB flash */ + uint32_t sf_reverse : 1; /*!< 0:no reverse, 1:reverse */ + uint32_t pkg_info : 2; /*!< 0:QFN32, 1:QFN40, 2:reserved, 3:reserved */ +} Efuse_Device_Info_Type; + +/** + * @brief Efuse Capcode type definition + */ +typedef struct +{ + uint32_t capCode : 6; /*!< Cap code value */ + uint32_t parity : 1; /*!< Parity of capcode */ + uint32_t en : 1; /*!< Enable status */ + uint32_t rsvd : 24; /*!< Reserved */ +} Efuse_Capcode_Info_Type; + +/** + * @brief Efuse common trim type definition + */ +typedef struct +{ + uint8_t en; /*!< Enable status */ + uint8_t parity; /*!< Trim parity */ + uint8_t empty; /*!< Trim empty */ + uint8_t len; /*!< Trim value len in bit */ + uint32_t value; /*!< Trim value */ +} Efuse_Common_Trim_Type; + +/*@} end of group EF_CTRL_Public_Types */ + +/** @defgroup EF_CTRL_Public_Constants + * @{ + */ + +/** @defgroup EF_CTRL_KEY_TYPE + * @{ + */ +#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \ + ((type) == EF_CTRL_KEY_SLOT1) || \ + ((type) == EF_CTRL_KEY_SLOT2) || \ + ((type) == EF_CTRL_KEY_SLOT3) || \ + ((type) == EF_CTRL_KEY_SLOT4) || \ + ((type) == EF_CTRL_KEY_SLOT5) || \ + ((type) == EF_CTRL_KEY_MAX)) + +/** @defgroup EF_CTRL_SIGN_TYPE + * @{ + */ +#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \ + ((type) == EF_CTRL_SIGN_RSA) || \ + ((type) == EF_CTRL_SIGN_ECC)) + +/** @defgroup EF_CTRL_SF_AES_TYPE + * @{ + */ +#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \ + ((type) == EF_CTRL_SF_AES_128) || \ + ((type) == EF_CTRL_SF_AES_192) || \ + ((type) == EF_CTRL_SF_AES_256)) + +/** @defgroup EF_CTRL_DBG_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) || \ + ((type) == EF_CTRL_DBG_PASSWORD) || \ + ((type) == EF_CTRL_DBG_CLOSE)) + +/** @defgroup EF_CTRL_CLK_TYPE + * @{ + */ +#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \ + ((type) == EF_CTRL_SAHB_CLK)) + +/** @defgroup EF_CTRL_CYC_PARA_TYPE + * @{ + */ +#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \ + ((type) == EF_CTRL_PARA_MANUAL)) + +/** @defgroup EF_CTRL_OP_MODE_TYPE + * @{ + */ +#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \ + ((type) == EF_CTRL_OP_MODE_MANUAL)) + +/*@} end of group EF_CTRL_Public_Constants */ + +/** @defgroup EF_CTRL_Public_Macros + * @{ + */ +#define EF_CTRL_EFUSE_R0_SIZE 128 + +/*@} end of group EF_CTRL_Public_Macros */ + +/** @defgroup EF_CTRL_Public_Functions + * @{ + */ +void EF_Ctrl_Sw_AHB_Clk_0(void); +void EF_Ctrl_Load_Efuse_R0(void); +void EF_Ctrl_Program_Efuse_0(void); +BL_Sts_Type EF_Ctrl_Busy(void); +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void); +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program); +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh); +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program); +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program); +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg); +void EF_Ctrl_Write_Secure_Boot(uint8_t sign[1], uint8_t aes[1], uint8_t program); +void EF_Ctrl_Read_Secure_Boot(uint8_t sign[1], uint8_t aes[1]); +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program); +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage); +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program); +uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val); +uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len); +void EF_Ctrl_Write_MAC_Address(uint8_t mac[8], uint8_t program); +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]); +void EF_Ctrl_Writelock_MAC_Address(uint8_t program); +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]); +/*----------*/ +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo); +uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program); +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload); +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload); +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program); +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload); +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program); +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len); +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program); +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len); +void EF_Ctrl_Clear(uint32_t index, uint32_t len); +void EF_Ctrl_Crc_Enable(void); +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void); +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue); +BL_Err_Type EF_Ctrl_Crc_Result(void); + +/*@} end of group EF_CTRL_Public_Functions */ + +/*@} end of group EF_CTRL */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_EF_CTRL_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_glb.h b/drivers/soc/bl702l/std/include/bl702l_glb.h new file mode 100644 index 000000000..bdc63c2cc --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_glb.h @@ -0,0 +1,885 @@ +/** + ****************************************************************************** + * @file bl702l_glb.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_GLB_H__ +#define __BL702L_GLB_H__ + +#include "glb_reg.h" +#include "pds_reg.h" +#include "bl702l_glb_gpio.h" +#include "bl702l_gpio.h" +#include "bl702l_l1c.h" +#include "bl702l_hbn.h" +#include "bl702l_aon.h" +#include "bl702l_ef_cfg.h" +#include "bl702l_pds.h" +#include "bl702l_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Public_Types + * @{ + */ + +/** + * @brief GLB IR_LED type definition + */ +typedef enum { + GLB_IR_LED0, /*!< IR_LED0 */ + GLB_IR_LED1, /*!< IR_LED1 */ +} GLB_IR_LED_Type; + +/** + * @brief GLB root clock type definition + */ +typedef enum { + GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */ + GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */ + GLB_ROOT_CLK_DLL, /*!< root clock select DLL others */ +} GLB_ROOT_CLK_Type; + +/** + * @brief GLB system clock type definition + */ +typedef enum { + GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */ + GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */ + GLB_SYS_CLK_DLL25P6M, /*!< use DLL output 25.6MHz as system clock */ + GLB_SYS_CLK_DLL42P67M, /*!< use DLL output 42.67MHz as system clock */ + GLB_SYS_CLK_DLL64M, /*!< use DLL output 64MHz as system clock */ + GLB_SYS_CLK_DLL128M, /*!< use DLL output 128MHz as system clock */ +} GLB_SYS_CLK_Type; + +/** + * @brief GLB AUDIO clock source type definition + */ +typedef enum { + GLB_AUDIO_CLK_SRC_2P032M, /*!< Select 2.032MHz as AUDIO clock source */ + GLB_AUDIO_CLK_SRC_6P095M, /*!< Select 6.095MHz as AUDIO clock source */ +} GLB_AUDIO_CLK_SRC_Type; + +/** + * @brief GLB KYS clock source type definition + */ +typedef enum { + GLB_KYS_CLK_SRC_XCLK, /*!< KYS clock source select XCLK */ + GLB_KYS_CLK_SRC_F32K, /*!< KYS clock source select f32k */ +} GLB_KYS_CLK_SRC_Type; + +/** + * @brief GLB DMA clock ID type definition + */ +typedef enum { + GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */ + GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */ + GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */ + GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */ +} GLB_DMA_CLK_ID_Type; + +/** + * @brief GLB IR clock source type definition + */ +typedef enum { + GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */ +} GLB_IR_CLK_SRC_Type; + +/** + * @brief GLB flash clock type definition + */ +typedef enum { + GLB_SFLASH_CLK_XCLK, /*!< Select XCLK as flash clock */ + GLB_SFLASH_CLK_64M, /*!< Select 64M as flash clock */ + GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */ + GLB_SFLASH_CLK_42P67M, /*!< Select 42.67M as flash clock */ +} GLB_SFLASH_CLK_Type; + +/** + * @brief GLB chip clock out 0 type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_0_NONE, /*!< no chip clock out */ + GLB_CHIP_CLK_OUT_0_2P032M, /*!< DLL div63 2.032MHz clock out */ + GLB_CHIP_CLK_OUT_0_6P095M, /*!< DLL div21 6.095MHz clock out */ + GLB_CHIP_CLK_OUT_0_XCLK, /*!< clk_xclk */ +} GLB_CHIP_CLK_OUT_0_Type; + +/** + * @brief GLB chip clock out 1 type definition + */ +typedef enum { + GLB_CHIP_CLK_OUT_1_NONE, /*!< no chip clock out */ + GLB_CHIP_CLK_OUT_1_F32K, /*!< f32k clock out */ + GLB_CHIP_CLK_OUT_1_ANA_XTAL, /*!< ana xtal clock out */ + GLB_CHIP_CLK_OUT_1_DIG_XTAL, /*!< dig xtal clock out */ +} GLB_CHIP_CLK_OUT_1_Type; + +/** + * @brief GLB I2C clock source type definition + */ +typedef enum { + GLB_I2C_CLK_SRC_BCLK, /*!< I2C clock source select BCLK */ + GLB_I2C_CLK_SRC_XCLK, /*!< I2C clock source select XCLK */ +} GLB_I2C_CLK_SRC_Type; + +/** + * @brief GLB SPI clock source type definition + */ +typedef enum { + GLB_SPI_CLK_SRC_BCLK, /*!< SPI clock source select BCLK */ + GLB_SPI_CLK_SRC_XCLK, /*!< SPI clock source select XCLK */ +} GLB_SPI_CLK_SRC_Type; + +/** + * @brief GLB SPI pad action type definition + */ +typedef enum { + GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */ + GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */ +} GLB_SPI_PAD_ACT_AS_Type; + +/** + * @brief GLB PKA clock source type definition + */ +typedef enum { + GLB_PKA_CLK_SRC_HCLK, /*!< PKA clock source select HCLK */ + GLB_PKA_CLK_SRC_DLL128M, /*!< PKA clock source select DLL128M */ + GLB_PKA_CLK_SRC_DLL64M, /*!< PKA clock source select DLL64M */ + GLB_PKA_CLK_SRC_DLL42P67M, /*!< PKA clock source select DLL42.67M */ +} GLB_PKA_CLK_SRC_Type; + +/** + * @brief BMX arb mode type definition + */ +typedef enum { + BMX_ARB_FIX, /*!< 0->fix */ + BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + BMX_ARB_RANDOM, /*!< 3->random */ +} BMX_ARB_Type; + +/** + * @brief GLB AHB software type definition + */ +typedef enum { + GLB_AHB_MCU_SW_M154 = 4, + GLB_AHB_MCU_SW_BLE = 8, + GLB_AHB_MCU_SW_GLB = 32, + GLB_AHB_MCU_SW_MIX = 33, + GLB_AHB_MCU_SW_GPIP = 34, + GLB_AHB_MCU_SW_SEC_DBG = 35, + GLB_AHB_MCU_SW_SEC_ENG = 36, + GLB_AHB_MCU_SW_TZ1 = 37, + GLB_AHB_MCU_SW_TZ2 = 38, + GLB_AHB_MCU_SW_EFUSE = 39, + GLB_AHB_MCU_SW_CCI = 40, + GLB_AHB_MCU_SW_L1C = 41, + GLB_AHB_MCU_SW_SF = 43, + GLB_AHB_MCU_SW_DMA = 44, + GLB_AHB_MCU_SW_PDS = 46, + GLB_AHB_MCU_SW_UART0 = 48, + GLB_AHB_MCU_SW_SPI = 50, + GLB_AHB_MCU_SW_I2C = 51, + GLB_AHB_MCU_SW_PWM = 52, + GLB_AHB_MCU_SW_TIMER = 53, + GLB_AHB_MCU_SW_IR_REMOTE = 54, + GLB_AHB_MCU_SW_CHECKSUM = 55, + GLB_AHB_MCU_SW_KYS = 57, + GLB_AHB_MCU_SW_AUSOLO = 61, + GLB_AHB_MCU_SW_PWRON_RST = 64, + GLB_AHB_MCU_SW_CPU_RESET = 65, + GLB_AHB_MCU_SW_SYS_RESET = 66, +} GLB_AHB_MCU_SW_Type; + +/** + * @brief GLB dis reset type definition + */ +typedef enum { + GLB_DISRST_MIX = 1, + GLB_DISRST_GPIP = 2, + GLB_DISRST_CCI = 8, + GLB_DISRST_SF = 11, + GLB_DISRST_DMA = 12, + GLB_DISRST_UART0 = 16, + GLB_DISRST_SPI = 18, + GLB_DISRST_I2C = 19, + GLB_DISRST_PWM = 20, + GLB_DISRST_TIMER = 21, + GLB_DISRST_IR_REMOTE = 22, + GLB_DISRST_CHECKSUM = 23, + GLB_DISRST_KYS = 25, + GLB_DISRST_AUSOLO = 29, +} GLB_DISRST_Type; + +/** + * @brief BMX configuration structure type definition + */ +typedef struct { + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} BMX_Cfg_Type; + +/** + * @brief RTC mode type definition + */ +typedef enum { + RTC_MODE_LOWPOWER, /*!< RTC work on low power mode */ + RTC_MODE_NORMAL, /*!< RTC work on normal mode */ +} RTC_MODE_Type; + +/** + * @brief BMX bus err type definition + */ +typedef enum { + BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} BMX_BUS_ERR_Type; + +/** + * @brief BMX bus err interrupt type definition + */ +typedef enum { + BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */ + BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */ +} BMX_ERR_INT_Type; + +/** + * @brief BMX time out interrupt type definition + */ +typedef enum { + BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */ + BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */ +} BMX_TO_INT_Type; + +/** + * @brief GLB EM type definition + */ +typedef enum { + GLB_EM_0KB = 0x0, /*!< 0x0 --> 0KB */ + GLB_EM_8KB = 0x3, /*!< 0x3 --> 8KB */ + GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */ +} GLB_EM_Type; + +/** + * @brief GLB MTIMER clock type definition + */ +typedef enum { + GLB_MTIMER_CLK_XCLK, /*!< BUS clock */ + GLB_MTIMER_CLK_F32K, /*!< 32KHz */ +} GLB_MTIMER_CLK_Type; + +/** + * @brief GLB ADC clock source type definition + */ +typedef enum { + GLB_ADC_CLK_SRC_F32K, /*!< ADC clock source select F32K */ + GLB_ADC_CLK_SRC_XCLK, /*!< ADC clock source select XCLK */ +} GLB_ADC_CLK_SRC_Type; + +/** + * @brief GLB DIG clock source select type definition + */ +typedef enum { + GLB_DIG_CLK_SRC_XTAL32M, /*!< select XTAL32M as DIG clock source */ + GLB_DIG_CLK_SRC_RC32M, /*!< select RC32M as DIG clock source */ +} GLB_DIG_CLK_SRC_Type; + +/** + * @brief GLB BT bandwidth type definition + */ +typedef enum { + GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */ + GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */ +} GLB_BT_BANDWIDTH_Type; + +/** + * @brief GLB UART signal type definition + */ +typedef enum { + GLB_UART_SIG_0, /*!< UART signal 0 */ + GLB_UART_SIG_1, /*!< UART signal 1 */ + GLB_UART_SIG_2, /*!< UART signal 2 */ + GLB_UART_SIG_3, /*!< UART signal 3 */ +} GLB_UART_SIG_Type; + +/** + * @brief GLB UART signal function type definition + */ +typedef enum { + GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */ + GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */ + GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */ + GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */ +} GLB_UART_SIG_FUN_Type; + +/** + * @brief GLB DLL output clock type definition + */ +typedef enum { + GLB_DLL_CLK_RF, /*!< DLL output div1 RF clock */ + GLB_DLL_CLK_2P032M, /*!< DLL output 2.032MHz clock */ + GLB_DLL_CLK_6P095M, /*!< DLL output 6.095MHz clock */ + GLB_DLL_CLK_25P6M, /*!< DLL output 25.6MHz clock */ + GLB_DLL_CLK_42P67M, /*!< DLL output 42.67MHz clock */ + GLB_DLL_CLK_64M, /*!< DLL output 64MHz clock */ + GLB_DLL_CLK_128M, /*!< DLL output 128MHz clock */ +} GLB_DLL_CLK_Type; + +/** + * @brief PLL XTAL type definition + */ +typedef enum { + GLB_DLL_XTAL_NONE, /*!< XTAL is none */ + GLB_DLL_XTAL_32M, /*!< XTAL is 32M */ + GLB_DLL_XTAL_RC32M, /*!< XTAL is RC32M */ +} GLB_DLL_XTAL_Type; + +/** + * @brief GLB AHB clock IP type definition + */ +typedef enum { + GLB_AHB_CLOCK_IP_CPU, + GLB_AHB_CLOCK_IP_SDU, + GLB_AHB_CLOCK_IP_SEC, + GLB_AHB_CLOCK_IP_DMA_0, + GLB_AHB_CLOCK_IP_DMA_1, + GLB_AHB_CLOCK_IP_DMA_2, + GLB_AHB_CLOCK_IP_CCI, + GLB_AHB_CLOCK_IP_RF_TOP, + GLB_AHB_CLOCK_IP_GPIP, + GLB_AHB_CLOCK_IP_TZC, + GLB_AHB_CLOCK_IP_EF_CTRL, + GLB_AHB_CLOCK_IP_SF_CTRL, + GLB_AHB_CLOCK_IP_EMAC, + GLB_AHB_CLOCK_IP_UART0, + GLB_AHB_CLOCK_IP_UART1, + GLB_AHB_CLOCK_IP_UART2, + GLB_AHB_CLOCK_IP_UART3, + GLB_AHB_CLOCK_IP_UART4, + GLB_AHB_CLOCK_IP_SPI, + GLB_AHB_CLOCK_IP_I2C, + GLB_AHB_CLOCK_IP_PWM, + GLB_AHB_CLOCK_IP_TIMER, + GLB_AHB_CLOCK_IP_IR, + GLB_AHB_CLOCK_IP_CHECKSUM, + GLB_AHB_CLOCK_IP_QDEC, + GLB_AHB_CLOCK_IP_KYS, + GLB_AHB_CLOCK_IP_I2S, + GLB_AHB_CLOCK_IP_USB11, + GLB_AHB_CLOCK_IP_CAM, + GLB_AHB_CLOCK_IP_MJPEG, + GLB_AHB_CLOCK_IP_BT_BLE_NORMAL, + GLB_AHB_CLOCK_IP_BT_BLE_LP, + GLB_AHB_CLOCK_IP_ZB_NORMAL, + GLB_AHB_CLOCK_IP_ZB_LP, + GLB_AHB_CLOCK_IP_WIFI_NORMAL, + GLB_AHB_CLOCK_IP_WIFI_LP, + GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL, + GLB_AHB_CLOCK_IP_BT_BLE_2_LP, + GLB_AHB_CLOCK_IP_EMI_MISC, + GLB_AHB_CLOCK_IP_PSRAM0_CTRL, + GLB_AHB_CLOCK_IP_PSRAM1_CTRL, + GLB_AHB_CLOCK_IP_USB20_SDU, + GLB_AHB_CLOCK_IP_MIX2, + GLB_AHB_CLOCK_IP_AUDIO, + GLB_AHB_CLOCK_IP_SDH, + GLB_AHB_CLOCK_IP_ZB2_NORMAL, + GLB_AHB_CLOCK_IP_ZB2_LP, + GLB_AHB_CLOCK_IP_I2C1, + GLB_AHB_CLOCK_IP_WIFI_PHY, + GLB_AHB_CLOCK_IP_WIFI_MAC_PHY, + GLB_AHB_CLOCK_IP_WIFI_PLATFORM, + GLB_AHB_CLOCK_IP_LZ4, + GLB_AHB_CLOCK_IP_AUPDM, + GLB_AHB_CLOCK_IP_GAUGE, + GLB_AHB_CLOCK_IP_DBI, + GLB_AHB_CLOCK_IP_PEC, + GLB_AHB_CLOCK_IP_ISO11898, + GLB_AHB_CLOCK_IP_AUSOLO_TOP, + GLB_AHB_CLOCK_IP_DMA_GPIO, + GLB_AHB_CLOCK_IP_MM_MISC, +} GLB_AHB_CLOCK_IP_Type; + +/*@} end of group GLB_Public_Types */ + +/** @defgroup GLB_Public_Constants + * @{ + */ + +/** @defgroup GLB_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_IR_LED_TYPE(type) (((type) == GLB_IR_LED0) || \ + ((type) == GLB_IR_LED1)) + +/** @defgroup GLB_ROOT_CLK_TYPE + * @{ + */ +#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \ + ((type) == GLB_ROOT_CLK_XTAL) || \ + ((type) == GLB_ROOT_CLK_DLL)) + +/** @defgroup GLB_SYS_CLK_TYPE + * @{ + */ +#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \ + ((type) == GLB_SYS_CLK_XTAL) || \ + ((type) == GLB_SYS_CLK_DLL25P6M) || \ + ((type) == GLB_SYS_CLK_DLL42P67M) || \ + ((type) == GLB_SYS_CLK_DLL64M) || \ + ((type) == GLB_SYS_CLK_DLL128M)) + +/** @defgroup GLB_AUDIO_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_AUDIO_CLK_SRC_TYPE(type) (((type) == GLB_AUDIO_CLK_SRC_2P032M) || \ + ((type) == GLB_AUDIO_CLK_SRC_6P095M)) + +/** @defgroup GLB_KYS_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_KYS_CLK_SRC_TYPE(type) (((type) == GLB_KYS_CLK_SRC_XCLK) || \ + ((type) == GLB_KYS_CLK_SRC_F32K)) + +/** @defgroup GLB_DMA_CLK_ID_TYPE + * @{ + */ +#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \ + ((type) == GLB_DMA_CLK_DMA0_CH1) || \ + ((type) == GLB_DMA_CLK_DMA0_CH2) || \ + ((type) == GLB_DMA_CLK_DMA0_CH3)) + +/** @defgroup GLB_IR_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK)) + +/** @defgroup GLB_I2C_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_I2C_CLK_SRC_TYPE(type) (((type) == GLB_I2C_CLK_SRC_BCLK) || \ + ((type) == GLB_I2C_CLK_SRC_XCLK)) + +/** @defgroup GLB_SPI_CLK_SRC_TYPE + * @{ + */ +#define IS_GLB_SPI_CLK_SRC_TYPE(type) (((type) == GLB_SPI_CLK_SRC_BCLK) || \ + ((type) == GLB_SPI_CLK_SRC_XCLK)) + +/** @defgroup GLB_SFLASH_CLK_TYPE + * @{ + */ +#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_XCLK) || \ + ((type) == GLB_SFLASH_CLK_64M) || \ + ((type) == GLB_SFLASH_CLK_BCLK) || \ + ((type) == GLB_SFLASH_CLK_42P67M)) + +/** @defgroup GLB_CHIP_CLK_OUT_1_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_1_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_1_NONE) || \ + ((type) == GLB_CHIP_CLK_OUT_1_F32K) || \ + ((type) == GLB_CHIP_CLK_OUT_1_ANA_XTAL) || \ + ((type) == GLB_CHIP_CLK_OUT_1_DIG_XTAL)) + +/** @defgroup GLB_CHIP_CLK_OUT_0_TYPE + * @{ + */ +#define IS_GLB_CHIP_CLK_OUT_0_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_0_NONE) || \ + ((type) == GLB_CHIP_CLK_OUT_0_2P032M) || \ + ((type) == GLB_CHIP_CLK_OUT_0_6P095M) || \ + ((type) == GLB_CHIP_CLK_OUT_0_XCLK)) + +/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE + * @{ + */ +#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \ + ((type) == GLB_SPI_PAD_ACT_AS_MASTER)) + +/** @defgroup GLB_PKA_CLK_TYPE + * @{ + */ +#define IS_GLB_PKA_CLK_SRC_TYPE(type) (((type) == GLB_PKA_CLK_SRC_HCLK) || \ + ((type) == GLB_PKA_CLK_SRC_DLL128M) || \ + ((type) == GLB_PKA_CLK_SRC_DLL64M) || \ + ((type) == GLB_PKA_CLK_SRC_DLL42P67M)) + +/** @defgroup GLB_AHB_SW_TYPE + * @{ + */ +#define IS_GLB_AHB_MCU_SW_TYPE(type) (((type) == GLB_AHB_MCU_SW_M154) || \ + ((type) == GLB_AHB_MCU_SW_BLE) || \ + ((type) == GLB_AHB_MCU_SW_GLB) || \ + ((type) == GLB_AHB_MCU_SW_MIX) || \ + ((type) == GLB_AHB_MCU_SW_GPIP) || \ + ((type) == GLB_AHB_MCU_SW_SEC_DBG) || \ + ((type) == GLB_AHB_MCU_SW_SEC_ENG) || \ + ((type) == GLB_AHB_MCU_SW_TZ1) || \ + ((type) == GLB_AHB_MCU_SW_TZ2) || \ + ((type) == GLB_AHB_MCU_SW_EFUSE) || \ + ((type) == GLB_AHB_MCU_SW_CCI) || \ + ((type) == GLB_AHB_MCU_SW_L1C) || \ + ((type) == GLB_AHB_MCU_SW_SF) || \ + ((type) == GLB_AHB_MCU_SW_DMA) || \ + ((type) == GLB_AHB_MCU_SW_PDS) || \ + ((type) == GLB_AHB_MCU_SW_UART0) || \ + ((type) == GLB_AHB_MCU_SW_SPI) || \ + ((type) == GLB_AHB_MCU_SW_I2C) || \ + ((type) == GLB_AHB_MCU_SW_PWM) || \ + ((type) == GLB_AHB_MCU_SW_TIMER) || \ + ((type) == GLB_AHB_MCU_SW_IR_REMOTE) || \ + ((type) == GLB_AHB_MCU_SW_CHECKSUM) || \ + ((type) == GLB_AHB_MCU_SW_KYS) || \ + ((type) == GLB_AHB_MCU_SW_AUSOLO) || \ + ((type) == GLB_AHB_MCU_SW_PWRON_RST) || \ + ((type) == GLB_AHB_MCU_SW_CPU_RESET) || \ + ((type) == GLB_AHB_MCU_SW_SYS_RESET)) + +/** @defgroup GLB DISRST_TYPE + * @{ + */ +#define IS_GLB_DISRST_TYPE(type) (((type) == GLB_DISRST_MIX) || \ + ((type) == GLB_DISRST_GPIP) || \ + ((type) == GLB_DISRST_CCI) || \ + ((type) == GLB_DISRST_SF) || \ + ((type) == GLB_DISRST_DMA) || \ + ((type) == GLB_DISRST_UART0) || \ + ((type) == GLB_DISRST_SPI) || \ + ((type) == GLB_DISRST_I2C) || \ + ((type) == GLB_DISRST_PWM) || \ + ((type) == GLB_DISRST_TIMER) || \ + ((type) == GLB_DISRST_IR_REMOTE) || \ + ((type) == GLB_DISRST_CHECKSUM) || \ + ((type) == GLB_DISRST_KYS) || \ + ((type) == GLB_DISRST_AUSOLO)) + +/** @defgroup RTC_MODE_TYPE + * @{ + */ +#define IS_RTC_MODE_TYPE(type) (((type) == RTC_MODE_LOWPOWER) || \ + ((type) == RTC_MODE_NORMAL)) + +/** @defgroup BMX_ARB_TYPE + * @{ + */ +#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \ + ((type) == BMX_ARB_ROUND_ROBIN) || \ + ((type) == BMX_ARB_RANDOM)) + +/** @defgroup BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup BMX_ERR_INT_TYPE + * @{ + */ +#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \ + ((type) == BMX_ERR_INT_ALL)) + +/** @defgroup BMX_TO_INT_TYPE + * @{ + */ +#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \ + ((type) == BMX_TO_INT_ALL)) + +/** @defgroup GLB_EM_TYPE + * @{ + */ +#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \ + ((type) == GLB_EM_8KB) || \ + ((type) == GLB_EM_16KB)) + +/** @defgroup GLB_MTIMER_CLK_TYPE + * @{ + */ +#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_XCLK) || \ + ((type) == GLB_MTIMER_CLK_F32K)) + +/** @defgroup GLB_ADC_CLK_TYPE + * @{ + */ +#define IS_GLB_ADC_CLK_SRC_TYPE(type) (((type) == GLB_ADC_CLK_SRC_F32K) || \ + ((type) == GLB_ADC_CLK_SRC_XCLK)) + +/** @defgroup GLB_DIG_CLK_TYPE + * @{ + */ +#define IS_GLB_DIG_CLK_SRC_TYPE(type) (((type) == GLB_DIG_CLK_SRC_XTAL32M) || \ + ((type) == GLB_DIG_CLK_SRC_RC32M)) + +/** @defgroup GLB_BT_BANDWIDTH_TYPE + * @{ + */ +#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \ + ((type) == GLB_BT_BANDWIDTH_2M)) + +/** @defgroup GLB_UART_SIG_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \ + ((type) == GLB_UART_SIG_1) || \ + ((type) == GLB_UART_SIG_2) || \ + ((type) == GLB_UART_SIG_3)) + +/** @defgroup GLB_UART_SIG_FUN_TYPE + * @{ + */ +#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \ + ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \ + ((type) == GLB_UART_SIG_FUN_UART0_RXD)) + +/** @defgroup GLB_DLL_CLK_TYPE + * @{ + */ +#define IS_GLB_DLL_CLK_TYPE(type) (((type) == GLB_DLL_CLK_RF) || \ + ((type) == GLB_DLL_CLK_2P032M) || \ + ((type) == GLB_DLL_CLK_6P095M) || \ + ((type) == GLB_DLL_CLK_25P6M) || \ + ((type) == GLB_DLL_CLK_42P67M) || \ + ((type) == GLB_DLL_CLK_64M) || \ + ((type) == GLB_DLL_CLK_128M)) + +/** @defgroup GLB_DLL_XTAL_TYPE + * @{ + */ +#define IS_GLB_DLL_XTAL_TYPE(type) (((type) == GLB_DLL_XTAL_NONE) || \ + ((type) == GLB_DLL_XTAL_32M) || \ + ((type) == GLB_DLL_XTAL_RC32M)) + +/*@} end of group GLB_Public_Constants */ + +/** @defgroup GLB_Public_Macros + * @{ + */ +#define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */ +#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */ + +#define GLB_AHB_CLOCK_CPU (1ULL << GLB_AHB_CLOCK_IP_CPU) +#define GLB_AHB_CLOCK_SDU (1ULL << GLB_AHB_CLOCK_IP_SDU) +#define GLB_AHB_CLOCK_SEC (1ULL << GLB_AHB_CLOCK_IP_SEC) +#define GLB_AHB_CLOCK_DMA_0 (1ULL << GLB_AHB_CLOCK_IP_DMA_0) +#define GLB_AHB_CLOCK_DMA_1 (1ULL << GLB_AHB_CLOCK_IP_DMA_1) +#define GLB_AHB_CLOCK_DMA_2 (1ULL << GLB_AHB_CLOCK_IP_DMA_2) +#define GLB_AHB_CLOCK_CCI (1ULL << GLB_AHB_CLOCK_IP_CCI) +#define GLB_AHB_CLOCK_RF_TOP (1ULL << GLB_AHB_CLOCK_IP_RF_TOP) +#define GLB_AHB_CLOCK_GPIP (1ULL << GLB_AHB_CLOCK_IP_GPIP) +#define GLB_AHB_CLOCK_TZC (1ULL << GLB_AHB_CLOCK_IP_TZC) +#define GLB_AHB_CLOCK_EF_CTRL (1ULL << GLB_AHB_CLOCK_IP_EF_CTRL) +#define GLB_AHB_CLOCK_SF_CTRL (1ULL << GLB_AHB_CLOCK_IP_SF_CTRL) +#define GLB_AHB_CLOCK_EMAC (1ULL << GLB_AHB_CLOCK_IP_EMAC) +#define GLB_AHB_CLOCK_UART0 (1ULL << GLB_AHB_CLOCK_IP_UART0) +#define GLB_AHB_CLOCK_UART1 (1ULL << GLB_AHB_CLOCK_IP_UART1) +#define GLB_AHB_CLOCK_UART2 (1ULL << GLB_AHB_CLOCK_IP_UART2) +#define GLB_AHB_CLOCK_UART3 (1ULL << GLB_AHB_CLOCK_IP_UART3) +#define GLB_AHB_CLOCK_UART4 (1ULL << GLB_AHB_CLOCK_IP_UART4) +#define GLB_AHB_CLOCK_SPI (1ULL << GLB_AHB_CLOCK_IP_SPI) +#define GLB_AHB_CLOCK_I2C (1ULL << GLB_AHB_CLOCK_IP_I2C) +#define GLB_AHB_CLOCK_PWM (1ULL << GLB_AHB_CLOCK_IP_PWM) +#define GLB_AHB_CLOCK_TIMER (1ULL << GLB_AHB_CLOCK_IP_TIMER) +#define GLB_AHB_CLOCK_IR (1ULL << GLB_AHB_CLOCK_IP_IR) +#define GLB_AHB_CLOCK_CHECKSUM (1ULL << GLB_AHB_CLOCK_IP_CHECKSUM) +#define GLB_AHB_CLOCK_QDEC (1ULL << GLB_AHB_CLOCK_IP_QDEC) +#define GLB_AHB_CLOCK_KYS (1ULL << GLB_AHB_CLOCK_IP_KYS) +#define GLB_AHB_CLOCK_I2S (1ULL << GLB_AHB_CLOCK_IP_I2S) +#define GLB_AHB_CLOCK_USB11 (1ULL << GLB_AHB_CLOCK_IP_USB11) +#define GLB_AHB_CLOCK_CAM (1ULL << GLB_AHB_CLOCK_IP_CAM) +#define GLB_AHB_CLOCK_MJPEG (1ULL << GLB_AHB_CLOCK_IP_MJPEG) +#define GLB_AHB_CLOCK_BT_BLE_NORMAL (1ULL << GLB_AHB_CLOCK_IP_BT_BLE_NORMAL) +#define GLB_AHB_CLOCK_BT_BLE_LP (1ULL << GLB_AHB_CLOCK_IP_BT_BLE_LP) +#define GLB_AHB_CLOCK_ZB_NORMAL (1ULL << GLB_AHB_CLOCK_IP_ZB_NORMAL) +#define GLB_AHB_CLOCK_ZB_LP (1ULL << GLB_AHB_CLOCK_IP_ZB_LP) +#define GLB_AHB_CLOCK_WIFI_NORMAL (1ULL << GLB_AHB_CLOCK_IP_WIFI_NORMAL) +#define GLB_AHB_CLOCK_WIFI_LP (1ULL << GLB_AHB_CLOCK_IP_WIFI_LP) +#define GLB_AHB_CLOCK_BT_BLE_2_NORMAL (1ULL << GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL) +#define GLB_AHB_CLOCK_BT_BLE_2_LP (1ULL << GLB_AHB_CLOCK_IP_BT_BLE_2_LP) +#define GLB_AHB_CLOCK_EMI_MISC (1ULL << GLB_AHB_CLOCK_IP_EMI_MISC) +#define GLB_AHB_CLOCK_PSRAM0_CTRL (1ULL << GLB_AHB_CLOCK_IP_PSRAM0_CTRL) +#define GLB_AHB_CLOCK_PSRAM1_CTRL (1ULL << GLB_AHB_CLOCK_IP_PSRAM1_CTRL) +#define GLB_AHB_CLOCK_USB20_SDU (1ULL << GLB_AHB_CLOCK_IP_USB20_SDU) +#define GLB_AHB_CLOCK_MIX2 (1ULL << GLB_AHB_CLOCK_IP_MIX2) +#define GLB_AHB_CLOCK_AUDIO (1ULL << GLB_AHB_CLOCK_IP_AUDIO) +#define GLB_AHB_CLOCK_SDH (1ULL << GLB_AHB_CLOCK_IP_SDH) +#define GLB_AHB_CLOCK_ZB_2_NORMAL (1ULL << GLB_AHB_CLOCK_IP_ZB2_NORMAL) +#define GLB_AHB_CLOCK_ZB_2_LP (1ULL << GLB_AHB_CLOCK_IP_ZB2_LP) +#define GLB_AHB_CLOCK_I2C1 (1ULL << GLB_AHB_CLOCK_IP_I2C1) +#define GLB_AHB_CLOCK_WIFI_PHY (1ULL << GLB_AHB_CLOCK_IP_WIFI_PHY) +#define GLB_AHB_CLOCK_WIFI_MAC_PHY (1ULL << GLB_AHB_CLOCK_IP_WIFI_MAC_PHY) +#define GLB_AHB_CLOCK_WIFI_PLATFORM (1ULL << GLB_AHB_CLOCK_IP_WIFI_PLATFORM) +#define GLB_AHB_CLOCK_LZ4 (1ULL << GLB_AHB_CLOCK_IP_LZ4) +#define GLB_AHB_CLOCK_AUPDM (1ULL << GLB_AHB_CLOCK_IP_AUPDM) +#define GLB_AHB_CLOCK_GAUGE (1ULL << GLB_AHB_CLOCK_IP_GAUGE) +#define GLB_AHB_CLOCK_DBI (1ULL << GLB_AHB_CLOCK_IP_DBI) +#define GLB_AHB_CLOCK_PEC (1ULL << GLB_AHB_CLOCK_IP_PEC) +#define GLB_AHB_CLOCK_ISO11898 (1ULL << GLB_AHB_CLOCK_IP_ISO11898) +#define GLB_AHB_CLOCK_AUSOLO_TOP (1ULL << GLB_AHB_CLOCK_IP_AUSOLO_TOP) +#define GLB_AHB_CLOCK_DMA_GPIO (1ULL << GLB_AHB_CLOCK_IP_DMA_GPIO) +#define GLB_AHB_CLOCK_MM_MISC (1ULL << GLB_AHB_CLOCK_IP_MM_MISC) + +/*@} end of group GLB_Public_Macros */ + +/** @defgroup GLB_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void); +void BMX_TO_IRQHandler(void); +#endif +/*----------*/ +GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void); +BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv); +uint8_t GLB_Get_BCLK_Div(void); +uint8_t GLB_Get_HCLK_Div(void); +BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq); +BL_Err_Type System_Core_Clock_Update_From_RC32M(void); +/*----------*/ +BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable); +BL_Err_Type GLB_Set_AUDIO_CLK(uint8_t clkDivEn, uint8_t autoDivEn, GLB_AUDIO_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_KYS_CLK(GLB_KYS_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk); +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Sel_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_0_Type clkSel); +BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_1_Type clkSel); +BL_Err_Type GLB_Set_Chip_Out_CLK_Enable(uint8_t enable, uint8_t pin); +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_SRC_Type clkSel); +/*----------*/ +BL_Err_Type GLB_SW_System_Reset(void); +BL_Err_Type GLB_SW_CPU_Reset(void); +BL_Err_Type GLB_SW_POR_Reset(void); +BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst); +BL_Err_Type GLB_MAC154_ZIGBEE_Reset(void); +BL_Err_Type GLB_BLE_Reset(void); +BL_Err_Type GLB_Disrst_Set(uint8_t enable, GLB_DISRST_Type disrst); +BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips); +BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips); +/*----------*/ +BL_Err_Type GLB_Set_RTC_Mode(RTC_MODE_Type rtcMode); +/*----------*/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg); +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void); +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void); +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void); +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType); +uint32_t GLB_BMX_Get_Err_Addr(void); +BL_Err_Type GLB_BMX_BusErrClr_Set(uint8_t enable); +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value); +uint32_t GLB_Get_SRAM_PARM(void); +BL_Err_Type GLB_Set_OCRAM_PARM(uint32_t value); +uint32_t GLB_Get_OCRAM_PARM(void); +/*----------*/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType); +/*----------*/ +BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable); +BL_Err_Type GLB_GPIO_O_Latch_Mode_Set(uint8_t enable); +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel); +BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable); +BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable); +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState); +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod); +BL_Err_Type GLB_Set_Flash_Scenario(uint8_t enable); +BL_Err_Type GLB_Set_Embedded_FLash_IO_PARM(uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs); +/*----------*/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_SRC_Type clkSel, uint8_t div); +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, GLB_DIG_CLK_SRC_Type clkSel, uint16_t div); +BL_Err_Type GLB_SW_BLE_WAKEUP_REQ_Set(uint8_t enable); +/*----------*/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun); +/*----------*/ +BL_Err_Type GLB_Power_Off_DLL(void); +BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType); +BL_Err_Type GLB_Enable_DLL_All_Clks(void); +BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk); +BL_Err_Type GLB_Disable_DLL_All_Clks(void); +BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk); +/*----------*/ +BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue); +uint32_t GLB_Get_Flash_Id_Value(void); +/*----------*/ +BL_Err_Type GLB_Trim_RC32M(void); +BL_Err_Type GLB_Set_Xtal_Cnt32k_Process(void); +BL_Err_Type GLB_Clear_Xtal_Cnt32k_Done(void); +BL_Err_Type GLB_RC32K_Deg_Start(void); +BL_Err_Type GLB_RC32K_Deg_End(void); +BL_Err_Type GLB_RC32K_Deg_Enable(uint8_t enable); +BL_Err_Type GLB_Xtal_Deg_Cnt_Limit_Set(uint8_t cnt); +/*----------*/ +BL_Err_Type GLB_IR_LED_Driver_Enable(void); +BL_Err_Type GLB_IR_LED_Driver_Disable(void); +BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_IR_LED_Type led); +BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_IR_LED_Type led); +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias); +/*----------*/; + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_GLB_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_glb_gpio.h b/drivers/soc/bl702l/std/include/bl702l_glb_gpio.h new file mode 100644 index 000000000..771636902 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_glb_gpio.h @@ -0,0 +1,138 @@ +/** + ****************************************************************************** + * @file bl702l_glb_gpio.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_GLB_GPIO_H__ +#define __BL702L_GLB_GPIO_H__ + +#include "glb_reg.h" +#include "pds_reg.h" +#include "bl702l_gpio.h" +#include "bl702l_l1c.h" +#include "bl702l_hbn.h" +#include "bl702l_aon.h" +#include "bl702l_pds.h" +#include "bl702l_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB_GPIO + * @{ + */ + +#define GLB_GPIO_OFFSET 0x100 +#define GLB_GPIO_INPUT_OFFSET 0x180 +#define GLB_GPIO_OUTPUT_OFFSET 0x188 +#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190 + +/** + * @brief GLB GPIO interrupt trigger mode type definition + */ +typedef enum { + GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE = 0, /*!< GPIO interrupt sync mode, GPIO falling edge trigger interrupt */ + GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE = 1, /*!< GPIO interrupt sync mode, GPIO rising edge trigger interrupt */ + GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL = 2, /*!< GPIO interrupt sync mode, GPIO low level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL = 3, /*!< GPIO interrupt sync mode, GPIO high level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO falling and rising edge trigger interrupt */ + GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE = 8, /*!< GPIO interrupt async mode, GPIO falling edge trigger interrupt */ + GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE = 9, /*!< GPIO interrupt async mode, GPIO rising edge trigger interrupt */ + GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL = 10, /*!< GPIO interrupt async mode, GPIO low level trigger interrupt (32k 3T) */ + GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL = 11, /*!< GPIO interrupt async mode, GPIO high level trigger interrupt (32k 3T) */ +} GLB_GPIO_INT_TRIG_Type; + +/** + * @brief GLB GPIO output mode type definition + */ +typedef enum { + GLB_GPIO_OUTPUT_MODE_WRITE = 0, /*!< GPIO output mode write */ + GLB_GPIO_OUTPUT_MODE_SETCLR = 1, /*!< GPIO output mode set/clr */ +} GLB_GPIO_OUTPUT_MODE_Type; + +/** + * @brief GPIO interrupt configuration structure type definition + */ +typedef struct +{ + GLB_GPIO_Type gpioPin; /*!< GPIO pin num */ + GLB_GPIO_INT_TRIG_Type trig; /*!< GPIO interrupt trig mode */ + BL_Mask_Type intMask; /*!< GPIO interrupt mask config */ +} GLB_GPIO_INT_Cfg_Type; + +/** @defgroup GLB_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +void GPIO_INT0_IRQHandler(void); +#endif +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg); +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt); +BL_Err_Type GLB_GPIO_OUTPUT_Mode_Set(GLB_GPIO_Type gpioPin, GLB_GPIO_OUTPUT_MODE_Type mode); +BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin); +uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val); +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask); +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin); +BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg); +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void); +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun); + +/*----------*/; + +/*@} end of group GLB_GPIO_Public_Functions */ + +/*@} end of group GLB_GPIO */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_GLB_GPIO_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_gpio.h b/drivers/soc/bl702l/std/include/bl702l_gpio.h new file mode 100644 index 000000000..fdab69fac --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_gpio.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file bl702l_gpio.h + * @version V1.0 + * @date 2022-05-10 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#ifndef __BL702L_GPIO_H__ +#define __BL702L_GPIO_H__ + +typedef enum { + GLB_GPIO_PIN_0 = 0, + GLB_GPIO_PIN_1, + GLB_GPIO_PIN_2, + GLB_GPIO_PIN_3, + GLB_GPIO_PIN_4, + GLB_GPIO_PIN_5, + GLB_GPIO_PIN_6, + GLB_GPIO_PIN_7, + GLB_GPIO_PIN_8, + GLB_GPIO_PIN_9, + GLB_GPIO_PIN_10, + GLB_GPIO_PIN_11, + GLB_GPIO_PIN_12, + GLB_GPIO_PIN_13, + GLB_GPIO_PIN_14, + GLB_GPIO_PIN_15, + GLB_GPIO_PIN_16, + GLB_GPIO_PIN_17, + GLB_GPIO_PIN_18, + GLB_GPIO_PIN_19, + GLB_GPIO_PIN_20, + GLB_GPIO_PIN_21, + GLB_GPIO_PIN_22, + GLB_GPIO_PIN_23, + GLB_GPIO_PIN_24, + GLB_GPIO_PIN_25, + GLB_GPIO_PIN_26, + GLB_GPIO_PIN_27, + GLB_GPIO_PIN_28, + GLB_GPIO_PIN_29, + GLB_GPIO_PIN_30, + GLB_GPIO_PIN_31, + GLB_GPIO_PIN_MAX, +} GLB_GPIO_Type; + +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */ +#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */ +#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */ +#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */ + +typedef enum { + GPIO_FUN_CLK_OUT = 0, + GPIO_FUN_BT_COEXIST = 1, + GPIO_FUN_FLASH_PSRAM = 2, + GPIO_FUN_QSPI = 2, + GPIO_FUN_SPI = 4, + GPIO_FUN_PDM = 5, + GPIO_FUN_I2C = 6, + GPIO_FUN_UART = 7, + GPIO_FUN_PWM = 8, + GPIO_FUN_ANALOG = 10, + GPIO_FUN_GPIO = 11, + GPIO_FUN_SCAN = 13, + GPIO_FUN_E21_JTAG = 14, + GPIO_FUN_DEBUG = 15, + GPIO_FUN_KEY_SCAN_IN = 21, + GPIO_FUN_KEY_SCAN_ROW = 21, + GPIO_FUN_KEY_SCAN_DRIVE = 22, + GPIO_FUN_KEY_SCAN_COL = 22, + + GPIO_FUN_DAC = 0xD1, + GPIO_FUN_ADC = 0xD2, + GPIO_FUN_GPIO_OUTPUT_UP = 0xE0, + GPIO_FUN_GPIO_OUTPUT_DOWN = 0xE1, + GPIO_FUN_GPIO_OUTPUT_NONE = 0xE2, + GPIO_FUN_GPIO_INPUT_UP = 0xE3, + GPIO_FUN_GPIO_INPUT_DOWN = 0xE4, + GPIO_FUN_GPIO_INPUT_NONE = 0xE5, + GPIO_FUN_GPIO_EXTI_SYNC_FALLING_EDGE = 0xE6, + GPIO_FUN_GPIO_EXTI_SYNC_RISING_EDGE = 0xE7, + GPIO_FUN_GPIO_EXTI_SYNC_LOW_LEVEL = 0xE8, + GPIO_FUN_GPIO_EXTI_SYNC_HIGH_LEVEL = 0xE9, + GPIO_FUN_GPIO_EXIT_SYNC_RISING_FALLING_EDGE = 0xEA, + GPIO_FUN_GPIO_EXTI_ASYNC_FALLING_EDGE = 0xEB, + GPIO_FUN_GPIO_EXTI_AYNC_RISING_EDGE = 0xEC, + GPIO_FUN_GPIO_EXTI_AYNC_LOW_LEVEL = 0xED, + GPIO_FUN_GPIO_EXTI_AYNC_HIGH_LEVEL = 0xEE, + GPIO_FUN_UART0_RTS = 0xF0, + GPIO_FUN_UART0_CTS = 0xF1, + GPIO_FUN_UART0_TX = 0xF2, + GPIO_FUN_UART0_RX = 0xF3, + GPIO_FUN_WAKEUP = 0xFE, + + GPIO_FUN_UNUSED = 0xFF, +} GLB_GPIO_FUNC_Type; + +typedef struct +{ + uint8_t gpioPin; + uint8_t gpioFun; + uint8_t gpioMode; + uint8_t pullType; + uint8_t drive; + uint8_t smtCtrl; +} GLB_GPIO_Cfg_Type; +#endif /*__BL702L_GPIO_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_hbn.h b/drivers/soc/bl702l/std/include/bl702l_hbn.h new file mode 100644 index 000000000..2d1be3fb1 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_hbn.h @@ -0,0 +1,730 @@ +/** + ****************************************************************************** + * @file bl702l_hbn.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_HBN_H__ +#define __BL702L_HBN_H__ + +#include "hbn_reg.h" +#include "bl702l_aon.h" +#include "bl702l_common.h" +#include "bflb_sflash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Public_Types + * @{ + */ + +/** + * @brief HBN PIR interrupt configuration type definition + */ +typedef struct +{ + BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */ + BL_Fun_Type highIntEn; /*!< High will trigger interrupt */ +} HBN_PIR_INT_CFG_Type; + +/** + * @brief HBN PIR low pass filter type definition + */ +typedef enum { + HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */ + HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */ +} HBN_PIR_LPF_Type; + +/** + * @brief HBN PIR high pass filter type definition + */ +typedef enum { + HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */ + HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */ + HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */ +} HBN_PIR_HPF_Type; + +/** + * @brief HBN BOR threshold type definition + */ +typedef enum { + HBN_BOR_THRES_1P80V, /*!< BOR threshold 1.80V */ + HBN_BOR_THRES_1P85V, /*!< BOR threshold 1.85V */ + HBN_BOR_THRES_1P90V, /*!< BOR threshold 1.90V */ + HBN_BOR_THRES_1P95V, /*!< BOR threshold 1.95V */ + HBN_BOR_THRES_2P00V, /*!< BOR threshold 2.00V */ + HBN_BOR_THRES_2P05V, /*!< BOR threshold 2.05V */ + HBN_BOR_THRES_2P10V, /*!< BOR threshold 2.10V */ + HBN_BOR_THRES_2P15V, /*!< BOR threshold 2.15V */ +} HBN_BOR_THRES_Type; + +/** + * @brief HBN BOR mode type definition + */ +typedef enum { + HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ + HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ +} HBN_BOR_MODE_Type; + +/** + * @brief HBN 32K clock type definition + */ +typedef enum { + HBN_32K_RC = 0, /*!< HBN use rc 32k */ + HBN_32K_XTAL, /*!< HBN use xtal 32k */ + HBN_32K_DIG = 3, /*!< HBN use dig 32k */ +} HBN_32K_CLK_Type; + +/** + * @brief HBN xclk clock type definition + */ +typedef enum { + HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */ + HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */ +} HBN_XCLK_CLK_Type; + +/** + * @brief HBN root clock type definition + */ +typedef enum { + HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */ + HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */ + HBN_ROOT_CLK_DLL, /*!< use DLL as root clock */ +} HBN_ROOT_CLK_Type; + +/** + * @brief HBN UART clock type definition + */ +typedef enum { + HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */ + HBN_UART_CLK_64M, /*!< Select 64M as UART clock */ + HBN_UART_CLK_XCLK, /*!< Select XCLK as UART clock */ +} HBN_UART_CLK_Type; + +/** + * @brief HBN RTC interrupt delay type definition + */ +typedef enum { + HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */ + HBN_RTC_INT_DELAY_0T = 1, /*!< HBN RTC interrupt delay 0T */ +} HBN_RTC_INT_Delay_Type; + +/** + * @brief HBN aon pad type definition + */ +typedef enum { + HBN_AON_PAD_GPIO9 = 0, /*!< HBN aon pad type: GPIO16 */ + HBN_AON_PAD_GPIO10 = 1, /*!< HBN aon pad type: GPIO17 */ + HBN_AON_PAD_GPIO11 = 2, /*!< HBN aon pad type: GPIO18 */ + HBN_AON_PAD_GPIO12 = 3, /*!< HBN aon pad type: GPIO19 */ + HBN_AON_PAD_GPIO13 = 4, /*!< HBN aon pad type: GPIO19 */ + HBN_AON_PAD_GPIO30 = 5, /*!< HBN aon pad type: GPIO19 */ + HBN_AON_PAD_GPIO31 = 6, /*!< HBN aon pad type: GPIO19 */ +} HBN_AON_PAD_Type; + +/** + * @brief HBN interrupt type definition + */ +typedef enum { + HBN_INT_GPIO9 = 0, /*!< HBN interrupt type: GPIO9 */ + HBN_INT_GPIO10 = 1, /*!< HBN interrupt type: GPIO10 */ + HBN_INT_GPIO11 = 2, /*!< HBN interrupt type: GPIO11 */ + HBN_INT_GPIO12 = 3, /*!< HBN interrupt type: GPIO12 */ + HBN_INT_GPIO13 = 4, /*!< HBN interrupt type: GPIO13 */ + HBN_INT_GPIO30 = 5, /*!< HBN interrupt type: GPIO30 */ + HBN_INT_GPIO31 = 6, /*!< HBN interrupt type: GPIO31 */ + HBN_INT_GPIO8 = 7, /*!< HBN interrupt type: GPIO8 */ + HBN_INT_GPIO14 = 8, /*!< HBN interrupt type: GPIO14 */ + HBN_INT_GPIO22 = 9, /*!< HBN interrupt type: GPIO22 */ + HBN_INT_RTC = 16, /*!< HBN interrupt type: RTC */ + HBN_INT_BOD = 18, /*!< HBN interrupt type: BOR */ + HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */ + HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */ +} HBN_INT_Type; + +/** + * @brief HBN acomp interrupt type definition + */ +typedef enum { + HBN_ACOMP_INT_EDGE_POSEDGE = 1, /*!< HBN acomp interrupt edge posedge */ + HBN_ACOMP_INT_EDGE_NEGEDGE = 2, /*!< HBN acomp interrupt edge negedge */ + HBN_ACOMP_INT_EDGE_POSEDGE_NEGEDGE = 3, /*!< HBN acomp interrupt edge posedge and negedge */ +} HBN_ACOMP_INT_EDGE_Type; + +/** + * @brief HBN reset event type definition + */ +typedef enum { + HBN_RST_EVENT_POR_OUT, /*!< por_out event */ + HBN_RST_EVENT_EXT_RST_N, /*!< ext_rst_n event */ + HBN_RST_EVENT_SW_RST, /*!< sw_rst event */ + HBN_RST_EVENT_PWR_RST_N, /*!< pwr_rst_n event */ + HBN_RST_EVENT_BOR_OUT, /*!< bor_out_ event */ +} HBN_RST_EVENT_Type; + +/** + * @brief HBN AON PAD configuration type definition + */ +typedef struct +{ + uint8_t ctrlEn; /*!< AON PAD Control by AON HW */ + uint8_t ie; /*!< Always on PAD IE/SMT (if corresponding AON GPIO controlled by AON HW) */ + uint8_t oe; /*!< Always on PAD OE (if corresponding AON GPIO controlled by AON HW) */ + uint8_t pullUp; /*!< Always on PAD PU (if corresponding AON GPIO controlled by AON HW) */ + uint8_t pullDown; /*!< Always on PAD PD (if corresponding AON GPIO controlled by AON HW) */ +} HBN_AON_PAD_CFG_Type; + +/** + * @brief HBN GPIO interrupt trigger type definition + */ +typedef enum { + HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */ + HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */ + HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */ +} HBN_GPIO_INT_Trigger_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT0_INT_GPIO9 = 0, /*!< HBN out 0 interrupt type: GPIO9 */ + HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */ + HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */ + HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */ + HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */ + HBN_OUT0_INT_GPIO30 = 5, /*!< HBN out 0 interrupt type: GPIO30 */ + HBN_OUT0_INT_GPIO31 = 6, /*!< HBN out 0 interrupt type: GPIO31 */ + HBN_OUT0_INT_GPIO8 = 7, /*!< HBN out 0 interrupt type: GPIO8 */ + HBN_OUT0_INT_GPIO14 = 8, /*!< HBN out 0 interrupt type: GPIO14 */ + HBN_OUT0_INT_GPIO22 = 9, /*!< HBN out 0 interrupt type: GPIO22 */ + HBN_OUT0_INT_RTC = 16, /*!< HBN out 0 interrupt type: RTC */ + HBN_OUT0_INT_MAX, /*!< HBN out 0 max num */ +} HBN_OUT0_INT_Type; + +/** + * @brief HBN OUT0 interrupt type definition + */ +typedef enum { + HBN_OUT1_INT_BOD, /*!< HBN out 1 interrupt type: BOD */ + HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */ + HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */ + HBN_OUT1_INT_MAX, /*!< HBN out 1 max num */ +} HBN_OUT1_INT_Type; + +/** + * @brief HBN LDO level type definition + */ +typedef enum { + HBN_LDO11_LEVEL_0P60V = 0, /*!< VDD11_AON voltage 0.60V */ + HBN_LDO11_LEVEL_0P65V = 1, /*!< VDD11_AON voltage 0.65V */ + HBN_LDO11_LEVEL_0P70V = 2, /*!< VDD11_AON voltage 0.70V */ + HBN_LDO11_LEVEL_0P75V = 3, /*!< VDD11_AON voltage 0.75V */ + HBN_LDO11_LEVEL_0P80V = 4, /*!< VDD11_AON voltage 0.80V */ + HBN_LDO11_LEVEL_0P85V = 5, /*!< VDD11_AON voltage 0.85V */ + HBN_LDO11_LEVEL_0P90V = 6, /*!< VDD11_AON voltage 0.90V */ + HBN_LDO11_LEVEL_0P95V = 7, /*!< VDD11_AON voltage 0.95V */ + HBN_LDO11_LEVEL_1P00V = 8, /*!< VDD11_AON voltage 1.00V */ + HBN_LDO11_LEVEL_1P05V = 9, /*!< VDD11_AON voltage 1.05V */ + HBN_LDO11_LEVEL_1P10V = 10, /*!< VDD11_AON voltage 1.10V */ +} HBN_LDO11_LEVEL_Type; + +/** + * @brief HBN LDO level type definition + */ +typedef enum { + HBN_LDO_LEVEL_0P60V = 0, /*!< HBN LDO voltage 0.60V */ + HBN_LDO_LEVEL_0P65V = 1, /*!< HBN LDO voltage 0.65V */ + HBN_LDO_LEVEL_0P70V = 2, /*!< HBN LDO voltage 0.70V */ + HBN_LDO_LEVEL_0P75V = 3, /*!< HBN LDO voltage 0.75V */ + HBN_LDO_LEVEL_0P80V = 4, /*!< HBN LDO voltage 0.80V */ + HBN_LDO_LEVEL_0P85V = 5, /*!< HBN LDO voltage 0.85V */ + HBN_LDO_LEVEL_0P90V = 6, /*!< HBN LDO voltage 0.90V */ + HBN_LDO_LEVEL_0P95V = 7, /*!< HBN LDO voltage 0.95V */ + HBN_LDO_LEVEL_1P00V = 8, /*!< HBN LDO voltage 1.00V */ + HBN_LDO_LEVEL_1P05V = 9, /*!< HBN LDO voltage 1.05V */ + HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */ + HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */ + HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */ + HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */ + HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */ + HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */ +} HBN_LDO_LEVEL_Type; + +/** + * @brief HBN LDO11RT drive strength type definition + */ +typedef enum { + HBN_LDO11RT_DRIVE_STRENGTH_5_50UA = 0, /*!< HBN LDO11RT drive strength 0: 5uA to 50uA */ + HBN_LDO11RT_DRIVE_STRENGTH_10_100UA = 1, /*!< HBN LDO11RT drive strength 1: 10uA to 100uA */ + HBN_LDO11RT_DRIVE_STRENGTH_15_150UA = 2, /*!< HBN LDO11RT drive strength 2: 15uA to 150uA */ + HBN_LDO11RT_DRIVE_STRENGTH_25_250UA = 3, /*!< HBN LDO11RT drive strength 3: 25uA to 250uA */ +} HBN_LDO11RT_DRIVE_STRENGTH_Type; + +/** + * @brief HBN level type definition + */ +typedef enum { + HBN_LEVEL_0, /*!< HBN pd_core */ + HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */ + HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */ +} HBN_LEVEL_Type; + +/** + * @brief HBN BOR configuration type definition + */ +typedef struct +{ + uint8_t enableBor; /*!< Enable BOR or not */ + uint8_t enableBorInt; /*!< Enable BOR interrupt or not */ + uint8_t borThreshold; /*!< BOR threshold */ + uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */ +} HBN_BOR_CFG_Type; + +/** + * @brief HBN APP configuration type definition + */ +typedef struct +{ + uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ + uint32_t sleepTime; /*!< HBN sleep time */ + uint8_t hw_pu_pd_en; /*!< Pull up or pull down enable in the hbn mode */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ + HBN_LEVEL_Type hbnLevel; /*!< HBN level */ + HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ +} HBN_APP_CFG_Type; + +/*@} end of group HBN_Public_Types */ + +/** @defgroup HBN_Public_Constants + * @{ + */ + +/** @defgroup HBN_PIR_LPF_TYPE + * @{ + */ +#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \ + ((type) == HBN_PIR_LPF_DIV2)) + +/** @defgroup HBN_PIR_HPF_TYPE + * @{ + */ +#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \ + ((type) == HBN_PIR_HPF_METHOD1) || \ + ((type) == HBN_PIR_HPF_METHOD2)) + +/** @defgroup HBN_BOR_THRES_TYPE + * @{ + */ +#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_1P80V) ||\ + ((type) == HBN_BOR_THRES_1P85V) ||\ + ((type) == HBN_BOR_THRES_1P90V) ||\ + ((type) == HBN_BOR_THRES_1P95V) ||\ + ((type) == HBN_BOR_THRES_2P00V) ||\ + ((type) == HBN_BOR_THRES_2P05V) ||\ + ((type) == HBN_BOR_THRES_2P10V) ||\ + ((type) == HBN_BOR_THRES_2P15V)) + +/** @defgroup HBN_BOR_MODE_TYPE + * @{ + */ +#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \ + ((type) == HBN_BOR_MODE_POR_RELEVANT)) + +/** @defgroup HBN_32K_CLK_TYPE + * @{ + */ +#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \ + ((type) == HBN_32K_XTAL) || \ + ((type) == HBN_32K_DIG)) + +/** @defgroup HBN_XCLK_CLK_TYPE + * @{ + */ +#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \ + ((type) == HBN_XCLK_CLK_XTAL)) + +/** @defgroup HBN_ROOT_CLK_TYPE + * @{ + */ +#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \ + ((type) == HBN_ROOT_CLK_XTAL) || \ + ((type) == HBN_ROOT_CLK_DLL)) + +/** @defgroup HBN_UART_CLK_TYPE + * @{ + */ +#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \ + ((type) == HBN_UART_CLK_64M) || \ + ((type) == HBN_UART_CLK_XCLK)) + +/** @defgroup HBN_RTC_INT_DELAY_TYPE + * @{ + */ +#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \ + ((type) == HBN_RTC_INT_DELAY_0T)) + +/** @defgroup HBN_INT_TYPE + * @{ + */ +#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) || \ + ((type) == HBN_INT_GPIO10) || \ + ((type) == HBN_INT_GPIO11) || \ + ((type) == HBN_INT_GPIO12) || \ + ((type) == HBN_INT_GPIO13) || \ + ((type) == HBN_INT_RTC) || \ + ((type) == HBN_INT_PIR) || \ + ((type) == HBN_INT_BOR) || \ + ((type) == HBN_INT_ACOMP0) || \ + ((type) == HBN_INT_ACOMP1)) + +/** @defgroup HBN_ACOMP_INT_EDGE_TYPE + * @{ + */ +#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \ + ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE) || \ + ((type) == HBN_ACOMP_INT_EDGE_POSEDGE_NEGEDGE)) +/** @defgroup HBN_RST_EVENT_TYPE + * @{ + */ +#define IS_HBN_RST_EVENT_TYPE(type) (((type) == HBN_RST_EVENT_POR_OUT) || \ + ((type) == HBN_RST_EVENT_EXT_RST_N) || \ + ((type) == HBN_RST_EVENT_SW_RST) || \ + ((type) == HBN_RST_EVENT_PWR_RST_N) || \ + ((type) == HBN_RST_EVENT_BOR_OUT)) + +/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE + * @{ + */ +#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \ + ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL)) + + +/** @defgroup HBN_AON_PAD_TYPE + * @{ + */ +#define IS_HBN_AON_PAD_TYPE(type) (((type) == HBN_AON_PAD_GPIO9) || \ + ((type) == HBN_AON_PAD_GPIO10) || \ + ((type) == HBN_AON_PAD_GPIO11) || \ + ((type) == HBN_AON_PAD_GPIO12) || \ + ((type) == HBN_AON_PAD_GPIO13) || \ + ((type) == HBN_AON_PAD_GPIO30) || \ + ((type) == HBN_AON_PAD_GPIO31)) + +/** @defgroup HBN_OUT0_INT_TYPE + * @{ + */ +#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) || \ + ((type) == HBN_OUT0_INT_GPIO10) || \ + ((type) == HBN_OUT0_INT_GPIO11) || \ + ((type) == HBN_OUT0_INT_GPIO12) || \ + ((type) == HBN_OUT0_INT_GPIO13) || \ + ((type) == HBN_OUT0_INT_RTC) || \ + ((type) == HBN_OUT0_MAX)) + +/** @defgroup HBN_OUT1_INT_TYPE + * @{ + */ +#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \ + ((type) == HBN_OUT1_INT_BOR) || \ + ((type) == HBN_OUT1_INT_ACOMP0) || \ + ((type) == HBN_OUT1_INT_ACOMP1) || \ + ((type) == HBN_OUT1_MAX)) + +/** @defgroup HBN_LDO11_LEVEL_Type + * @{ + */ +#define IS_HBN_LDO11_LEVEL_TYPE(type) (((type) == HBN_LDO11_LEVEL_0P60V) || \ + ((type) == HBN_LDO11_LEVEL_0P65V) || \ + ((type) == HBN_LDO11_LEVEL_0P70V) || \ + ((type) == HBN_LDO11_LEVEL_0P75V) || \ + ((type) == HBN_LDO11_LEVEL_0P80V) || \ + ((type) == HBN_LDO11_LEVEL_0P85V) || \ + ((type) == HBN_LDO11_LEVEL_0P90V) || \ + ((type) == HBN_LDO11_LEVEL_0P95V) || \ + ((type) == HBN_LDO11_LEVEL_1P00V) || \ + ((type) == HBN_LDO11_LEVEL_1P05V) || \ + ((type) == HBN_LDO11_LEVEL_1P10V)) + +/** @defgroup HBN_LDO_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \ + ((type) == HBN_LDO_LEVEL_0P65V) || \ + ((type) == HBN_LDO_LEVEL_0P70V) || \ + ((type) == HBN_LDO_LEVEL_0P75V) || \ + ((type) == HBN_LDO_LEVEL_0P80V) || \ + ((type) == HBN_LDO_LEVEL_0P85V) || \ + ((type) == HBN_LDO_LEVEL_0P90V) || \ + ((type) == HBN_LDO_LEVEL_0P95V) || \ + ((type) == HBN_LDO_LEVEL_1P00V) || \ + ((type) == HBN_LDO_LEVEL_1P05V) || \ + ((type) == HBN_LDO_LEVEL_1P10V) || \ + ((type) == HBN_LDO_LEVEL_1P15V) || \ + ((type) == HBN_LDO_LEVEL_1P20V) || \ + ((type) == HBN_LDO_LEVEL_1P25V) || \ + ((type) == HBN_LDO_LEVEL_1P30V) || \ + ((type) == HBN_LDO_LEVEL_1P35V)) + +/** @defgroup HBN_LDO11RT_DRIVE_STRENGTH_TYPE + * @{ + */ +#define IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(type) (((type) == HBN_LDO11RT_DRIVE_STRENGTH_5_50UA) || \ + ((type) == HBN_LDO11RT_DRIVE_STRENGTH_10_100UA) || \ + ((type) == HBN_LDO11RT_DRIVE_STRENGTH_15_150UA) || \ + ((type) == HBN_LDO11RT_DRIVE_STRENGTH_25_250UA)) + +/** @defgroup HBN_LEVEL_TYPE + * @{ + */ +#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \ + ((type) == HBN_LEVEL_1) || \ + ((type) == HBN_LEVEL_2)) + +/*@} end of group HBN_Public_Constants */ + +/** @defgroup HBN_Public_Macros + * @{ + */ +#define HBN_RAM_SIZE (4 * 1024) +#define HBN_RTC_COMP_BIT0_39 0x01 +#define HBN_RTC_COMP_BIT0_23 0x02 +#define HBN_RTC_COMP_BIT13_39 0x04 +#define HBN_STATUS_ENTER_FLAG 0x4e424845 +#define HBN_STATUS_WAKEUP_FLAG 0x4e424857 +#define HBN_RELEASE_CORE_FLAG (0x4) +#define HBN_WAKEUP_GPIO_NONE 0x00 +#define HBN_WAKEUP_GPIO_9 0x01 +#define HBN_WAKEUP_GPIO_10 0x02 +#define HBN_WAKEUP_GPIO_11 0x04 +#define HBN_WAKEUP_GPIO_12 0x08 +#define HBN_WAKEUP_GPIO_13 0x10 +#define HBN_WAKEUP_GPIO_30 0x20 +#define HBN_WAKEUP_GPIO_31 0x40 +#define HBN_WAKEUP_GPIO_8 0x80 +#define HBN_WAKEUP_GPIO_14 0x100 +#define HBN_WAKEUP_GPIO_22 0x200 +#define HBN_WAKEUP_GPIO_ALL 0x3FF + +/* 0x108 : HBN_RSV2 */ +#define HBN_LDO18IO_POWER_ON_DLY HBN_LDO18IO_POWER_ON_DLY +#define HBN_LDO18IO_POWER_ON_DLY_POS (0U) +#define HBN_LDO18IO_POWER_ON_DLY_LEN (11U) +#define HBN_LDO18IO_POWER_ON_DLY_MSK (((1U << HBN_LDO18IO_POWER_ON_DLY_LEN) - 1) << HBN_LDO18IO_POWER_ON_DLY_POS) +#define HBN_LDO18IO_POWER_ON_DLY_UMSK (~(((1U << HBN_LDO18IO_POWER_ON_DLY_LEN) - 1) << HBN_LDO18IO_POWER_ON_DLY_POS)) +#define HBN_LDO18IO_POWER_OFF_DLY HBN_LDO18IO_POWER_OFF_DLY +#define HBN_LDO18IO_POWER_OFF_DLY_POS (11U) +#define HBN_LDO18IO_POWER_OFF_DLY_LEN (5U) +#define HBN_LDO18IO_POWER_OFF_DLY_MSK (((1U << HBN_LDO18IO_POWER_OFF_DLY_LEN) - 1) << HBN_LDO18IO_POWER_OFF_DLY_POS) +#define HBN_LDO18IO_POWER_OFF_DLY_UMSK (~(((1U << HBN_LDO18IO_POWER_OFF_DLY_LEN) - 1) << HBN_LDO18IO_POWER_OFF_DLY_POS)) +#define HBN_LDO18IO_POWER_DLY_STS HBN_LDO18IO_POWER_DLY_STS +#define HBN_LDO18IO_POWER_DLY_STS_POS (16U) +#define HBN_LDO18IO_POWER_DLY_STS_LEN (8U) +#define HBN_LDO18IO_POWER_DLY_STS_MSK (((1U << HBN_LDO18IO_POWER_DLY_STS_LEN) - 1) << HBN_LDO18IO_POWER_DLY_STS_POS) +#define HBN_LDO18IO_POWER_DLY_STS_UMSK (~(((1U << HBN_LDO18IO_POWER_DLY_STS_LEN) - 1) << HBN_LDO18IO_POWER_DLY_STS_POS)) +#define HBN_CORE_UNHALT HBN_CORE_UNHALT +#define HBN_CORE_UNHALT_POS (25U) +#define HBN_CORE_UNHALT_LEN (1U) +#define HBN_CORE_UNHALT_MSK (((1U << HBN_CORE_UNHALT_LEN) - 1) << HBN_CORE_UNHALT_POS) +#define HBN_CORE_UNHALT_UMSK (~(((1U << HBN_CORE_UNHALT_LEN) - 1) << HBN_CORE_UNHALT_POS)) +#define HBN_USER_BOOT_SEL HBN_USER_BOOT_SEL +#define HBN_USER_BOOT_SEL_POS (26U) +#define HBN_USER_BOOT_SEL_LEN (2U) +#define HBN_USER_BOOT_SEL_MSK (((1U << HBN_USER_BOOT_SEL_LEN) - 1) << HBN_USER_BOOT_SEL_POS) +#define HBN_USER_BOOT_SEL_UMSK (~(((1U << HBN_USER_BOOT_SEL_LEN) - 1) << HBN_USER_BOOT_SEL_POS)) +#define HBN_RELEASE_CORE HBN_RELEASE_CORE +#define HBN_RELEASE_CORE_POS (28U) +#define HBN_RELEASE_CORE_LEN (4U) +#define HBN_RELEASE_CORE_MSK (((1U << HBN_RELEASE_CORE_LEN) - 1) << HBN_RELEASE_CORE_POS) +#define HBN_RELEASE_CORE_UMSK (~(((1U << HBN_RELEASE_CORE_LEN) - 1) << HBN_RELEASE_CORE_POS)) + +/* 0x108 : HBN_RSV3 */ +#define HBN_XTAL_TYPE HBN_XTAL_TYPE +#define HBN_XTAL_TYPE_POS (0U) +#define HBN_XTAL_TYPE_LEN (4U) +#define HBN_XTAL_TYPE_MSK (((1U << HBN_XTAL_TYPE_LEN) - 1) << HBN_XTAL_TYPE_POS) +#define HBN_XTAL_TYPE_UMSK (~(((1U << HBN_XTAL_TYPE_LEN) - 1) << HBN_XTAL_TYPE_POS)) +#define HBN_XTAL_STS HBN_XTAL_STS +#define HBN_XTAL_STS_POS (4U) +#define HBN_XTAL_STS_LEN (4U) +#define HBN_XTAL_STS_MSK (((1U << HBN_XTAL_STS_LEN) - 1) << HBN_XTAL_STS_POS) +#define HBN_XTAL_STS_UMSK (~(((1U << HBN_XTAL_STS_LEN) - 1) << HBN_XTAL_STS_POS)) +#define HBN_FLASH_POWER_DLY HBN_FLASH_POWER_DLY +#define HBN_FLASH_POWER_DLY_POS (8U) +#define HBN_FLASH_POWER_DLY_LEN (8U) +#define HBN_FLASH_POWER_DLY_MSK (((1U << HBN_FLASH_POWER_DLY_LEN) - 1) << HBN_FLASH_POWER_DLY_POS) +#define HBN_FLASH_POWER_DLY_UMSK (~(((1U << HBN_FLASH_POWER_DLY_LEN) - 1) << HBN_FLASH_POWER_DLY_POS)) +#define HBN_FLASH_POWER_STS HBN_FLASH_POWER_STS +#define HBN_FLASH_POWER_STS_POS (16U) +#define HBN_FLASH_POWER_STS_LEN (4U) +#define HBN_FLASH_POWER_STS_MSK (((1U << HBN_FLASH_POWER_STS_LEN) - 1) << HBN_FLASH_POWER_STS_POS) +#define HBN_FLASH_POWER_STS_UMSK (~(((1U << HBN_FLASH_POWER_STS_LEN) - 1) << HBN_FLASH_POWER_STS_POS)) +#define PDS_GPIO_KEEP_PIN PDS_GPIO_KEEP_PIN +#define PDS_GPIO_KEEP_PIN_POS (20U) +#define PDS_GPIO_KEEP_PIN_LEN (4U) +#define PDS_GPIO_KEEP_PIN_MSK (((1U << PDS_GPIO_KEEP_PIN_LEN) - 1) << PDS_GPIO_KEEP_PIN_POS) +#define PDS_GPIO_KEEP_PIN_UMSK (~(((1U << PDS_GPIO_KEEP_PIN_LEN) - 1) << PDS_GPIO_KEEP_PIN_POS)) +#define HBN_GPIO_KEEP_PIN HBN_GPIO_KEEP_PIN +#define HBN_GPIO_KEEP_PIN_POS (24U) +#define HBN_GPIO_KEEP_PIN_LEN (4U) +#define HBN_GPIO_KEEP_PIN_MSK (((1U << HBN_GPIO_KEEP_PIN_LEN) - 1) << HBN_GPIO_KEEP_PIN_POS) +#define HBN_GPIO_KEEP_PIN_UMSK (~(((1U << HBN_GPIO_KEEP_PIN_LEN) - 1) << HBN_GPIO_KEEP_PIN_POS)) +#define PDS_GPIO_KEEP_STS PDS_GPIO_KEEP_STS +#define PDS_GPIO_KEEP_STS_POS (28U) +#define PDS_GPIO_KEEP_STS_LEN (2U) +#define PDS_GPIO_KEEP_STS_MSK (((1U << PDS_GPIO_KEEP_STS_LEN) - 1) << PDS_GPIO_KEEP_STS_POS) +#define PDS_GPIO_KEEP_STS_UMSK (~(((1U << PDS_GPIO_KEEP_STS_LEN) - 1) << PDS_GPIO_KEEP_STS_POS)) +#define HBN_GPIO_KEEP_STS HBN_GPIO_KEEP_STS +#define HBN_GPIO_KEEP_STS_POS (30U) +#define HBN_GPIO_KEEP_STS_LEN (2U) +#define HBN_GPIO_KEEP_STS_MSK (((1U << HBN_GPIO_KEEP_STS_LEN) - 1) << HBN_GPIO_KEEP_STS_POS) +#define HBN_GPIO_KEEP_STS_UMSK (~(((1U << HBN_GPIO_KEEP_STS_LEN) - 1) << HBN_GPIO_KEEP_STS_POS)) + +/*@} end of group HBN_Public_Macros */ + +/** @defgroup HBN_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void); +void HBN_OUT1_IRQHandler(void); +#endif +/*----------*/ +void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); +void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); +BL_Err_Type HBN_Reset(void); +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); +BL_Err_Type HBN_Disable(void); +/*----------*/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void); +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode); +/*----------*/ +BL_Err_Type HBN_PDS_Set_Ldo11_Vout(HBN_LDO11_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel); +BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel); +/*----------*/ +BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType); +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel); +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk); +BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk); +/*----------*/ +BL_Err_Type HBN_Set_HRAM_slp(void); +BL_Err_Type HBN_Set_HRAM_Ret(void); +/*----------*/ +uint32_t HBN_Get_Status_Flag(void); +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag); +uint32_t HBN_Get_Wakeup_Addr(void); +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr); +uint8_t HBN_Get_User_Boot_Config(void); +BL_Err_Type HBN_Set_User_Boot_Config(uint8_t ubCfg); +/*----------*/ +BL_Err_Type HBN_Clear_RTC_Counter(void); +BL_Err_Type HBN_Enable_RTC_Counter(void); +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode); +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh); +BL_Err_Type HBN_Clear_RTC_INT(void); +/*----------*/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType); +BL_Err_Type HBN_GPIO_INT_Disable(void); +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType); +uint8_t HBN_Get_Pin_Wakeup_Mode(void); +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType); +BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable); +BL_Err_Type HBN_Comm_Pad_Wakeup_En_Cfg(uint8_t padCfg); +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); +BL_Err_Type HBN_Enable_PDS_Pad_Keep(uint32_t keepSel); +BL_Err_Type HBN_Pin_WakeUp_Mask(uint16_t maskVal); +void HBN_GPIO_Wakeup_Set(uint16_t gpio_wakeup_src, HBN_GPIO_INT_Trigger_Type gpio_trig_type); +BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg); +/*----------*/ +BL_Err_Type HBN_Enable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge); +BL_Err_Type HBN_Disable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge); +/*----------*/ +BL_Err_Type HBN_Enable_BOR_IRQ(void); +BL_Err_Type HBN_Disable_BOR_IRQ(void); +/*----------*/ +BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event); +BL_Err_Type HBN_Clear_Reset_Event(void); +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type HBN_Out0_IRQHandler_Install(void); +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type HBN_Out1_IRQHandler_Install(void); +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun); +#endif +/*----------*/ +BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, + uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask); +/*----------*/ +BL_Err_Type HBN_Power_On_Xtal_32K(void); +BL_Err_Type HBN_Power_Off_Xtal_32K(void); +BL_Err_Type HBN_Power_On_RC32K(void); +BL_Err_Type HBN_Power_Off_RC32K(void); +BL_Err_Type HBN_Trim_RC32K(void); +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg); +/*----------*/ +void HBN_Enable(HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); +/*----------*/ + +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_HBN_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_kys.h b/drivers/soc/bl702l/std/include/bl702l_kys.h new file mode 100644 index 000000000..284c295ea --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_kys.h @@ -0,0 +1,179 @@ +/** + * @file bl702l_kys.h +* @version V1.0 +* @date +* @brief This file is the standard driver header file +****************************************************************************** +* @attention +* +*

© COPYRIGHT(c) 2020 Bouffalo Lab

+* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of Bouffalo Lab nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +*/ + +#ifndef __BL702L_KYS_H__ +#define __BL702L_KYS_H__ + +#include "kys_reg.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup KYS + * @{ + */ + +/** @defgroup KYS_Public_Types + * @{ + */ + +/** + * @brief KYS keycode type definition + */ +// typedef enum { +// KYS_KEYCODE_0, /*!< KYS keycode 0 */ +// KYS_KEYCODE_1, /*!< KYS keycode 1 */ +// KYS_KEYCODE_2, /*!< KYS keycode 2 */ +// KYS_KEYCODE_3, /*!< KYS keycode 3 */ +// KYS_KEYCODE_4, /*!< KYS keycode 4 */ +// KYS_KEYCODE_5, /*!< KYS keycode 5 */ +// } KYS_Keycode_Type; + +// /** +// * @brief KYS Interrupt type definition +// */ +// typedef enum { +// KYS_KEYCODE_INT, /*!< keycode mode interrupt */ +// KYS_KEYFIFO_INT, /*!< keycode fifo mode interrupt*/ +// KYS_GHOST_INT, /*!< */ +// KYS_INT_ALL, +// } KYS_INT_Type; + +/** + * @brief KYS Interrupt Status type definition + * + */ +typedef enum { + KYS_INT_KS_DONE, /*!< keyscan done status */ + KYS_INT_KEYFIFO_FULL, /*!< keycode FIFO full detection */ + KYS_INT_KEYFIFO_HALF, /*!< keycode FIFO half detection */ + KYS_INT_KEYFIFO_QUARTER, /*!< keycode FIFO quarter detection */ + KYS_INT_KEYFIFO_NONEMPTY, /*!< keycode FIFO nonempty detection */ + KYS_INT_GHOST_DET, /*!< ghost key event detection status (keycode=0xF5 is ghost key) */ + KYS_INT_ALL, +} KYS_INT_Type; + +typedef enum { + KYS_INT_KS_DONE_CLR = 7, + KYS_INT_KEYFIFO_CLR = 8, + KYS_INT_GHOST_CLR = 12, + KYS_INT_CLR_ALL, +} KYS_INT_CLR_Type; + +/** + * @brief KYS configuration structure type definition + */ +typedef struct +{ + uint8_t col; /*!< Col of keyboard,max:8 */ + uint8_t row; /*!< Row of keyboard,max:8 */ + uint8_t idle_duration; /*!< Idle duration between column scans */ + uint8_t fifo_mode; /*!< Fifo mode for keycode (incremental) */ + BL_Fun_Type ghost_en; /*!< Enable or disable ghost key event detection */ + BL_Fun_Type deglitch_en; /*!< Enable or disable deglitch function */ + uint8_t deglitch_cnt; /*!< Deglitch count */ +} KYS_CFG_Type; + +/*@} end of group KYS_Public_Types */ + +/** @defgroup KYS_Public_Constants + * @{ + */ + +/** @defgroup KYS_INT_TYPE + * @{ + */ +#define IS_KYS_INT_TYPE(type) (((type) == KYS_INT_KS_DONE) || \ + ((type) == KYS_INT_KEYFIFO_FULL) || \ + ((type) == KYS_INT_KEYFIFO_HALF) || \ + ((type) == KYS_INT_KEYFIFO_QUARTER) || \ + ((type) == KYS_INT_KEYFIFO_NONEMPTY) || \ + ((type) == KYS_INT_GHOST_DET) || \ + ((type) == KYS_INT_ALL)) + +/** @defgroup KYS_INT_CLR_TYPE + * @{ + */ +#define IS_KYS_INT_CLR_TYPE(type) (((type) == KYS_INT_KS_DONE_CLR) || \ + ((type) == KYS_INT_KEYFIFO_CLR) || \ + ((type) == KYS_INT_GHOST_CLR) || \ + ((type) == KYS_INT_CLR_ALL)) + +/*@} end of group KYS_Public_Constants */ + +/** @defgroup KYS_Public_Macros + * @{ + */ + +/*@} end of group KYS_Public_Macros */ + +/** @defgroup KYS_Public_Functions + * @{ + */ + +/** + * @brief UART Functions + */ +// #ifndef BFLB_USE_HAL_DRIVER +void KYS_IRQHandler(void); +// #endif +BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg); +BL_Err_Type KYS_Enable(void); +BL_Err_Type KYS_Disable(void); +BL_Err_Type KYS_IntMask(KYS_INT_Type intType, BL_Mask_Type intMask); +BL_Err_Type KYS_IntClear(KYS_INT_CLR_Type intType); +BL_Err_Type KYS_Int_Callback_Install(KYS_INT_Type intType, intCallback_Type *cbFun); +BL_Sts_Type KYS_GetIntStatus(KYS_INT_Type intType); +uint8_t KYS_ReadKeyfifo(void); +void KYS_Get_FIFO_Idx(uint8_t *fifo_head, uint8_t *fifo_tail); +// uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row); + +/*@} end of group KYS_Public_Functions */ + +/*@} end of group KYS */ + +/*@} end of group BL702_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_KYS_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_l1c.h b/drivers/soc/bl702l/std/include/bl702l_l1c.h new file mode 100644 index 000000000..0cc8cdd22 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_l1c.h @@ -0,0 +1,210 @@ +/** + ****************************************************************************** + * @file bl702l_l1c.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_L1C_H__ +#define __BL702L_L1C_H__ + +#include "l1c_reg.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Public_Types + * @{ + */ + +/** + * @brief L1C configuration structure type definition + */ +typedef struct +{ + BL_Fun_Type wrapDis; /*!< wrap disable */ + BL_Fun_Type bypassEn; /*!< bypass cache enable */ + uint8_t wayDis; /*!< Disable part of cache ways & used as ITCM */ + BL_Fun_Type cntEn; /*!< l1c count enable */ +} L1C_CACHE_Cfg_Type; + +/** + * @brief L1C BMX arb mode type definition + */ +typedef enum { + L1C_BMX_ARB_FIX, /*!< 0->fix */ + L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */ + L1C_BMX_ARB_RANDOM, /*!< 3->random */ +} L1C_BMX_ARB_Type; + +/** + * @brief L1C BMX configuration structure type definition + */ +typedef struct +{ + uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */ + BL_Fun_Type errEn; /*!< Bus error response enable */ + L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */ +} L1C_BMX_Cfg_Type; + +/** + * @brief L1C BMX bus err type definition + */ +typedef enum { + L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */ + L1C_BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */ +} L1C_BMX_BUS_ERR_Type; + +/** + * @brief L1C BMX bus err interrupt type definition + */ +typedef enum { + L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */ + L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */ +} L1C_BMX_ERR_INT_Type; + +/** + * @brief L1C BMX time out interrupt type definition + */ +typedef enum { + L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */ + L1C_BMX_TO_INT_ALL, /*!< L1C_BMX timeout interrupt max num */ +} L1C_BMX_TO_INT_Type; + +/*@} end of group L1C_Public_Types */ + +/** @defgroup L1C_Public_Constants + * @{ + */ + +/** @defgroup L1C_BMX_ARB_TYPE + * @{ + */ +#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) || \ + ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \ + ((type) == L1C_BMX_ARB_RANDOM)) + +/** @defgroup L1C_BMX_BUS_ERR_TYPE + * @{ + */ +#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \ + ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE)) + +/** @defgroup L1C_BMX_ERR_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \ + ((type) == L1C_BMX_ERR_INT_ALL)) + +/** @defgroup L1C_BMX_TO_INT_TYPE + * @{ + */ +#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \ + ((type) == L1C_BMX_TO_INT_ALL)) + +/*@} end of group L1C_Public_Constants */ + +/** @defgroup L1C_Public_Macros + * @{ + */ +#define L1C_WAY_DISABLE_NONE 0x00 +#define L1C_WAY_DISABLE_ONE 0x01 +#define L1C_WAY_DISABLE_TWO 0x03 +#define L1C_WAY_DISABLE_THREE 0x07 +#define L1C_WAY_DISABLE_ALL 0x0F +#define L1C_WAY_DISABLE_USER 0xFF +#if 1 +/*NP config address */ +#define L1C_CONF_REG (L1C_BASE + 0x00) +#define L1C_HIT_CNT_LSB_REG (L1C_BASE + 0x04) +#define L1C_HIT_CNT_MSB_REG (L1C_BASE + 0x08) +#define L1C_MISS_CNT_REG (L1C_BASE + 0x0C) +/* Get miss and hit count */ +#define L1C_Get_Miss_Cnt() BL702L_REG_RD(L1C_MISS_CNT_REG) +#define L1C_Get_Hit_Cnt_LSB() BL702L_REG_RD(L1C_HIT_CNT_LSB_REG) +#define L1C_Get_Hit_Cnt_MSB() BL702L_REG_RD(L1C_HIT_CNT_MSB_REG) +#endif + +/*@} end of group L1C_Public_Macros */ + +/** @defgroup L1C_Public_Functions + * @{ + */ +/*----------*/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void); +void L1C_BMX_TO_IRQHandler(void); +#endif +/*----------*/ +void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn); +BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable); +BL_Err_Type L1C_Cache_Flush(void); +void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh); +uint32_t L1C_Cache_Miss_Count_Get(void); +void L1C_Cache_Read_Disable(void); +/*----------*/ +BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap); +BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal); +BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable); +/*----------*/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg); +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void); +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void); +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void); +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType); +uint32_t L1C_BMX_Get_Err_Addr(void); +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun); +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, + intCallback_Type *cbFun); +/*----------*/; + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_L1C_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_pds.h b/drivers/soc/bl702l/std/include/bl702l_pds.h new file mode 100644 index 000000000..91a67a237 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_pds.h @@ -0,0 +1,710 @@ +/** + ****************************************************************************** + * @file bl702l_pds.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_PDS_H__ +#define __BL702L_PDS_H__ + +#include "pds_reg.h" +#include "bl702l_aon.h" +#include "bl702l_hbn.h" +#include "bl702l_common.h" +#include "bflb_sflash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Public_Types + * @{ + */ + +/** + * @brief PDS GPIO configuration type definition + */ +typedef struct +{ + uint8_t pd_en; + uint8_t pu_en; + uint8_t ie_en; + uint8_t oe_en; +} PDS_GPIO_Cfg_Type; + +/** + * @brief PDS RAM configuration type definition + */ +typedef struct +{ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET1N : 1; /*!< [0] 0~16KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET1N : 1; /*!< [1] 16~32KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET1N : 1; /*!< [2] 32~48KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET1N : 1; /*!< [3] 48~64KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_64KB_80KB_CPU_RAM_RET1N : 1; /*!< [4] 64~80KB cpu_ram RET1N */ + uint32_t PDS_RAM_CFG_RSV_5_7 : 3; /*!< [7:5]reserve */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET2N : 1; /*!< [8] 0~16KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET2N : 1; /*!< [9] 16~32KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET2N : 1; /*!< [10] 32~48KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET2N : 1; /*!< [11] 48~64KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_64KB_80KB_CPU_RAM_RET2N : 1; /*!< [12] 64~80KB cpu_ram RET2N */ + uint32_t PDS_RAM_CFG_RSV_13_15 : 3; /*!< [15:13]reserve */ + uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_PGEN : 1; /*!< [16] 0~16KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_PGEN : 1; /*!< [17] 16~32KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_PGEN : 1; /*!< [18] 32~48KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_PGEN : 1; /*!< [19] 48~64KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_64KB_80KB_CPU_RAM_PGEN : 1; /*!< [20] 64~80KB cpu_ram PGEN */ + uint32_t PDS_RAM_CFG_RSV_21_31 : 11; /*!< [31:21]reserve */ +} PDS_RAM_CFG_Type; + +/** + * @brief PDS configuration type definition + */ +typedef struct +{ + uint32_t pdsStart : 1; /*!< [0]PDS Start */ + uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */ + uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */ + uint32_t waitRC32mRdy : 1; /*!< [3]wait XTAL Ready during before PDS Interrupt */ + uint32_t avdd14Off : 1; /*!< [4]power down avdd14 during PDS */ + uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */ + uint32_t glbRstProtect : 1; /*!< [6]avoid glb_reg reset by any reset */ + uint32_t puFlash : 1; /*!< [7]turn off Flash Power During PDS */ + uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */ + uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */ + uint32_t swPuFlash : 1; /*!< [10]SW Turn on Flash */ + uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */ + uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */ + uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */ + uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */ + uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */ + uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */ + uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */ + uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */ + uint32_t rsv19 : 1; /*!< [19]Reserved */ + uint32_t xtalCntRC32kEn : 1; /*!< [20]HW Auto count RC32K to be XTAL Counter after PDS */ + uint32_t cpu0WfiMask : 1; /*!< [21]pds start condition mask np_wfi */ + uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */ + uint32_t pdsCtlRfSel : 1; /*!< [23]PDS control RF on/off */ + uint32_t xtalDegEn : 1; /*!< [24]Enable Digital Deg */ + uint32_t bleWakeupReqEn : 1; /*!< [25]PDS auto send ble_wakeup_req to sleep_timer when exit PDS */ + uint32_t swGpioIsoMod : 1; /*!< [26]SW force keep GPIO */ + uint32_t pdsClkOff : 1; /*!< [27]Turn off PDS Clock , Set this bit to 0 to active PDS */ + uint32_t pdsGpioKeep : 3; /*!< [30:28]enable or disable keep function */ + uint32_t pdsGpioIsoMod : 1; /*!< [31]HW Keep GPIO at PDS Mode */ +} PDS_CTL_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t rsv0_7 : 8; /*!< [7:0]reserve */ + uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */ + uint32_t rsv9 : 1; /*!< [9]reserve */ + uint32_t forceBzPdsRst : 1; /*!< [10]manual force BZ pds reset */ + uint32_t rsv11_15 : 5; /*!< [15:11]reserve */ + uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */ + uint32_t rsv17 : 1; /*!< [17]reserve */ + uint32_t forceBzGateClk : 1; /*!< [18]manual force BZ clock gated */ + uint32_t rsv19_31 : 13; /*!< [31:19]reserve */ +} PDS_CTL2_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t rsv0 : 1; /*!< [0]reserve */ + uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */ + uint32_t rsv2_6 : 5; /*!< [6:2]reserve */ + uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */ + uint32_t rsv8_12 : 5; /*!< [12:8]reserve */ + uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */ + uint32_t rsv14_29 : 16; /*!< [29:14]reserve */ + uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */ + uint32_t rsv31 : 1; /*!< [31]reserve */ +} PDS_CTL3_Type; + +/** + * @brief PDS force configuration type definition + */ +typedef struct +{ + uint32_t rsv0 : 1; /*!< [0]reserve */ + uint32_t cpuRst : 1; /*!< [1]NP reset at PDS Sleep state */ + uint32_t rsv2 : 1; /*!< [2]reserve */ + uint32_t cpuGateClk : 1; /*!< [3]NP clock gated at PDS Sleep state */ + uint32_t rsv4_12 : 9; /*!< [12:4]reserve */ + uint32_t BzRst : 1; /*!< [13]BZ reset at PDS Sleep state */ + uint32_t rsv14 : 1; /*!< [14]reserve */ + uint32_t BzGateClk : 1; /*!< [15]BZ clock gated at PDS Sleep state */ + uint32_t rsv16_23 : 8; /*!< [23:16]reserve */ + uint32_t MiscPwrOff : 1; /*!< [24]core_misc Power off at PDS Sleep state */ + uint32_t MiscRst : 1; /*!< [25]core_misc reset at PDS Sleep state */ + uint32_t rsv26 : 1; /*!< [26]reserve */ + uint32_t MiscGateClk : 1; /*!< [27]core_misc clock gated at PDS Sleep state */ + uint32_t rsv28_31 : 4; /*!< [30:28]reserve */ +} PDS_CTL4_Type; + +/** + * @brief PDS default level configuration type definition + */ +typedef struct +{ + PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */ + PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */ + PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */ + PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */ +} PDS_DEFAULT_LV_CFG_Type; + +/** + * @brief PDS interrupt type definition + */ +typedef enum { + PDS_INT_WAKEUP = 0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */ + PDS_INT_RF_DONE = 2, /*!< PDS RF done interrupt */ + PDS_INT_MAX, /*!< PDS int max number */ +} PDS_INT_Type; + +typedef enum { + PDS_WAKEUP_SRC_HBN_IRQ_OUT = 0, /*!< wakeup trigger by hbn_irq_out[1:0] */ + PDS_WAKEUP_SRC_KYD_WAKEUP, /*!< wakeup trigger by pds_kyd_wakeup */ + PDS_WAKEUP_SRC_GPIO_IRQ, /*!< wakeup trigger by gpio_irq */ + PDS_WAKEUP_SRC_PDS_IO_INT, /*!< wakeup trigger by irrx_int */ + PDS_WAKEUP_SRC_BLE_SLP_IRQ, /*!< wakeup trigger by ble_slp_irq */ + PDS_WAKEUP_SRC_KYS_INT, /*!< wakeup trigger by kys_int */ + PDS_WAKEUP_SRC_WDG_TIMEOUT, /*!< wakeup trigger by pds_watchdog_timeout event */ +} PDS_WAKEUP_SRC_Type; +/** + * @brief PDS GPIO type definition + */ +typedef enum { + PDS_GPIO_PIN_0 = 0, + PDS_GPIO_PIN_1, + PDS_GPIO_PIN_2, + PDS_GPIO_PIN_3, + PDS_GPIO_PIN_7 = 7, + PDS_GPIO_PIN_8, + PDS_GPIO_PIN_14 = 14, + PDS_GPIO_PIN_15, + PDS_GPIO_PIN_16, + PDS_GPIO_PIN_17, + PDS_GPIO_PIN_18, + PDS_GPIO_PIN_19, + PDS_GPIO_PIN_20, + PDS_GPIO_PIN_21, + PDS_GPIO_PIN_22, + PDS_GPIO_PIN_23, + PDS_GPIO_PIN_24, + PDS_GPIO_PIN_25, + PDS_GPIO_PIN_26, + PDS_GPIO_PIN_27, + PDS_GPIO_PIN_28, + PDS_GPIO_PIN_29, + PDS_GPIO_PIN_MAX, +} PDS_GPIO_Type; + +typedef enum { + PDS_KEY_ROW_0 = 0, + PDS_KEY_ROW_1, + PDS_KEY_ROW_2, + PDS_KEY_ROW_3, + PDS_KEY_ROW_4, + PDS_KEY_ROW_5, + PDS_KEY_ROW_6, + PDS_KEY_ROW_7, +} PDS_KEY_ROW_Type; + +typedef enum { + PDS_KEY_COL_0 = 0, + PDS_KEY_COL_1, + PDS_KEY_COL_2, + PDS_KEY_COL_3, + PDS_KEY_COL_4, + PDS_KEY_COL_5, + PDS_KEY_COL_6, + PDS_KEY_COL_7, +} PDS_KEY_COL_Type; + +/** + * @brief PDS KYS COL and ROW GPIO Select + */ +typedef enum { + PDS_KYS_GPIO_PIN_0 = 0, + PDS_KYS_GPIO_PIN_1, + PDS_KYS_GPIO_PIN_2, + PDS_KYS_GPIO_PIN_3, + PDS_KYS_GPIO_PIN_7 = 7, + PDS_KYS_GPIO_PIN_8, + PDS_KYS_GPIO_PIN_9, + PDS_KYS_GPIO_PIN_10, + PDS_KYS_GPIO_PIN_11, + PDS_KYS_GPIO_PIN_12, + PDS_KYS_GPIO_PIN_13, + PDS_KYS_GPIO_PIN_14, + PDS_KYS_GPIO_PIN_15, + PDS_KYS_GPIO_PIN_16, + PDS_KYS_GPIO_PIN_17, + PDS_KYS_GPIO_PIN_18, + PDS_KYS_GPIO_PIN_19, + PDS_KYS_GPIO_PIN_20, + PDS_KYS_GPIO_PIN_21, + PDS_KYS_GPIO_PIN_22, + PDS_KYS_GPIO_PIN_23, + PDS_KYS_GPIO_PIN_24, + PDS_KYS_GPIO_PIN_25, + PDS_KYS_GPIO_PIN_26, + PDS_KYS_GPIO_PIN_27, + PDS_KYS_GPIO_PIN_28, + PDS_KYS_GPIO_PIN_29, + PDS_KYS_GPIO_PIN_30, + PDS_KYS_GPIO_PIN_31, + PDS_KYS_GPIO_PIN_MAX, +} PDS_KYS_GPIO_Type; + +/** + * @brief PDS KYD White Key Select + */ +typedef enum { + PDS_KYD_NO_WHITE_KEY_MODE = 0, + PDS_KYD_INVERT_DETECT_MODE, + PDS_KYD_MASK_DETECT_MODE, +} PDS_KYD_WHITE_KEY_MODE_Type; + +/** + * @brief PDS GPIO group set type + */ +typedef enum { + PDS_GPIO_GROUP_SET_GPIO0_GPIO3, /*!< gpio int set 0, gpio0 - gpio3 */ + PDS_GPIO_GROUP_SET_GPIO7, /*!< gpio int set 1, gpio7 */ + PDS_GPIO_GROUP_SET_GPIO8, /*!< gpio int set 2, gpio8 */ + PDS_GPIO_GROUP_SET_GPIO14_GPIO15, /*!< gpio int set 3, gpio14 - gpio15 */ + PDS_GPIO_GROUP_SET_GPIO16_GPIO19, /*!< gpio int set 4, gpio16 - gpio19 */ + PDS_GPIO_GROUP_SET_GPIO20_GPIO23, /*!< gpio int set 5, gpio20 - gpio23 */ + PDS_GPIO_GROUP_SET_GPIO24_GPIO27, /*!< gpio int set 6, gpio14 - gpio17 */ + PDS_GPIO_GROUP_SET_GPIO28_GPIO29, /*!< gpio int set 7, gpio28 - gpio29 */ +} PDS_GPIO_GROUP_SET_Type; + +/** + * @brief PDS reset event type definition + */ +typedef enum { + PDS_RST_EVENT_BUS_RST, /*!< hreset_n (Bus Reset) */ + PDS_RST_EVENT_HBN_PWR_ON_RST, /*!< pwr_rst_n (hbn power on reset) */ + PDS_RST_EVENT_PDS_RST, /*!< pds_rst_n (pds reset) */ + PDS_RST_EVENT_MAX, /*!< PDS rst event max number */ +} PDS_RST_EVENT_Type; + +/** + * @brief PDS RF status type definition + */ +typedef enum { + PDS_RF_STS_OFF = 0, /*!< 4'b0000 */ + PDS_RF_STS_PU_MBG = 1, /*!< 4'b0001 */ + PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */ + PDS_RF_STS_PU_SFREG = 7, /*!< 4'b0111 */ + PDS_RF_STS_BZ_EN_AON = 15, /*!< 4'b1111 */ +} PDS_RF_STS_Type; + +/** + * @brief PDS status type definition + */ +typedef enum { + PDS_STS_IDLE = 0, /*!< 4'b0000 */ + PDS_STS_ECG = 8, /*!< 4'b1000 */ + PDS_STS_ERST = 12, /*!< 4'b1100 */ + PDS_STS_EISO = 15, /*!< 4'b1111 */ + PDS_STS_POFF = 7, /*!< 4'b0111 */ + PDS_STS_PRE_BGON = 3, /*!< 4'b0011 */ + PDS_STS_PRE_BGON1 = 1, /*!< 4'b0001 */ + PDS_STS_BGON = 5, /*!< 4'b0101 */ + PDS_STS_CLK_SW_32M = 4, /*!< 4'b0100 */ + PDS_STS_PON_DCDC = 6, /*!< 4'b0110 */ + PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */ + PDS_STS_PON = 10, /*!< 4'b1010 */ + PDS_STS_DISO = 2, /*!< 4'b0010 */ + PDS_STS_DCG = 13, /*!< 4'b1101 */ + PDS_STS_DRST = 11, /*!< 4'b1011 */ + PDS_STS_WAIT_EFUSE = 9, /*!< 4'b1001 */ +} PDS_STS_Type; + +/** + * @brief PDS auto power down configuration type definition + */ +typedef struct +{ + BL_Fun_Type mbgPower; /*!< PDS auto [31] MBG power */ + BL_Fun_Type ldo18rfPower; /*!< PDS auto [30] LDO18RF power */ + BL_Fun_Type sfregPower; /*!< PDS auto [29] SF_REG power */ + BL_Fun_Type pllPower; /*!< PDS auto [28] PLL power */ + BL_Fun_Type cpu0Power; /*!< PDS auto [19] NP power */ + BL_Fun_Type rc32mPower; /*!< PDS auto [17] RC32M power */ + BL_Fun_Type xtalPower; /*!< PDS auto [14] XTAL power */ + BL_Fun_Type allPower; /*!< PDS auto [13] all power */ + BL_Fun_Type isoPower; /*!< PDS auto [11] ISO power */ + BL_Fun_Type bzPower; /*!< PDS auto [10] BZ power */ + BL_Fun_Type sramDisStanby; /*!< PDS auto [9] SRAM memory stanby disable */ + BL_Fun_Type cgPower; /*!< PDS auto [8] CG power */ + BL_Fun_Type cpu1Power; /*!< PDS auto [7] AP power */ + BL_Fun_Type usbPower; /*!< PDS auto [3] USB power */ +} PDS_AUTO_POWER_DOWN_CFG_Type; + +/** + * @brief PDS auto configuration type definition + */ +typedef struct +{ + uint32_t vddcoreVol; /*!< PDS auto [27:24] VDDCORE voltage, reference 0x4001F80C[27:24], recommended 0xA */ + BL_Fun_Type vddcoreVolEn; /*!< PDS auto [18] VDDCORE voltage enable bit */ + BL_Fun_Type cpu0NotNeedWFI; /*!< PDS auto [21] NP not need WFI to get in PDS mode */ + BL_Fun_Type cpu1NotNeedWFI; /*!< PDS auto [20] AP not need WFI to get in PDS mode */ + BL_Fun_Type busReset; /*!< PDS auto [16] bus reset bit, reset after wake up from PDS mode */ + BL_Fun_Type disIrqWakeUp; /*!< PDS auto [15] disable IRQ request to wake up from PDS mode, except PDS counter IRQ */ + BL_Fun_Type powerOffXtalForever; /*!< PDS auto [2] power off xtal after get in PDS mode, and never power on xtal after wake up */ + BL_Fun_Type sleepForever; /*!< PDS auto [1] sleep forever after get in PDS mode, need reset system to restart */ +} PDS_AUTO_NORMAL_CFG_Type; + +/** + * @brief PDS force type definition + */ +typedef enum { + PDS_FORCE_NP, /*!< PDS force NP */ + PDS_FORCE_RSV, /*!< rsv */ + PDS_FORCE_BZ, /*!< PDS force BZ */ +} PDS_FORCE_Type; + +/*@} end of group PDS_Public_Types */ + +/** @defgroup PDS_Public_Constants + * @{ + */ + +/** @defgroup PDS_INT_TYPE + * @{ + */ +#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \ + ((type) == PDS_INT_RF_DONE)) + +/** @defgroup PDS_WAKEUP_SRC_Type + * @{ + */ +#define IS_PDS_WAKEUP_SRC_Type (((type) == PDS_WAKEUP_SRC_HBN_IRQ_OUT) || \ + ((type) == PDS_WAKEUP_SRC_KYD_WAKEUP) || \ + ((type) == PDS_WAKEUP_SRC_GPIO_IRQ) || \ + ((type) == PDS_WAKEUP_SRC_PDS_IO_INT) || \ + ((type) == PDS_WAKEUP_SRC_BLE_SLP_IRQ) || \ + ((type) == PDS_WAKEUP_SRC_KYS_INT) || \ + ((type) == PDS_WAKEUP_SRC_WDG_TIMEOUT)) + +/** @defgroup PDS_GPIO_Type + * @{ + */ +#define IS_PDS_GPIO_TYPE(type) (((type) == PDS_GPIO_PIN_0) || \ + ((type) == PDS_GPIO_PIN_1) || \ + ((type) == PDS_GPIO_PIN_2) || \ + ((type) == PDS_GPIO_PIN_3) || \ + ((type) == PDS_GPIO_PIN_7) || \ + ((type) == PDS_GPIO_PIN_8) || \ + ((type) == PDS_GPIO_PIN_14) || \ + ((type) == PDS_GPIO_PIN_15) || \ + ((type) == PDS_GPIO_PIN_16) || \ + ((type) == PDS_GPIO_PIN_17) || \ + ((type) == PDS_GPIO_PIN_18) || \ + ((type) == PDS_GPIO_PIN_19) || \ + ((type) == PDS_GPIO_PIN_20) || \ + ((type) == PDS_GPIO_PIN_21) || \ + ((type) == PDS_GPIO_PIN_22) || \ + ((type) == PDS_GPIO_PIN_23) || \ + ((type) == PDS_GPIO_PIN_24) || \ + ((type) == PDS_GPIO_PIN_25) || \ + ((type) == PDS_GPIO_PIN_26) || \ + ((type) == PDS_GPIO_PIN_27) || \ + ((type) == PDS_GPIO_PIN_28) || \ + ((type) == PDS_GPIO_PIN_29)) + +/** @defgroup PDS_KYS_GPIO_Type + * @{ + */ +#define IS_PDS_KYS_GPIO_TYPE(type) (((type) == PDS_KYS_GPIO_PIN_0) || \ + ((type) == PDS_KYS_GPIO_PIN_1) || \ + ((type) == PDS_KYS_GPIO_PIN_2) || \ + ((type) == PDS_KYS_GPIO_PIN_3) || \ + ((type) == PDS_KYS_GPIO_PIN_7) || \ + ((type) == PDS_KYS_GPIO_PIN_8) || \ + ((type) == PDS_KYS_GPIO_PIN_9) || \ + ((type) == PDS_KYS_GPIO_PIN_10) || \ + ((type) == PDS_KYS_GPIO_PIN_11) || \ + ((type) == PDS_KYS_GPIO_PIN_12) || \ + ((type) == PDS_KYS_GPIO_PIN_13) || \ + ((type) == PDS_KYS_GPIO_PIN_14) || \ + ((type) == PDS_KYS_GPIO_PIN_15) || \ + ((type) == PDS_KYS_GPIO_PIN_16) || \ + ((type) == PDS_KYS_GPIO_PIN_17) || \ + ((type) == PDS_KYS_GPIO_PIN_18) || \ + ((type) == PDS_KYS_GPIO_PIN_19) || \ + ((type) == PDS_KYS_GPIO_PIN_20) || \ + ((type) == PDS_KYS_GPIO_PIN_21) || \ + ((type) == PDS_KYS_GPIO_PIN_22) || \ + ((type) == PDS_KYS_GPIO_PIN_23) || \ + ((type) == PDS_KYS_GPIO_PIN_24) || \ + ((type) == PDS_KYS_GPIO_PIN_25) || \ + ((type) == PDS_KYS_GPIO_PIN_26) || \ + ((type) == PDS_KYS_GPIO_PIN_27) || \ + ((type) == PDS_KYS_GPIO_PIN_28) || \ + ((type) == PDS_KYS_GPIO_PIN_29) || \ + ((type) == PDS_KYS_GPIO_PIN_30) || \ + ((type) == PDS_KYS_GPIO_PIN_31)) + +#define IS_PDS_KYS_ROW_TYPE(type) (((type) == PDS_KEY_ROW_0) || \ + ((type) == PDS_KEY_ROW_1) || \ + ((type) == PDS_KEY_ROW_2) || \ + ((type) == PDS_KEY_ROW_3) || \ + ((type) == PDS_KEY_ROW_4) || \ + ((type) == PDS_KEY_ROW_5) || \ + ((type) == PDS_KEY_ROW_6) || \ + ((type) == PDS_KEY_ROW_7)) + +#define IS_PDS_KYS_COL_TYPE(type) (((type) == PDS_KEY_COL_0) || \ + ((type) == PDS_KEY_COL_1) || \ + ((type) == PDS_KEY_COL_2) || \ + ((type) == PDS_KEY_COL_3) || \ + ((type) == PDS_KEY_COL_4) || \ + ((type) == PDS_KEY_COL_5) || \ + ((type) == PDS_KEY_COL_6) || \ + ((type) == PDS_KEY_COL_7)) + +/** @defgroup PDS_GPIO_GROUP_SET_Type + * @{ + */ +#define IS_PDS_GPIO_GROUP_SET_Type(type) (((type) == PDS_GPIO_GROUP_SET_GPIO0_GPIO3) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO7) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO8) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO14_GPIO15) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO16_GPIO19) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO20_GPIO23) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO24_GPIO27) || \ + ((type) == PDS_GPIO_GROUP_SET_GPIO28_GPIO29)) + +/** + * @brief PDS GPIO interrupt control mode type definition + */ +typedef enum { + PDS_GPIO_INT_SYNC_FALLING_EDGE = 0, /*!< GPIO interrupt sync mode, GPIO negedge pulse trigger interrupt */ + PDS_GPIO_INT_SYNC_RISING_EDGE = 1, /*!< GPIO interrupt sync mode, GPIO posedge pulse trigger interrupt */ + PDS_GPIO_INT_SYNC_LOW_LEVEL = 2, /*!< GPIO interrupt sync mode, GPIO negedge level trigger interrupt */ + PDS_GPIO_INT_SYNC_HIGH_LEVEL = 3, /*!< GPIO interrupt sync mode, GPIO posedge level trigger interrupt */ + PDS_GPIO_INT_SYNC_RISING_FALLING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO posedge negedge pulse trigger interrupt */ + PDS_GPIO_INT_ASYNC_FALLING_EDGE = 8, /*!< GPIO interrupt async mode, GPIO negedge pulse trigger interrupt */ + PDS_GPIO_INT_ASYNC_RISING_EDGE = 9, /*!< GPIO interrupt async mode, GPIO posedge pulse trigger interrupt */ + PDS_GPIO_INT_ASYNC_LOW_LEVEL = 10, /*!< GPIO interrupt async mode, GPIO negedge level trigger interrupt */ + PDS_GPIO_INT_ASYNC_HIGH_LEVEL = 11, /*!< GPIO interrupt async mode, GPIO posedge level trigger interrupt */ +} PDS_GPIO_INT_TRIG_Type; + +/** @defgroup PDS_RST_EVENT_TYPE + * @{ + */ +#define IS_PDS_RST_EVENT_TYPE(type) (((type) == PDS_RST_EVENT_BUS_RST) || \ + ((type) == PDS_RST_EVENT_HBN_PWR_ON_RST) || \ + ((type) == PDS_RST_EVENT_PDS_RST) || \ + ((type) == PDS_RST_EVENT_MAX)) + +/** @defgroup PDS_PLL_STS_TYPE + * @{ + */ +#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \ + ((type) == PDS_PLL_STS_SFREG) || \ + ((type) == PDS_PLL_STS_PU) || \ + ((type) == PDS_PLL_STS_RDY)) + +/** @defgroup PDS_RF_STS_TYPE + * @{ + */ +#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \ + ((type) == PDS_RF_STS_PU_MBG) || \ + ((type) == PDS_RF_STS_PU_LDO15RF) || \ + ((type) == PDS_RF_STS_PU_SFREG) || \ + ((type) == PDS_RF_STS_BZ_EN_AON)) + +/** @defgroup PDS_STS_TYPE + * @{ + */ +#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \ + ((type) == PDS_STS_ECG) || \ + ((type) == PDS_STS_ERST) || \ + ((type) == PDS_STS_EISO) || \ + ((type) == PDS_STS_POFF) || \ + ((type) == PDS_STS_PRE_BGON) || \ + ((type) == PDS_STS_PRE_BGON1) || \ + ((type) == PDS_STS_BGON) || \ + ((type) == PDS_STS_CLK_SW_32M) || \ + ((type) == PDS_STS_PON_DCDC) || \ + ((type) == PDS_STS_PON_LDO11_MISC) || \ + ((type) == PDS_STS_PON) || \ + ((type) == PDS_STS_DISO) || \ + ((type) == PDS_STS_DCG) || \ + ((type) == PDS_STS_DRST) || \ + ((type) == PDS_STS_WAIT_EFUSE)) + +/** @defgroup PDS_PLL_XTAL_TYPE + * @{ + */ +#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \ + ((type) == PDS_PLL_XTAL_32M) || \ + ((type) == PDS_PLL_XTAL_RC32M)) + +/** @defgroup PDS_PLL_CLK_TYPE + * @{ + */ +#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \ + ((type) == PDS_PLL_CLK_240M) || \ + ((type) == PDS_PLL_CLK_192M) || \ + ((type) == PDS_PLL_CLK_160M) || \ + ((type) == PDS_PLL_CLK_120M) || \ + ((type) == PDS_PLL_CLK_96M) || \ + ((type) == PDS_PLL_CLK_80M) || \ + ((type) == PDS_PLL_CLK_48M) || \ + ((type) == PDS_PLL_CLK_32M)) + +/** @defgroup PDS_FORCE_TYPE + * @{ + */ +#define IS_PDS_FORCE_TYPE(type) (((type) == PDS_FORCE_NP) || \ + ((type) == PDS_FORCE_RSV) || \ + ((type) == PDS_FORCE_BZ) || \ + ((type) == PDS_FORCE_USB)) + +/** @defgroup PDS_AUDIO_PLL_TYPE + * @{ + */ +#define IS_PDS_AUDIO_PLL_TYPE(type) (((type) == AUDIO_PLL_12288000_HZ) || \ + ((type) == AUDIO_PLL_11289600_HZ) || \ + ((type) == AUDIO_PLL_5644800_HZ) || \ + ((type) == AUDIO_PLL_24576000_HZ) || \ + ((type) == AUDIO_PLL_24000000_HZ) || \ + ((type) == AUDIO_PLL_50000000_HZ)) + +/*@} end of group PDS_Public_Constants */ + +/** @defgroup PDS_Public_Macros + * @{ + */ +#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */ +#define PDS_WARMUP_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */ +#define PDS_FORCE_PWR_OFF_OFFSET (0) +#define PDS_FORCE_ISO_EN_OFFSET (4) +#define PDS_FORCE_PDS_RST_OFFSET (8) +#define PDS_FORCE_MEM_STBY_OFFSET (12) +#define PDS_FORCE_GATE_CLK_OFFSET (16) + +#define PDS_GPIO_IS_GROUP_ID(pin) (pin >> 2) +/*@} end of group PDS_Public_Macros */ + +/** @defgroup PDS_Public_Functions + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun); +void PDS_WAKEUP_IRQHandler(void); +#endif +/*----------*/ +BL_Err_Type PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_Type pin, PDS_GPIO_Cfg_Type *cfg); +BL_Err_Type PDS_GPIO_Write(PDS_GPIO_GROUP_SET_Type grp, uint32_t val); +BL_Err_Type PDS_Set_GPIO_Pad_IntMask(PDS_GPIO_GROUP_SET_Type grp, BL_Mask_Type intMask); +BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_GROUP_SET_Type grp, PDS_GPIO_INT_TRIG_Type trig); +BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_GROUP_SET_Type grp); +BL_Err_Type PDS_Set_All_GPIO_IntClear(void); +BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(PDS_GPIO_Type pin); +/*----------*/ +BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg); +BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg); +/*----------*/ +BL_Err_Type PDS_Disable_GPIO_Keep(void); +BL_Err_Type PDS_Enable_PDS_Pad_Keep(uint32_t keepSel); +/*----------*/ +BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt); +BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3); +BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg); +BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt); +/*----------*/ +BL_Err_Type PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_Type intType, BL_Fun_Type enable); +BL_Sts_Type PDS_Get_Wakeup_Src(PDS_WAKEUP_SRC_Type intType); +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask); +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType); +BL_Err_Type PDS_IntClear(void); +/*----------*/ +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void); +PDS_STS_Type PDS_Get_PdsStstus(void); +/*----------*/ +BL_Err_Type PDS_Clear_Reset_Event(void); +BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event); +/*----------*/ +BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void); +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun); +/*----------*/ +// void PDS_Auto_Time_Config(uint32_t sleepDuration); +void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable); +void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain); +void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain); +/*----------*/ +BL_Err_Type PDS_Set_KYD_Matrix_Size(uint8_t col_size, uint8_t row_size); +BL_Err_Type PDS_Set_KYD_Col_Value(uint8_t val); +BL_Err_Type PDS_Set_KYD_Row_Pull(uint8_t en); +BL_Err_Type PDS_Set_KYD_Wakeup_En(uint8_t en); +BL_Err_Type PDS_Clear_KYD_Wakeup(void); +BL_Err_Type PDS_Set_KYS_ROW_IN_GPIO(PDS_KEY_ROW_Type row_x, PDS_KYS_GPIO_Type sel_io); +BL_Err_Type PDS_Set_KYS_COL_OUT_GPIO(PDS_KEY_COL_Type col_x, PDS_KYS_GPIO_Type sel_io); +BL_Err_Type PDS_Get_KYS_Wakeup_ROW_INDEX_GPIO(PDS_KEY_ROW_Type* row_index,PDS_KYS_GPIO_Type* row_gpio); +BL_Err_Type PDS_Get_KYS_Wakeup_COL_INDEX_GPIO(PDS_KEY_COL_Type* col_index,PDS_KYS_GPIO_Type* col_gpio); +BL_Err_Type PDS_Set_KYS_White_Key(uint8_t white_key_i ,PDS_KEY_ROW_Type row_index,PDS_KEY_COL_Type col_index,PDS_KYD_WHITE_KEY_MODE_Type type); +/*----------*/ + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_PDS_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_pm.h b/drivers/soc/bl702l/std/include/bl702l_pm.h new file mode 100644 index 000000000..f42747453 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_pm.h @@ -0,0 +1,64 @@ +#ifndef __BL702L_PM_H__ +#define __BL702L_PM_H__ + +#include "bl702l_common.h" + +enum pm_pds_sleep_level { + PM_PDS_LEVEL_31 = 31, +}; + +enum pm_hbn_sleep_level { + PM_HBN_LEVEL_0, + PM_HBN_LEVEL_1, + PM_HBN_LEVEL_2, +}; + +enum pm_event_type { + PM_HBN_WAKEUP_EVENT_NONE, + PM_HBN_GPIO9_WAKEUP_EVENT, + PM_HBN_GPIO10_WAKEUP_EVENT, + PM_HBN_GPIO11_WAKEUP_EVENT, + PM_HBN_GPIO12_WAKEUP_EVENT, + PM_HBN_RTC_WAKEUP_EVENT, + PM_HBN_BOR_WAKEUP_EVENT, + PM_HBN_ACOMP0_WAKEUP_EVENT, + PM_HBN_ACOMP1_WAKEUP_EVENT, +}; + +typedef struct +{ + uint8_t pdsLevel; /*!< PDS level */ + uint8_t turnOffRF; /*!< Wheather turn off RF */ + uint8_t powerDownFlash; /*!< Whether power down flash */ + uint8_t ocramRetetion; /*!< Whether OCRAM Retention */ + uint8_t turnoffPLL; /*!< Whether trun off PLL */ + uint8_t turnoffDLL; /*!< Whether trun off PLL */ + uint8_t flashContRead; /*!< Whether enable flash continue read */ + uint8_t ioKeepSel; /*!< PDS io keep select */ + uint8_t pdsLdoEn; /*!< Whether enable PDS control LDO */ + uint8_t fastRecovery; /*!< Whether enable fast recovery */ + uint32_t sleepTime; /*!< PDS sleep time */ + uint32_t *flashCfg; /*!< Flash config pointer, used when power down flash */ + uint32_t ldoLevel; /*!< LDO level */ + void (*preCbFun)(void); /*!< Pre callback function */ + void (*postCbFun)(void); /*!< Post callback function */ +} PM_PDS_CFG_Type; + +#ifdef __cplusplus +extern "C" { +#endif + +BL_Err_Type pm_pds_wakeup_src_en(uint32_t WakeupType); +void pm_pds_enable(uint32_t *cfg); +void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time); +void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint32_t sleep_time); +void pm_pds_io_wakeup_en(uint32_t pin,int trigMode, int pu, int pd); +void pm_hbn_io_wakeup_en(uint32_t pin,int trigMode, int pu, int pd); +BL_Err_Type pm_set_io_keep(uint32_t pin,uint32_t value); +uint32_t pm_acomp_wakeup_en(uint8_t acompNo, uint8_t pin, uint8_t pos_edge_en, uint8_t neg_edge_en); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/drivers/soc/bl702l/std/include/bl702l_romapi_patch.h b/drivers/soc/bl702l/std/include/bl702l_romapi_patch.h new file mode 100644 index 000000000..a59146169 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_romapi_patch.h @@ -0,0 +1,42 @@ +/** + ****************************************************************************** + * @file bl702l_romapi_patch.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_ROMAPI_PATCH_H__ +#define __BL702L_ROMAPI_PATCH_H__ + +#include "bflb_sflash.h" +#include "bflb_xip_sflash.h" + +#endif diff --git a/drivers/soc/bl702l/std/include/bl702l_romdriver.h b/drivers/soc/bl702l/std/include/bl702l_romdriver.h new file mode 100644 index 000000000..dbc0309cd --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_romdriver.h @@ -0,0 +1,2020 @@ +/** + ****************************************************************************** + * @file bl702l_romdriver.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_ROMDRIVER_H__ +#define __BL702L_ROMDRIVER_H__ + +#include "bl702l_aon.h" +#include "bl702l_clock.h" +#include "bl702l_common.h" +#include "bl702l_ef_cfg.h" +#include "bl702l_ef_ctrl.h" +#include "bl702l_glb.h" +#include "bl702l_glb_gpio.h" +#include "bl702l_hbn.h" +#include "bl702l_l1c.h" +#include "bl702l_pds.h" +// #include "bl702l_uart.h" +#include "bflb_sf_cfg.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sflash.h" +#include "bflb_xip_sflash.h" + +// #include "bl702l_ir.h" +// #include "bl702l_kys.h" +// #include "bl702l_psram.h" +// #include "bl702l_timer.h" + +// #include "misc.h" +// #include "softcrc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup ROMDRIVER + * @{ + */ + +/** @defgroup ROMDRIVER_Public_Types + * @{ + */ + +#define ROMAPI_INDEX_SECT_SIZE (0x800) +#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1) + +typedef enum { + ROM_API_INDEX_VERSION = 0, + ROM_API_INDEX_RSVD_0, + ROM_API_INDEX_RSVD_1, + ROM_API_INDEX_RSVD_LAST, + + + ROM_API_INDEX_AON_Power_On_MBG, + ROM_API_INDEX_AON_Power_Off_MBG, + ROM_API_INDEX_AON_Power_On_XTAL, + ROM_API_INDEX_AON_Set_Xtal_CapCode, + ROM_API_INDEX_AON_Get_Xtal_CapCode, + ROM_API_INDEX_AON_Set_Xtal_CapCode_Extra, + ROM_API_INDEX_AON_Power_Off_XTAL, + ROM_API_INDEX_AON_Power_On_BG, + ROM_API_INDEX_AON_Power_Off_BG, + ROM_API_INDEX_AON_Power_On_LDO11_SOC, + ROM_API_INDEX_AON_Power_Off_LDO11_SOC, + ROM_API_INDEX_AON_Power_On_SFReg, + ROM_API_INDEX_AON_Power_Off_SFReg, + ROM_API_INDEX_AON_Set_LDO11_SOC_Sstart_Delay, + ROM_API_INDEX_AON_Set_DCDC14_Top_0, + ROM_API_INDEX_AON_Trim_Ldo11socVoutTrim, + ROM_API_INDEX_AON_Trim_Ldo14VoutTrim, + ROM_API_INDEX_AON_Trim_Dcdc14VoutTrim, + + ROM_API_INDEX_Clock_System_Clock_Get, + ROM_API_INDEX_Clock_Peripheral_Clock_Get, + + ROM_API_INDEX_SystemCoreClockGet, + + ROM_API_INDEX_CPU_Get_MTimer_Clock, + ROM_API_INDEX_CPU_Get_MTimer_Counter, + ROM_API_INDEX_CPU_Get_CPU_Cycle, + ROM_API_INDEX_CPU_Get_MTimer_US, + ROM_API_INDEX_CPU_Get_MTimer_MS, + ROM_API_INDEX_CPU_MTimer_Delay_US, + ROM_API_INDEX_CPU_MTimer_Delay_MS, + + ROM_API_INDEX_BL702L_Delay_US, + ROM_API_INDEX_BL702L_Delay_MS, + + ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity, + ROM_API_INDEX_EF_Ctrl_Read_Common_Trim, + ROM_API_INDEX_EF_Ctrl_Write_Common_Trim, + ROM_API_INDEX_EF_Ctrl_Is_MAC_Address_Slot_Empty, + ROM_API_INDEX_EF_Ctrl_Write_MAC_Address_Opt, + ROM_API_INDEX_EF_Ctrl_Read_MAC_Address_Opt, + ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0, + ROM_API_INDEX_EF_Ctrl_Program_Efuse_0, + ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0, + ROM_API_INDEX_EF_Ctrl_Busy, + ROM_API_INDEX_EF_Ctrl_AutoLoad_Done, + ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd, + ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd, + ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd, + ROM_API_INDEX_EF_Ctrl_Writelock_Dbg_Pwd, + ROM_API_INDEX_EF_Ctrl_Write_Secure_Cfg, + ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg, + ROM_API_INDEX_EF_Ctrl_Write_Secure_Boot, + ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot, + ROM_API_INDEX_EF_Ctrl_Write_Sw_Usage, + ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage, + ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage, + ROM_API_INDEX_EF_Ctrl_Write_MAC_Address, + ROM_API_INDEX_EF_Ctrl_Get_Byte_Zero_Cnt, + ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero, + ROM_API_INDEX_EF_Ctrl_Read_MAC_Address, + ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address, + ROM_API_INDEX_EF_Ctrl_Read_Chip_ID, + ROM_API_INDEX_EF_Ctrl_Read_Device_Info, + ROM_API_INDEX_EF_Ctrl_Is_CapCode_Empty, + ROM_API_INDEX_EF_Ctrl_Write_CapCode_Opt, + ROM_API_INDEX_EF_Ctrl_Read_CapCode_Opt, + ROM_API_INDEX_EF_Ctrl_Is_PowerOffset_Slot_Empty, + ROM_API_INDEX_EF_Ctrl_Write_PowerOffset_Opt, + ROM_API_INDEX_EF_Ctrl_Read_PowerOffset_Opt, + ROM_API_INDEX_EF_Ctrl_Write_AES_Key, + ROM_API_INDEX_EF_Ctrl_Read_AES_Key, + ROM_API_INDEX_EF_Ctrl_Writelock_AES_Key, + ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key, + ROM_API_INDEX_EF_Ctrl_Program_Direct_R0, + ROM_API_INDEX_EF_Ctrl_Read_Direct_R0, + ROM_API_INDEX_EF_Ctrl_Clear, + ROM_API_INDEX_EF_Ctrl_Crc_Enable, + ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy, + ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden, + ROM_API_INDEX_EF_Ctrl_Crc_Result, + + ROM_API_INDEX_GLB_Get_Root_CLK_Sel, + ROM_API_INDEX_GLB_Set_System_CLK_Div, + ROM_API_INDEX_GLB_Get_BCLK_Div, + ROM_API_INDEX_GLB_Get_HCLK_Div, + ROM_API_INDEX_GLB_Set_System_CLK, + + ROM_API_INDEX_System_Core_Clock_Update_From_RC32M, + + ROM_API_INDEX_GLB_Set_MAC154_ZIGBEE_CLK, + ROM_API_INDEX_GLB_Set_BLE_CLK, + ROM_API_INDEX_GLB_Set_AUDIO_CLK, + ROM_API_INDEX_GLB_Set_KYS_CLK, + ROM_API_INDEX_GLB_Set_DMA_CLK, + ROM_API_INDEX_GLB_Set_IR_CLK, + ROM_API_INDEX_GLB_Set_SF_CLK, + ROM_API_INDEX_GLB_Set_UART_CLK, + ROM_API_INDEX_GLB_Sel_TMR_GPIO_Clock, + ROM_API_INDEX_GLB_Set_Chip_Out_0_CLK_Sel, + ROM_API_INDEX_GLB_Set_Chip_Out_1_CLK_Sel, + ROM_API_INDEX_GLB_Set_Chip_Out_0_CLK_Enable, + ROM_API_INDEX_GLB_Set_Chip_Out_1_CLK_Enable, + ROM_API_INDEX_GLB_Set_I2C_CLK, + ROM_API_INDEX_GLB_Set_SPI_CLK, + ROM_API_INDEX_GLB_Set_PKA_CLK_Sel, + ROM_API_INDEX_GLB_SW_System_Reset, + ROM_API_INDEX_GLB_SW_CPU_Reset, + ROM_API_INDEX_GLB_SW_POR_Reset, + ROM_API_INDEX_GLB_AHB_MCU_Software_Reset, + ROM_API_INDEX_GLB_Disrst_Set, + ROM_API_INDEX_GLB_MAC154_ZIGBEE_Reset, + ROM_API_INDEX_GLB_BLE_Reset, + ROM_API_INDEX_GLB_PER_Clock_Gate, + ROM_API_INDEX_GLB_PER_Clock_UnGate, + ROM_API_INDEX_GLB_Set_RTC_Mode, + ROM_API_INDEX_GLB_BMX_Init, + ROM_API_INDEX_GLB_BMX_Addr_Monitor_Enable, + ROM_API_INDEX_GLB_BMX_Addr_Monitor_Disable, + ROM_API_INDEX_GLB_BMX_BusErrResponse_Enable, + ROM_API_INDEX_GLB_BMX_BusErrResponse_Disable, + ROM_API_INDEX_GLB_BMX_Get_Status, + ROM_API_INDEX_GLB_BMX_Get_Err_Addr, + ROM_API_INDEX_GLB_BMX_BusErrClr_Set, + ROM_API_INDEX_GLB_Set_SRAM_PARM, + ROM_API_INDEX_GLB_Get_SRAM_PARM, + ROM_API_INDEX_GLB_Set_OCRAM_PARM, + ROM_API_INDEX_GLB_Get_OCRAM_PARM, + ROM_API_INDEX_GLB_Set_EM_Sel, + ROM_API_INDEX_GLB_Set_Kys_Drv_Col, + ROM_API_INDEX_GLB_GPIO_O_Latch_Mode_Set, + ROM_API_INDEX_GLB_JTAG_Sig_Swap_Set, + ROM_API_INDEX_GLB_CCI_Use_IO_0_1_2_7, + ROM_API_INDEX_GLB_CCI_Use_Jtag_Pin, + ROM_API_INDEX_GLB_Swap_SPI_0_MOSI_With_MISO, + ROM_API_INDEX_GLB_Set_SPI_0_ACT_MOD_Sel, + ROM_API_INDEX_GLB_Set_Flash_Scenario, + ROM_API_INDEX_GLB_Set_Embedded_FLash_IO_PARM, + ROM_API_INDEX_GLB_Set_MTimer_CLK, + ROM_API_INDEX_GLB_Set_ADC_CLK, + ROM_API_INDEX_GLB_Set_DIG_32K_CLK, + ROM_API_INDEX_GLB_SW_BLE_WAKEUP_REQ_Set, + ROM_API_INDEX_GLB_UART_Fun_Sel, + ROM_API_INDEX_GLB_Power_Off_DLL, + ROM_API_INDEX_GLB_Power_On_DLL, + ROM_API_INDEX_GLB_Enable_DLL_All_Clks, + ROM_API_INDEX_GLB_Enable_DLL_Clk, + ROM_API_INDEX_GLB_Disable_DLL_All_Clks, + ROM_API_INDEX_GLB_Disable_DLL_Clk, + ROM_API_INDEX_GLB_Set_Flash_Id_Value, + ROM_API_INDEX_GLB_Get_Flash_Id_Value, + ROM_API_INDEX_GLB_Trim_RC32M, + ROM_API_INDEX_GLB_Set_Xtal_Cnt32k_Process, + ROM_API_INDEX_GLB_Clear_Xtal_Cnt32k_Done, + ROM_API_INDEX_GLB_RC32K_Deg_Start, + ROM_API_INDEX_GLB_RC32K_Deg_End, + ROM_API_INDEX_GLB_RC32K_Deg_Enable, + ROM_API_INDEX_GLB_Xtal_Deg_Cnt_Limit_Set, + ROM_API_INDEX_GLB_IR_LED_Driver_Enable, + ROM_API_INDEX_GLB_IR_LED_Driver_Disable, + ROM_API_INDEX_GLB_IR_LED_Driver_Output_Enable, + ROM_API_INDEX_GLB_IR_LED_Driver_Output_Disable, + ROM_API_INDEX_GLB_IR_LED_Driver_Ibias, + ROM_API_INDEX_GLB_GPIO_Init, + ROM_API_INDEX_GLB_GPIO_Func_Init, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Mode_Set, + ROM_API_INDEX_GLB_GPIO_INPUT_Enable, + ROM_API_INDEX_GLB_GPIO_INPUT_Disable, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable, + ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable, + ROM_API_INDEX_GLB_GPIO_Set_HZ, + ROM_API_INDEX_GLB_GPIO_Get_Fun, + ROM_API_INDEX_GLB_GPIO_Write, + ROM_API_INDEX_GLB_GPIO_Read, + ROM_API_INDEX_GLB_GPIO_Set, + ROM_API_INDEX_GLB_GPIO_Clr, + ROM_API_INDEX_GLB_GPIO_IntMask, + ROM_API_INDEX_GLB_Clr_GPIO_IntStatus, + ROM_API_INDEX_GLB_Get_GPIO_IntStatus, + ROM_API_INDEX_GLB_GPIO_Int_Init, + + ROM_API_INDEX_HBN_Mode_Enter, + ROM_API_INDEX_HBN_GPIO_Wakeup_Set, + ROM_API_INDEX_HBN_Power_Down_Flash, + ROM_API_INDEX_HBN_Enable, + ROM_API_INDEX_HBN_Reset, + ROM_API_INDEX_HBN_App_Reset, + ROM_API_INDEX_HBN_Disable, + ROM_API_INDEX_HBN_Get_BOR_OUT_State, + ROM_API_INDEX_HBN_Set_BOR_Config, + ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout, + ROM_API_INDEX_HBN_Set_Ldo11_All_Vout, + ROM_API_INDEX_HBN_32K_Sel, + ROM_API_INDEX_HBN_Set_UART_CLK_Sel, + ROM_API_INDEX_HBN_Set_XCLK_CLK_Sel, + ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel, + ROM_API_INDEX_HBN_Set_HRAM_slp, + ROM_API_INDEX_HBN_Set_HRAM_Ret, + ROM_API_INDEX_HBN_Power_On_Xtal_32K, + ROM_API_INDEX_HBN_Power_Off_Xtal_32K, + ROM_API_INDEX_HBN_Power_On_RC32K, + ROM_API_INDEX_HBN_Power_Off_RC32K, + ROM_API_INDEX_HBN_Trim_RC32K, + ROM_API_INDEX_HBN_Get_Status_Flag, + ROM_API_INDEX_HBN_Set_Status_Flag, + ROM_API_INDEX_HBN_Get_Wakeup_Addr, + ROM_API_INDEX_HBN_Set_Wakeup_Addr, + ROM_API_INDEX_HBN_Get_User_Boot_Config, + ROM_API_INDEX_HBN_Set_User_Boot_Config, + ROM_API_INDEX_HBN_Clear_RTC_Counter, + ROM_API_INDEX_HBN_Enable_RTC_Counter, + ROM_API_INDEX_HBN_Set_RTC_Timer, + ROM_API_INDEX_HBN_Get_RTC_Timer_Val, + ROM_API_INDEX_HBN_Clear_RTC_INT, + ROM_API_INDEX_HBN_GPIO_INT_Enable, + ROM_API_INDEX_HBN_GPIO_INT_Disable, + ROM_API_INDEX_HBN_Get_INT_State, + ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode, + ROM_API_INDEX_HBN_Clear_IRQ, + ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg, + ROM_API_INDEX_HBN_Comm_Pad_Wakeup_En_Cfg, + ROM_API_INDEX_HBN_Aon_Pad_IeSmt_Cfg, + ROM_API_INDEX_HBN_Pin_WakeUp_Mask, + ROM_API_INDEX_HBN_Enable_AComp0_IRQ, + ROM_API_INDEX_HBN_Disable_AComp0_IRQ, + ROM_API_INDEX_HBN_Enable_AComp1_IRQ, + ROM_API_INDEX_HBN_Disable_AComp1_IRQ, + ROM_API_INDEX_HBN_Enable_BOR_IRQ, + ROM_API_INDEX_HBN_Disable_BOR_IRQ, + ROM_API_INDEX_HBN_Get_Reset_Event, + ROM_API_INDEX_HBN_Clear_Reset_Event, + ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg, + ROM_API_INDEX_HBN_Set_BOR_Cfg, + + ROM_API_INDEX_L1C_Cache_Write_Set, + ROM_API_INDEX_L1C_Cache_Enable_Set, + ROM_API_INDEX_L1C_Cache_Flush, + ROM_API_INDEX_L1C_Cache_Hit_Count_Get, + ROM_API_INDEX_L1C_Cache_Miss_Count_Get, + ROM_API_INDEX_L1C_Cache_Read_Disable, + ROM_API_INDEX_L1C_Set_Wrap, + ROM_API_INDEX_L1C_Set_Way_Disable, + ROM_API_INDEX_L1C_IROM_2T_Access_Set, + ROM_API_INDEX_L1C_BMX_Init, + ROM_API_INDEX_L1C_BMX_Addr_Monitor_Enable, + ROM_API_INDEX_L1C_BMX_Addr_Monitor_Disable, + ROM_API_INDEX_L1C_BMX_BusErrResponse_Enable, + ROM_API_INDEX_L1C_BMX_BusErrResponse_Disable, + ROM_API_INDEX_L1C_BMX_Get_Status, + ROM_API_INDEX_L1C_BMX_Get_Err_Addr, + + ROM_API_INDEX_PDS_Set_GPIO_Pad_Cfg, + ROM_API_INDEX_PDS_GPIO_Write, + ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask, + ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode, + ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr, + ROM_API_INDEX_PDS_Set_All_GPIO_IntClear, + ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus, + ROM_API_INDEX_PDS_Disable_GPIO_Keep, + ROM_API_INDEX_PDS_Enable, + ROM_API_INDEX_PDS_Force_Config, + ROM_API_INDEX_PDS_RAM_Config, + ROM_API_INDEX_PDS_Default_Level_Config, + ROM_API_INDEX_PDS_Wakeup_Src_En, + ROM_API_INDEX_PDS_Get_Wakeup_Src, + ROM_API_INDEX_PDS_IntMask, + ROM_API_INDEX_PDS_Get_IntStatus, + ROM_API_INDEX_PDS_IntClear, + ROM_API_INDEX_PDS_Get_PdsRfStstus, + ROM_API_INDEX_PDS_Get_PdsStstus, + ROM_API_INDEX_PDS_Clear_Reset_Event, + ROM_API_INDEX_PDS_Get_Reset_Event, + ROM_API_INDEX_PDS_Auto_Enable, + ROM_API_INDEX_PDS_Manual_Force_Turn_Off, + ROM_API_INDEX_PDS_Manual_Force_Turn_On, + ROM_API_INDEX_PDS_Set_KYD_Matrix_Size, + ROM_API_INDEX_PDS_Set_KYD_Col_Value, + ROM_API_INDEX_PDS_Set_KYD_Row_Pull, + ROM_API_INDEX_PDS_Set_KYD_Wakeup_En, + + ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock, + ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio, + ROM_API_INDEX_SF_Cfg_Flash_Identify, + ROM_API_INDEX_SF_Ctrl_Enable, + ROM_API_INDEX_SF_Ctrl_Psram_Init, + ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay, + ROM_API_INDEX_SF_Ctrl_Cmds_Set, + ROM_API_INDEX_SF_Ctrl_Burst_Toggle_Set, + ROM_API_INDEX_SF_Ctrl_Select_Pad, + ROM_API_INDEX_SF_Ctrl_Select_Bank, + ROM_API_INDEX_SF_Ctrl_Set_Owner, + ROM_API_INDEX_SF_Ctrl_Disable, + ROM_API_INDEX_SF_Ctrl_AES_Enable_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable_LE, + ROM_API_INDEX_SF_Ctrl_AES_Set_Region, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key, + ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV, + ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE, + ROM_API_INDEX_SF_Ctrl_AES_Enable, + ROM_API_INDEX_SF_Ctrl_AES_Disable, + ROM_API_INDEX_SF_Ctrl_Is_AES_Enable, + ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset, + ROM_API_INDEX_SF_Ctrl_SendCmd, + ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set, + ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set, + ROM_API_INDEX_SF_Ctrl_GetBusyState, + + ROM_API_INDEX_SFlash_Init, + ROM_API_INDEX_SFlash_SetSPIMode, + ROM_API_INDEX_SFlash_Read_Reg, + ROM_API_INDEX_SFlash_Write_Reg, + ROM_API_INDEX_SFlash_Read_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Write_Reg_With_Cmd, + ROM_API_INDEX_SFlash_Clear_Status_Register, + ROM_API_INDEX_SFlash_Busy, + ROM_API_INDEX_SFlash_Write_Enable, + ROM_API_INDEX_SFlash_Qspi_Enable, + ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable, + ROM_API_INDEX_SFlash_Chip_Erase, + ROM_API_INDEX_SFlash_Sector_Erase, + ROM_API_INDEX_SFlash_Blk32_Erase, + ROM_API_INDEX_SFlash_Blk64_Erase, + ROM_API_INDEX_SFlash_Erase, + ROM_API_INDEX_SFlash_Program, + ROM_API_INDEX_SFlash_GetUniqueId, + ROM_API_INDEX_SFlash_GetJedecId, + ROM_API_INDEX_SFlash_GetDeviceId, + ROM_API_INDEX_SFlash_Powerdown, + ROM_API_INDEX_SFlash_Releae_Powerdown, + ROM_API_INDEX_SFlash_Restore_From_Powerdown, + ROM_API_INDEX_SFlash_SetBurstWrap, + ROM_API_INDEX_SFlash_DisableBurstWrap, + ROM_API_INDEX_SFlash_Software_Reset, + ROM_API_INDEX_SFlash_Reset_Continue_Read, + ROM_API_INDEX_SFlash_Set_IDbus_Cfg, + ROM_API_INDEX_SFlash_IDbus_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Read_Enable, + ROM_API_INDEX_SFlash_Cache_Read_Disable, + ROM_API_INDEX_SFlash_Read, + + ROM_API_INDEX_UART_SetBaudRate, + ROM_API_INDEX_UART_Init, + ROM_API_INDEX_UART_DeInit, + ROM_API_INDEX_UART_FifoConfig, + ROM_API_INDEX_UART_Enable, + ROM_API_INDEX_UART_Disable, + ROM_API_INDEX_UART_SetTxDataLength, + ROM_API_INDEX_UART_SetRxDataLength, + ROM_API_INDEX_UART_SetRxTimeoutValue, + ROM_API_INDEX_UART_SetRxByteCount, + ROM_API_INDEX_UART_SetDeglitchCount, + ROM_API_INDEX_UART_ApplyAbrResult, + ROM_API_INDEX_UART_SetRtsValue, + ROM_API_INDEX_UART_ClrRtsValue, + ROM_API_INDEX_UART_SetTxValue, + ROM_API_INDEX_UART_ClrTxValue, + ROM_API_INDEX_UART_TxFreeRun, + ROM_API_INDEX_UART_AutoBaudDetection, + ROM_API_INDEX_UART_SetAllowableError0X55, + ROM_API_INDEX_UART_GetBitWidth0X55, + ROM_API_INDEX_UART_SetRS485, + ROM_API_INDEX_UART_TxFifoClear, + ROM_API_INDEX_UART_RxFifoClear, + ROM_API_INDEX_UART_IntMask, + ROM_API_INDEX_UART_IntClear, + ROM_API_INDEX_UART_SendData, + ROM_API_INDEX_UART_SendDataBlock, + ROM_API_INDEX_UART_ReceiveData, + ROM_API_INDEX_UART_GetAutoBaudCount, + ROM_API_INDEX_UART_GetRxByteCount, + ROM_API_INDEX_UART_GetTxFifoCount, + ROM_API_INDEX_UART_GetRxFifoCount, + ROM_API_INDEX_UART_GetIntStatus, + ROM_API_INDEX_UART_GetTxBusBusyStatus, + ROM_API_INDEX_UART_GetRxBusBusyStatus, + ROM_API_INDEX_UART_GetOverflowStatus, + + ROM_API_INDEX_XIP_SFlash_Opt_Enter, + ROM_API_INDEX_XIP_SFlash_Opt_Exit, + ROM_API_INDEX_XIP_SFlash_State_Save, + ROM_API_INDEX_XIP_SFlash_State_Restore, + ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Write_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock, + ROM_API_INDEX_XIP_SFlash_Clear_Status_Register_Need_Lock, + + ROM_API_INDEX_IR_TxInit, + ROM_API_INDEX_IR_TxPulseWidthConfig, + ROM_API_INDEX_IR_FifoConfig, + ROM_API_INDEX_IR_DeInit, + ROM_API_INDEX_IR_Enable, + ROM_API_INDEX_IR_Disable, + ROM_API_INDEX_IR_TxSWM, + ROM_API_INDEX_IR_TxFifoClear, + ROM_API_INDEX_IR_SendData, + ROM_API_INDEX_IR_SWMSendData, + ROM_API_INDEX_IR_SendCommand, + ROM_API_INDEX_IR_SWMSendCommand, + ROM_API_INDEX_IR_SendNEC, + ROM_API_INDEX_IR_IntMask, + ROM_API_INDEX_IR_ClrIntStatus, + ROM_API_INDEX_IR_GetIntStatus, + ROM_API_INDEX_IR_GetFifoStatus, + ROM_API_INDEX_IR_GetTxFifoCount, + ROM_API_INDEX_IR_LEDInit, + ROM_API_INDEX_IR_LEDSend, + + ROM_API_INDEX_KYS_Init, + ROM_API_INDEX_KYS_Enable, + ROM_API_INDEX_KYS_Disable, + ROM_API_INDEX_KYS_IntMask, + ROM_API_INDEX_KYS_IntClear, + ROM_API_INDEX_KYS_GetIntStatus, + ROM_API_INDEX_KYS_Get_FIFO_Idx, + ROM_API_INDEX_KYS_ReadKeyfifo, + + ROM_API_INDEX_Psram_Init, + ROM_API_INDEX_Psram_ReadReg, + ROM_API_INDEX_Psram_WriteReg, + ROM_API_INDEX_Psram_SetDriveStrength, + ROM_API_INDEX_Psram_SetBurstWrap, + ROM_API_INDEX_Psram_ReadId, + ROM_API_INDEX_Psram_EnterQuadMode, + ROM_API_INDEX_Psram_ExitQuadMode, + ROM_API_INDEX_Psram_ToggleBurstLength, + ROM_API_INDEX_Psram_SoftwareReset, + ROM_API_INDEX_Psram_Set_IDbus_Cfg, + ROM_API_INDEX_Psram_Cache_Write_Set, + ROM_API_INDEX_Psram_Write, + ROM_API_INDEX_Psram_Read, + + ROM_API_INDEX_TIMER_GetCompValue, + ROM_API_INDEX_TIMER_SetCompValue, + ROM_API_INDEX_TIMER_CompValueEffectImmediately, + ROM_API_INDEX_TIMER_GetCounterValue, + ROM_API_INDEX_TIMER_ResetCounterValue, + ROM_API_INDEX_TIMER_GetMatchStatus, + ROM_API_INDEX_TIMER_GetPreloadValue, + ROM_API_INDEX_TIMER_SetPreloadValue, + ROM_API_INDEX_TIMER_SetPreloadTrigSrc, + ROM_API_INDEX_TIMER_SetCountMode, + ROM_API_INDEX_TIMER_ClearIntStatus, + ROM_API_INDEX_TIMER_Init, + ROM_API_INDEX_TIMER_DeInit, + ROM_API_INDEX_TIMER_Enable, + ROM_API_INDEX_TIMER_Disable, + ROM_API_INDEX_TIMER_IntMask, + ROM_API_INDEX_TIMER_GPIOSetPolarity, + ROM_API_INDEX_TIMER_CH0_SetMeasurePulseWidth, + ROM_API_INDEX_TIMER_CH0_GetMeasurePulseWidth, + ROM_API_INDEX_TIMER_ForceClockDivision, + + ROM_API_INDEX_WDT_Set_Clock, + ROM_API_INDEX_WDT_GetMatchValue, + ROM_API_INDEX_WDT_SetCompValue, + ROM_API_INDEX_WDT_CompValueEffectImmediately, + ROM_API_INDEX_WDT_GetCounterValue, + ROM_API_INDEX_WDT_ResetCounterValue, + ROM_API_INDEX_WDT_GetResetStatus, + ROM_API_INDEX_WDT_ClearResetStatus, + ROM_API_INDEX_WDT_Enable, + ROM_API_INDEX_WDT_Disable, + ROM_API_INDEX_WDT_ForceClockDivision, + ROM_API_INDEX_WDT_IntMask, + ROM_API_INDEX_WDT_GPIOSetPolarity, + + ROM_API_INDEX_arch_memcpy, + ROM_API_INDEX_arch_memcpy4, + ROM_API_INDEX_arch_memcpy_fast, + ROM_API_INDEX_arch_memset, + ROM_API_INDEX_arch_memset4, + ROM_API_INDEX_arch_memcmp, + + ROM_API_INDEX_memcopy_to_fifo, + + ROM_API_INDEX_fifocopy_to_mem, + + ROM_API_INDEX_BFLB_Soft_CRC32_Ex, + ROM_API_INDEX_BFLB_Soft_CRC32, + + ROM_API_INDEX_FUNC_EMPTY_START, + + ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX + +} ROM_API_INDEX_e; + +/*@} end of group ROMDRIVER_Public_Types */ + +/** @defgroup ROMDRIVER_Public_Constants + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Constants */ + +/** @defgroup ROMDRIVER_Public_Macros + * @{ + */ + + +#define ROM_APITABLE ((uint32_t *)0x21010800) + + +#define RomDriver_AON_Power_On_MBG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG]) + +#define RomDriver_AON_Power_Off_MBG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG]) + +#define RomDriver_AON_Power_On_XTAL \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL]) + +#define RomDriver_AON_Set_Xtal_CapCode \ + ((BL_Err_Type (*) (uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode]) + +#define RomDriver_AON_Get_Xtal_CapCode \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode]) + +#define RomDriver_AON_Set_Xtal_CapCode_Extra \ + ((BL_Err_Type (*) (uint8_t extra))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode_Extra]) + +#define RomDriver_AON_Power_Off_XTAL \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL]) + +#define RomDriver_AON_Power_On_BG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG]) + +#define RomDriver_AON_Power_Off_BG \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG]) + +#define RomDriver_AON_Power_On_LDO11_SOC \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO11_SOC]) + +#define RomDriver_AON_Power_Off_LDO11_SOC \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO11_SOC]) + +#define RomDriver_AON_Power_On_SFReg \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg]) + +#define RomDriver_AON_Power_Off_SFReg \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg]) + +#define RomDriver_AON_Set_LDO11_SOC_Sstart_Delay \ + ((BL_Err_Type (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_AON_Set_LDO11_SOC_Sstart_Delay]) + +#define RomDriver_AON_Set_DCDC14_Top_0 \ + ((BL_Err_Type (*) (uint8_t voutSel, uint8_t vpfm))ROM_APITABLE[ROM_API_INDEX_AON_Set_DCDC14_Top_0]) + +#define RomDriver_AON_Trim_Ldo11socVoutTrim \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_Ldo11socVoutTrim]) + +#define RomDriver_AON_Trim_Ldo14VoutTrim \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_Ldo14VoutTrim]) + +#define RomDriver_AON_Trim_Dcdc14VoutTrim \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_Dcdc14VoutTrim]) + +#define RomDriver_Clock_System_Clock_Get \ + ((uint32_t (*) (BL_System_Clock_Type type))ROM_APITABLE[ROM_API_INDEX_Clock_System_Clock_Get]) + +#define RomDriver_Clock_Peripheral_Clock_Get \ + ((uint32_t (*) (BL_Peripheral_Type type))ROM_APITABLE[ROM_API_INDEX_Clock_Peripheral_Clock_Get]) + +#define RomDriver_SystemCoreClockGet \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SystemCoreClockGet]) + +#define RomDriver_CPU_Get_MTimer_Clock \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_Clock]) + +#define RomDriver_CPU_Get_MTimer_Counter \ + ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_Counter]) + +#define RomDriver_CPU_Get_CPU_Cycle \ + ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_CPU_Cycle]) + +#define RomDriver_CPU_Get_MTimer_US \ + ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_US]) + +#define RomDriver_CPU_Get_MTimer_MS \ + ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_MS]) + +#define RomDriver_CPU_MTimer_Delay_US \ + ((BL_Err_Type (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_CPU_MTimer_Delay_US]) + +#define RomDriver_CPU_MTimer_Delay_MS \ + ((BL_Err_Type (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_CPU_MTimer_Delay_MS]) + +#define RomDriver_BL702L_Delay_US \ + ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702L_Delay_US]) + +#define RomDriver_BL702L_Delay_MS \ + ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702L_Delay_MS]) + +#define RomDriver_EF_Ctrl_Get_Trim_Parity \ + ((uint8_t (*) (uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity]) + +#define RomDriver_EF_Ctrl_Read_Common_Trim \ + ((void (*) (char *name, Efuse_Common_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Common_Trim]) + +#define RomDriver_EF_Ctrl_Write_Common_Trim \ + ((void (*) (char *name, uint8_t trim_en, uint32_t trim_value))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Common_Trim]) + +#define RomDriver_EF_Ctrl_Is_MAC_Address_Slot_Empty \ + ((uint8_t (*) (uint8_t slot, uint8_t reload))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Is_MAC_Address_Slot_Empty]) + +#define RomDriver_EF_Ctrl_Write_MAC_Address_Opt \ + ((BL_Err_Type (*) (uint8_t slot, uint8_t mac[8], uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_MAC_Address_Opt]) + +#define RomDriver_EF_Ctrl_Read_MAC_Address_Opt \ + ((BL_Err_Type (*) (uint8_t slot, uint8_t mac[8], uint8_t reload))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_MAC_Address_Opt]) + +#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]) + +#define RomDriver_EF_Ctrl_Program_Efuse_0 \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0]) + +#define RomDriver_EF_Ctrl_Load_Efuse_R0 \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]) + +#define RomDriver_EF_Ctrl_Busy \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy]) + +#define RomDriver_EF_Ctrl_AutoLoad_Done \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done]) + +#define RomDriver_EF_Ctrl_Write_Dbg_Pwd \ + ((void (*) (uint32_t passWdLow, uint32_t passWdHigh, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd]) + +#define RomDriver_EF_Ctrl_Read_Dbg_Pwd \ + ((void (*) (uint32_t *passWdLow, uint32_t *passWdHigh))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd]) + +#define RomDriver_EF_Ctrl_Readlock_Dbg_Pwd \ + ((void (*) (uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd]) + +#define RomDriver_EF_Ctrl_Writelock_Dbg_Pwd \ + ((void (*) (uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_Dbg_Pwd]) + +#define RomDriver_EF_Ctrl_Write_Secure_Cfg \ + ((void (*) (EF_Ctrl_Sec_Param_Type *cfg, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Secure_Cfg]) + +#define RomDriver_EF_Ctrl_Read_Secure_Cfg \ + ((void (*) (EF_Ctrl_Sec_Param_Type *cfg))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg]) + +#define RomDriver_EF_Ctrl_Write_Secure_Boot \ + ((void (*) (uint8_t sign[1], uint8_t aes[1], uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Secure_Boot]) + +#define RomDriver_EF_Ctrl_Read_Secure_Boot \ + ((void (*) (uint8_t sign[1], uint8_t aes[1]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot]) + +#define RomDriver_EF_Ctrl_Write_Sw_Usage \ + ((void (*) (uint32_t index, uint32_t usage, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_Sw_Usage]) + +#define RomDriver_EF_Ctrl_Read_Sw_Usage \ + ((void (*) (uint32_t index, uint32_t *usage))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage]) + +#define RomDriver_EF_Ctrl_Writelock_Sw_Usage \ + ((void (*) (uint32_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage]) + +#define RomDriver_EF_Ctrl_Write_MAC_Address \ + ((void (*) (uint8_t mac[8], uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_MAC_Address]) + +#define RomDriver_EF_Ctrl_Get_Byte_Zero_Cnt \ + ((uint32_t (*) (uint8_t val))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Byte_Zero_Cnt]) + +#define RomDriver_EF_Ctrl_Is_All_Bits_Zero \ + ((uint8_t (*) (uint32_t val, uint8_t start, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero]) + +#define RomDriver_EF_Ctrl_Read_MAC_Address \ + ((BL_Err_Type (*) (uint8_t mac[8]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_MAC_Address]) + +#define RomDriver_EF_Ctrl_Writelock_MAC_Address \ + ((void (*) (uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address]) + +#define RomDriver_EF_Ctrl_Read_Chip_ID \ + ((BL_Err_Type (*) (uint8_t chipID[8]))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Chip_ID]) + +#define RomDriver_EF_Ctrl_Read_Device_Info \ + ((void (*) (Efuse_Device_Info_Type *deviceInfo))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Device_Info]) + +#define RomDriver_EF_Ctrl_Is_CapCode_Empty \ + ((uint8_t (*) (uint8_t slot, uint8_t reload))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Is_CapCode_Empty]) + +#define RomDriver_EF_Ctrl_Write_CapCode_Opt \ + ((BL_Err_Type (*) (uint8_t slot, uint8_t code, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_CapCode_Opt]) + +#define RomDriver_EF_Ctrl_Read_CapCode_Opt \ + ((BL_Err_Type (*) (uint8_t slot, uint8_t *code, uint8_t reload))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_CapCode_Opt]) + +#define RomDriver_EF_Ctrl_Is_PowerOffset_Slot_Empty \ + ((uint8_t (*) (uint8_t slot, uint8_t reload))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Is_PowerOffset_Slot_Empty]) + +#define RomDriver_EF_Ctrl_Write_PowerOffset_Opt \ + ((BL_Err_Type (*) (uint8_t slot, int8_t pwrOffset[2], uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_PowerOffset_Opt]) + +#define RomDriver_EF_Ctrl_Read_PowerOffset_Opt \ + ((BL_Err_Type (*) (uint8_t slot, int8_t pwrOffset[2], uint8_t reload))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_PowerOffset_Opt]) + +#define RomDriver_EF_Ctrl_Write_AES_Key \ + ((void (*) (uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_AES_Key]) + +#define RomDriver_EF_Ctrl_Read_AES_Key \ + ((void (*) (uint8_t index, uint32_t *keyData, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_AES_Key]) + +#define RomDriver_EF_Ctrl_Writelock_AES_Key \ + ((void (*) (uint8_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_AES_Key]) + +#define RomDriver_EF_Ctrl_Readlock_AES_Key \ + ((void (*) (uint8_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key]) + +#define RomDriver_EF_Ctrl_Program_Direct_R0 \ + ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct_R0]) + +#define RomDriver_EF_Ctrl_Read_Direct_R0 \ + ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct_R0]) + +#define RomDriver_EF_Ctrl_Clear \ + ((void (*) (uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear]) + +#define RomDriver_EF_Ctrl_Crc_Enable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Enable]) + +#define RomDriver_EF_Ctrl_Crc_Is_Busy \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy]) + +#define RomDriver_EF_Ctrl_Crc_Set_Golden \ + ((void (*) (uint32_t goldenValue))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden]) + +#define RomDriver_EF_Ctrl_Crc_Result \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Result]) + +#define RomDriver_GLB_Get_Root_CLK_Sel \ + ((GLB_ROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel]) + +#define RomDriver_GLB_Set_System_CLK_Div \ + ((BL_Err_Type (*) (uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div]) + +#define RomDriver_GLB_Get_BCLK_Div \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div]) + +#define RomDriver_GLB_Get_HCLK_Div \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div]) + +#define RomDriver_GLB_Set_System_CLK \ + ((BL_Err_Type (*) (GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK]) + +#define RomDriver_System_Core_Clock_Update_From_RC32M \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M]) + +#define RomDriver_GLB_Set_MAC154_ZIGBEE_CLK \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MAC154_ZIGBEE_CLK]) + +#define RomDriver_GLB_Set_BLE_CLK \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_BLE_CLK]) + +#define RomDriver_GLB_Set_AUDIO_CLK \ + ((BL_Err_Type (*) (uint8_t clkDivEn, uint8_t autoDivEn, GLB_AUDIO_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_AUDIO_CLK]) + +#define RomDriver_GLB_Set_KYS_CLK \ + ((BL_Err_Type (*) (GLB_KYS_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_KYS_CLK]) + +#define RomDriver_GLB_Set_DMA_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_DMA_CLK_ID_Type clk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DMA_CLK]) + +#define RomDriver_GLB_Set_IR_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_IR_CLK]) + +#define RomDriver_GLB_Set_SF_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK]) + +#define RomDriver_GLB_Set_UART_CLK \ + ((BL_Err_Type (*) (uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_UART_CLK]) + +#define RomDriver_GLB_Sel_TMR_GPIO_Clock \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Sel_TMR_GPIO_Clock]) + +#define RomDriver_GLB_Set_Chip_Out_0_CLK_Sel \ + ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_0_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Out_0_CLK_Sel]) + +#define RomDriver_GLB_Set_Chip_Out_1_CLK_Sel \ + ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_1_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Out_1_CLK_Sel]) + +#define RomDriver_GLB_Set_Chip_Out_0_CLK_Enable \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Out_0_CLK_Enable]) + +#define RomDriver_GLB_Set_Chip_Out_1_CLK_Enable \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Out_1_CLK_Enable]) + +#define RomDriver_GLB_Set_I2C_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_I2C_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_I2C_CLK]) + +#define RomDriver_GLB_Set_SPI_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_SPI_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SPI_CLK]) + +#define RomDriver_GLB_Set_PKA_CLK_Sel \ + ((BL_Err_Type (*) (GLB_PKA_CLK_SRC_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel]) + +#define RomDriver_GLB_SW_System_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset]) + +#define RomDriver_GLB_SW_CPU_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset]) + +#define RomDriver_GLB_SW_POR_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset]) + +#define RomDriver_GLB_AHB_MCU_Software_Reset \ + ((BL_Err_Type (*) (GLB_AHB_MCU_SW_Type swrst))ROM_APITABLE[ROM_API_INDEX_GLB_AHB_MCU_Software_Reset]) + +#define RomDriver_GLB_Disrst_Set \ + ((BL_Err_Type (*) (uint8_t enable, GLB_DISRST_Type disrst))ROM_APITABLE[ROM_API_INDEX_GLB_Disrst_Set]) + +#define RomDriver_GLB_MAC154_ZIGBEE_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_MAC154_ZIGBEE_Reset]) + +#define RomDriver_GLB_BLE_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_BLE_Reset]) + +#define RomDriver_GLB_PER_Clock_Gate \ + ((BL_Err_Type (*) (uint64_t ips))ROM_APITABLE[ROM_API_INDEX_GLB_PER_Clock_Gate]) + +#define RomDriver_GLB_PER_Clock_UnGate \ + ((BL_Err_Type (*) (uint64_t ips))ROM_APITABLE[ROM_API_INDEX_GLB_PER_Clock_UnGate]) + +#define RomDriver_GLB_Set_RTC_Mode \ + ((BL_Err_Type (*) (RTC_MODE_Type rtcMode))ROM_APITABLE[ROM_API_INDEX_GLB_Set_RTC_Mode]) + +#define RomDriver_GLB_BMX_Init \ + ((BL_Err_Type (*) (BMX_Cfg_Type *BmxCfg))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_Init]) + +#define RomDriver_GLB_BMX_Addr_Monitor_Enable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_Addr_Monitor_Enable]) + +#define RomDriver_GLB_BMX_Addr_Monitor_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_Addr_Monitor_Disable]) + +#define RomDriver_GLB_BMX_BusErrResponse_Enable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_BusErrResponse_Enable]) + +#define RomDriver_GLB_BMX_BusErrResponse_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_BusErrResponse_Disable]) + +#define RomDriver_GLB_BMX_Get_Status \ + ((BL_Sts_Type (*) (BMX_BUS_ERR_Type errType))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_Get_Status]) + +#define RomDriver_GLB_BMX_Get_Err_Addr \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_Get_Err_Addr]) + +#define RomDriver_GLB_BMX_BusErrClr_Set \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_BusErrClr_Set]) + +#define RomDriver_GLB_Set_SRAM_PARM \ + ((BL_Err_Type (*) (uint32_t value))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SRAM_PARM]) + +#define RomDriver_GLB_Get_SRAM_PARM \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_SRAM_PARM]) + +#define RomDriver_GLB_Set_OCRAM_PARM \ + ((BL_Err_Type (*) (uint32_t value))ROM_APITABLE[ROM_API_INDEX_GLB_Set_OCRAM_PARM]) + +#define RomDriver_GLB_Get_OCRAM_PARM \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_OCRAM_PARM]) + +#define RomDriver_GLB_Set_EM_Sel \ + ((BL_Err_Type (*) (GLB_EM_Type emType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EM_Sel]) + +#define RomDriver_GLB_Set_Kys_Drv_Col \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Kys_Drv_Col]) + +#define RomDriver_GLB_GPIO_O_Latch_Mode_Set \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_O_Latch_Mode_Set]) + +#define RomDriver_GLB_JTAG_Sig_Swap_Set \ + ((BL_Err_Type (*) (uint8_t swapSel))ROM_APITABLE[ROM_API_INDEX_GLB_JTAG_Sig_Swap_Set]) + +#define RomDriver_GLB_CCI_Use_IO_0_1_2_7 \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_CCI_Use_IO_0_1_2_7]) + +#define RomDriver_GLB_CCI_Use_Jtag_Pin \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_CCI_Use_Jtag_Pin]) + +#define RomDriver_GLB_Swap_SPI_0_MOSI_With_MISO \ + ((BL_Err_Type (*) (BL_Fun_Type newState))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_SPI_0_MOSI_With_MISO]) + +#define RomDriver_GLB_Set_SPI_0_ACT_MOD_Sel \ + ((BL_Err_Type (*) (GLB_SPI_PAD_ACT_AS_Type mod))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SPI_0_ACT_MOD_Sel]) + +#define RomDriver_GLB_Set_Flash_Scenario \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Flash_Scenario]) + +#define RomDriver_GLB_Set_Embedded_FLash_IO_PARM \ + ((BL_Err_Type (*) (uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Embedded_FLash_IO_PARM]) + +#define RomDriver_GLB_Set_MTimer_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MTimer_CLK]) + +#define RomDriver_GLB_Set_ADC_CLK \ + ((BL_Err_Type (*) (uint8_t enable, GLB_ADC_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_ADC_CLK]) + +#define RomDriver_GLB_Set_DIG_32K_CLK \ + ((BL_Err_Type (*) (uint8_t enable, uint8_t compensation, GLB_DIG_CLK_SRC_Type clkSel, uint16_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DIG_32K_CLK]) + +#define RomDriver_GLB_SW_BLE_WAKEUP_REQ_Set \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_SW_BLE_WAKEUP_REQ_Set]) + +#define RomDriver_GLB_UART_Fun_Sel \ + ((BL_Err_Type (*) (GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun))ROM_APITABLE[ROM_API_INDEX_GLB_UART_Fun_Sel]) + +#define RomDriver_GLB_Power_Off_DLL \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_DLL]) + +#define RomDriver_GLB_Power_On_DLL \ + ((BL_Err_Type (*) (GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_DLL]) + +#define RomDriver_GLB_Enable_DLL_All_Clks \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_All_Clks]) + +#define RomDriver_GLB_Enable_DLL_Clk \ + ((BL_Err_Type (*) (GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_Clk]) + +#define RomDriver_GLB_Disable_DLL_All_Clks \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_All_Clks]) + +#define RomDriver_GLB_Disable_DLL_Clk \ + ((BL_Err_Type (*) (GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_Clk]) + +#define RomDriver_GLB_Set_Flash_Id_Value \ + ((BL_Err_Type (*) (uint32_t idValue))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Flash_Id_Value]) + +#define RomDriver_GLB_Get_Flash_Id_Value \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Flash_Id_Value]) + +#define RomDriver_GLB_Trim_RC32M \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_RC32M]) + +#define RomDriver_GLB_Set_Xtal_Cnt32k_Process \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Xtal_Cnt32k_Process]) + +#define RomDriver_GLB_Clear_Xtal_Cnt32k_Done \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Clear_Xtal_Cnt32k_Done]) + +#define RomDriver_GLB_RC32K_Deg_Start \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_RC32K_Deg_Start]) + +#define RomDriver_GLB_RC32K_Deg_End \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_RC32K_Deg_End]) + +#define RomDriver_GLB_RC32K_Deg_Enable \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_RC32K_Deg_Enable]) + +#define RomDriver_GLB_Xtal_Deg_Cnt_Limit_Set \ + ((BL_Err_Type (*) (uint8_t cnt))ROM_APITABLE[ROM_API_INDEX_GLB_Xtal_Deg_Cnt_Limit_Set]) + +#define RomDriver_GLB_IR_LED_Driver_Enable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Enable]) + +#define RomDriver_GLB_IR_LED_Driver_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Disable]) + +#define RomDriver_GLB_IR_LED_Driver_Output_Enable \ + ((BL_Err_Type (*) (GLB_IR_LED_Type led))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Output_Enable]) + +#define RomDriver_GLB_IR_LED_Driver_Output_Disable \ + ((BL_Err_Type (*) (GLB_IR_LED_Type led))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Output_Disable]) + +#define RomDriver_GLB_IR_LED_Driver_Ibias \ + ((BL_Err_Type (*) (uint8_t ibias))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Ibias]) + +#define RomDriver_GLB_GPIO_Init \ + ((BL_Err_Type (*) (GLB_GPIO_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init]) + +#define RomDriver_GLB_GPIO_Func_Init \ + ((BL_Err_Type (*) (GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Func_Init]) + +#define RomDriver_GLB_GPIO_OUTPUT_Mode_Set \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin, GLB_GPIO_OUTPUT_MODE_Type mode))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Mode_Set]) + +#define RomDriver_GLB_GPIO_INPUT_Enable \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_INPUT_Enable]) + +#define RomDriver_GLB_GPIO_INPUT_Disable \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_INPUT_Disable]) + +#define RomDriver_GLB_GPIO_OUTPUT_Enable \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable]) + +#define RomDriver_GLB_GPIO_OUTPUT_Disable \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable]) + +#define RomDriver_GLB_GPIO_Set_HZ \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ]) + +#define RomDriver_GLB_GPIO_Get_Fun \ + ((uint8_t (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun]) + +#define RomDriver_GLB_GPIO_Write \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin, uint32_t val))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Write]) + +#define RomDriver_GLB_GPIO_Read \ + ((uint32_t (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Read]) + +#define RomDriver_GLB_GPIO_Set \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set]) + +#define RomDriver_GLB_GPIO_Clr \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Clr]) + +#define RomDriver_GLB_GPIO_IntMask \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_IntMask]) + +#define RomDriver_GLB_Clr_GPIO_IntStatus \ + ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_GPIO_IntStatus]) + +#define RomDriver_GLB_Get_GPIO_IntStatus \ + ((BL_Sts_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Get_GPIO_IntStatus]) + +#define RomDriver_GLB_GPIO_Int_Init \ + ((BL_Err_Type (*) (GLB_GPIO_INT_Cfg_Type *intCfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Int_Init]) + +#define RomDriver_HBN_Mode_Enter \ + ((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter]) + +#define RomDriver_HBN_GPIO_Wakeup_Set \ + ((void (*) (uint16_t gpio_wakeup_src, HBN_GPIO_INT_Trigger_Type gpio_trig_type))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_Wakeup_Set]) + +#define RomDriver_HBN_Power_Down_Flash \ + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) + +#define RomDriver_HBN_Enable \ + ((void (*) (HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable]) + +#define RomDriver_HBN_Reset \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset]) + +#define RomDriver_HBN_App_Reset \ + ((BL_Err_Type (*) (uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv))ROM_APITABLE[ROM_API_INDEX_HBN_App_Reset]) + +#define RomDriver_HBN_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Disable]) + +#define RomDriver_HBN_Get_BOR_OUT_State \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_BOR_OUT_State]) + +#define RomDriver_HBN_Set_BOR_Config \ + ((BL_Err_Type (*) (uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode))ROM_APITABLE[ROM_API_INDEX_HBN_Set_BOR_Config]) + +#define RomDriver_HBN_Set_Ldo11_Aon_Vout \ + ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout]) + +#define RomDriver_HBN_Set_Ldo11_Soc_Vout \ + ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout]) + +#define RomDriver_HBN_Set_Ldo11_All_Vout \ + ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_All_Vout]) + +#define RomDriver_HBN_32K_Sel \ + ((BL_Err_Type (*) (HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel]) + +#define RomDriver_HBN_Set_UART_CLK_Sel \ + ((BL_Err_Type (*) (HBN_UART_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_UART_CLK_Sel]) + +#define RomDriver_HBN_Set_XCLK_CLK_Sel \ + ((BL_Err_Type (*) (HBN_XCLK_CLK_Type xClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_XCLK_CLK_Sel]) + +#define RomDriver_HBN_Set_ROOT_CLK_Sel \ + ((BL_Err_Type (*) (HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]) + +#define RomDriver_HBN_Set_HRAM_slp \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Set_HRAM_slp]) + +#define RomDriver_HBN_Set_HRAM_Ret \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Set_HRAM_Ret]) + +#define RomDriver_HBN_Power_On_Xtal_32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K]) + +#define RomDriver_HBN_Power_Off_Xtal_32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K]) + +#define RomDriver_HBN_Power_On_RC32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K]) + +#define RomDriver_HBN_Power_Off_RC32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K]) + +#define RomDriver_HBN_Trim_RC32K \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K]) + +#define RomDriver_HBN_Get_Status_Flag \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Status_Flag]) + +#define RomDriver_HBN_Set_Status_Flag \ + ((BL_Err_Type (*) (uint32_t flag))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Status_Flag]) + +#define RomDriver_HBN_Get_Wakeup_Addr \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Wakeup_Addr]) + +#define RomDriver_HBN_Set_Wakeup_Addr \ + ((BL_Err_Type (*) (uint32_t addr))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Wakeup_Addr]) + +#define RomDriver_HBN_Get_User_Boot_Config \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_User_Boot_Config]) + +#define RomDriver_HBN_Set_User_Boot_Config \ + ((BL_Err_Type (*) (uint8_t ubCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_User_Boot_Config]) + +#define RomDriver_HBN_Clear_RTC_Counter \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_RTC_Counter]) + +#define RomDriver_HBN_Enable_RTC_Counter \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_RTC_Counter]) + +#define RomDriver_HBN_Set_RTC_Timer \ + ((BL_Err_Type (*) (HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode))ROM_APITABLE[ROM_API_INDEX_HBN_Set_RTC_Timer]) + +#define RomDriver_HBN_Get_RTC_Timer_Val \ + ((BL_Err_Type (*) (uint32_t *valLow, uint32_t *valHigh))ROM_APITABLE[ROM_API_INDEX_HBN_Get_RTC_Timer_Val]) + +#define RomDriver_HBN_Clear_RTC_INT \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_RTC_INT]) + +#define RomDriver_HBN_GPIO_INT_Enable \ + ((BL_Err_Type (*) (HBN_GPIO_INT_Trigger_Type gpioIntTrigType))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_INT_Enable]) + +#define RomDriver_HBN_GPIO_INT_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_INT_Disable]) + +#define RomDriver_HBN_Get_INT_State \ + ((BL_Sts_Type (*) (HBN_INT_Type irqType))ROM_APITABLE[ROM_API_INDEX_HBN_Get_INT_State]) + +#define RomDriver_HBN_Get_Pin_Wakeup_Mode \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode]) + +#define RomDriver_HBN_Clear_IRQ \ + ((BL_Err_Type (*) (HBN_INT_Type irqType))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_IRQ]) + +#define RomDriver_HBN_Hw_Pu_Pd_Cfg \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg]) + +#define RomDriver_HBN_Comm_Pad_Wakeup_En_Cfg \ + ((BL_Err_Type (*) (uint8_t padCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Comm_Pad_Wakeup_En_Cfg]) + +#define RomDriver_HBN_Aon_Pad_IeSmt_Cfg \ + ((BL_Err_Type (*) (uint8_t padCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_IeSmt_Cfg]) + +#define RomDriver_HBN_Pin_WakeUp_Mask \ + ((BL_Err_Type (*) (uint16_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask]) + +#define RomDriver_HBN_Enable_AComp0_IRQ \ + ((BL_Err_Type (*) (HBN_ACOMP_INT_EDGE_Type edge))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_AComp0_IRQ]) + +#define RomDriver_HBN_Disable_AComp0_IRQ \ + ((BL_Err_Type (*) (HBN_ACOMP_INT_EDGE_Type edge))ROM_APITABLE[ROM_API_INDEX_HBN_Disable_AComp0_IRQ]) + +#define RomDriver_HBN_Enable_AComp1_IRQ \ + ((BL_Err_Type (*) (HBN_ACOMP_INT_EDGE_Type edge))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_AComp1_IRQ]) + +#define RomDriver_HBN_Disable_AComp1_IRQ \ + ((BL_Err_Type (*) (HBN_ACOMP_INT_EDGE_Type edge))ROM_APITABLE[ROM_API_INDEX_HBN_Disable_AComp1_IRQ]) + +#define RomDriver_HBN_Enable_BOR_IRQ \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Enable_BOR_IRQ]) + +#define RomDriver_HBN_Disable_BOR_IRQ \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Disable_BOR_IRQ]) + +#define RomDriver_HBN_Get_Reset_Event \ + ((BL_Sts_Type (*) (HBN_RST_EVENT_Type event))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Reset_Event]) + +#define RomDriver_HBN_Clear_Reset_Event \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_Reset_Event]) + +#define RomDriver_HBN_GPIO_Dbg_Pull_Cfg \ + ((BL_Err_Type (*) (BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg]) + +#define RomDriver_HBN_Set_BOR_Cfg \ + ((BL_Err_Type (*) (HBN_BOR_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_BOR_Cfg]) + +#define RomDriver_L1C_Cache_Write_Set \ + ((void (*) (BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Write_Set]) + +#define RomDriver_L1C_Cache_Enable_Set \ + ((BL_Err_Type (*) (uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Enable_Set]) + +#define RomDriver_L1C_Cache_Flush \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Flush]) + +#define RomDriver_L1C_Cache_Hit_Count_Get \ + ((void (*) (uint32_t *hitCountLow, uint32_t *hitCountHigh))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Hit_Count_Get]) + +#define RomDriver_L1C_Cache_Miss_Count_Get \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Miss_Count_Get]) + +#define RomDriver_L1C_Cache_Read_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Read_Disable]) + +#define RomDriver_L1C_Set_Wrap \ + ((BL_Err_Type (*) (BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap]) + +#define RomDriver_L1C_Set_Way_Disable \ + ((BL_Err_Type (*) (uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable]) + +#define RomDriver_L1C_IROM_2T_Access_Set \ + ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set]) + +#define RomDriver_L1C_BMX_Init \ + ((BL_Err_Type (*) (L1C_BMX_Cfg_Type *l1cBmxCfg))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_Init]) + +#define RomDriver_L1C_BMX_Addr_Monitor_Enable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_Addr_Monitor_Enable]) + +#define RomDriver_L1C_BMX_Addr_Monitor_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_Addr_Monitor_Disable]) + +#define RomDriver_L1C_BMX_BusErrResponse_Enable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_BusErrResponse_Enable]) + +#define RomDriver_L1C_BMX_BusErrResponse_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_BusErrResponse_Disable]) + +#define RomDriver_L1C_BMX_Get_Status \ + ((BL_Sts_Type (*) (L1C_BMX_BUS_ERR_Type errType))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_Get_Status]) + +#define RomDriver_L1C_BMX_Get_Err_Addr \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_BMX_Get_Err_Addr]) + +#define RomDriver_PDS_Set_GPIO_Pad_Cfg \ + ((BL_Err_Type (*) (PDS_GPIO_Type pin, PDS_GPIO_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_Cfg]) + +#define RomDriver_PDS_GPIO_Write \ + ((BL_Err_Type (*) (PDS_GPIO_GROUP_SET_Type grp, uint32_t val))ROM_APITABLE[ROM_API_INDEX_PDS_GPIO_Write]) + +#define RomDriver_PDS_Set_GPIO_Pad_IntMask \ + ((BL_Err_Type (*) (PDS_GPIO_GROUP_SET_Type grp, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask]) + +#define RomDriver_PDS_Set_GPIO_Pad_IntMode \ + ((BL_Err_Type (*) (PDS_GPIO_GROUP_SET_Type grp, PDS_GPIO_INT_TRIG_Type trig))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode]) + +#define RomDriver_PDS_Set_GPIO_Pad_IntClr \ + ((BL_Err_Type (*) (PDS_GPIO_GROUP_SET_Type grp))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr]) + +#define RomDriver_PDS_Set_All_GPIO_IntClear \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_All_GPIO_IntClear]) + +#define RomDriver_PDS_Get_GPIO_Pad_IntStatus \ + ((BL_Sts_Type (*) (PDS_GPIO_Type pin))ROM_APITABLE[ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus]) + +#define RomDriver_PDS_Disable_GPIO_Keep \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_GPIO_Keep]) + +#define RomDriver_PDS_Enable \ + ((BL_Err_Type (*) (PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Enable]) + +#define RomDriver_PDS_Force_Config \ + ((BL_Err_Type (*) (PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3))ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config]) + +#define RomDriver_PDS_RAM_Config \ + ((BL_Err_Type (*) (PDS_RAM_CFG_Type *ramCfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config]) + +#define RomDriver_PDS_Default_Level_Config \ + ((BL_Err_Type (*) (PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config]) + +#define RomDriver_PDS_Wakeup_Src_En \ + ((BL_Err_Type (*) (PDS_WAKEUP_SRC_Type intType, BL_Fun_Type enable))ROM_APITABLE[ROM_API_INDEX_PDS_Wakeup_Src_En]) + +#define RomDriver_PDS_Get_Wakeup_Src \ + ((BL_Sts_Type (*) (PDS_WAKEUP_SRC_Type intType))ROM_APITABLE[ROM_API_INDEX_PDS_Get_Wakeup_Src]) + +#define RomDriver_PDS_IntMask \ + ((BL_Err_Type (*) (PDS_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_PDS_IntMask]) + +#define RomDriver_PDS_Get_IntStatus \ + ((BL_Sts_Type (*) (PDS_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_PDS_Get_IntStatus]) + +#define RomDriver_PDS_IntClear \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_IntClear]) + +#define RomDriver_PDS_Get_PdsRfStstus \ + ((PDS_RF_STS_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Get_PdsRfStstus]) + +#define RomDriver_PDS_Get_PdsStstus \ + ((PDS_STS_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Get_PdsStstus]) + +#define RomDriver_PDS_Clear_Reset_Event \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Clear_Reset_Event]) + +#define RomDriver_PDS_Get_Reset_Event \ + ((BL_Sts_Type (*) (PDS_RST_EVENT_Type event))ROM_APITABLE[ROM_API_INDEX_PDS_Get_Reset_Event]) + +#define RomDriver_PDS_Auto_Enable \ + ((void (*) (PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable))ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Enable]) + +#define RomDriver_PDS_Manual_Force_Turn_Off \ + ((void (*) (PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_Off]) + +#define RomDriver_PDS_Manual_Force_Turn_On \ + ((void (*) (PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_On]) + +#define RomDriver_PDS_Set_KYD_Matrix_Size \ + ((BL_Err_Type (*) (uint8_t col_size, uint8_t row_size))ROM_APITABLE[ROM_API_INDEX_PDS_Set_KYD_Matrix_Size]) + +#define RomDriver_PDS_Set_KYD_Col_Value \ + ((BL_Err_Type (*) (uint8_t val))ROM_APITABLE[ROM_API_INDEX_PDS_Set_KYD_Col_Value]) + +#define RomDriver_PDS_Set_KYD_Row_Pull \ + ((BL_Err_Type (*) (uint8_t en))ROM_APITABLE[ROM_API_INDEX_PDS_Set_KYD_Row_Pull]) + +#define RomDriver_PDS_Set_KYD_Wakeup_En \ + ((BL_Err_Type (*) (uint8_t en))ROM_APITABLE[ROM_API_INDEX_PDS_Set_KYD_Wakeup_En]) + +#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ + ((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ + ((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ + ((BL_Err_Type (*) (uint32_t flashID, spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + +#define RomDriver_SF_Cfg_Init_Flash_Gpio \ + ((int (*) (uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) + +#define RomDriver_SF_Cfg_Flash_Identify \ + ((uint32_t (*) (uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + +#define RomDriver_SF_Ctrl_Enable \ + ((void (*) (const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + +#define RomDriver_SF_Ctrl_Psram_Init \ + ((void (*) (struct sf_ctrl_psram_cfg *sfCtrlPsramCfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init]) + +#define RomDriver_SF_Ctrl_Get_Clock_Delay \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) + +#define RomDriver_SF_Ctrl_Set_Clock_Delay \ + ((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) + +#define RomDriver_SF_Ctrl_Cmds_Set \ + ((void (*) (struct sf_ctrl_cmds_cfg *cmdsCfg, uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set]) + +#define RomDriver_SF_Ctrl_Burst_Toggle_Set \ + ((void (*) (uint8_t burstToggleEn, uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Burst_Toggle_Set]) + +#define RomDriver_SF_Ctrl_Select_Pad \ + ((void (*) (uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + +#define RomDriver_SF_Ctrl_Select_Bank \ + ((void (*) (uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank]) + +#define RomDriver_SF_Ctrl_Set_Owner \ + ((void (*) (uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + +#define RomDriver_SF_Ctrl_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) + +#define RomDriver_SF_Ctrl_AES_Enable_BE \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable_LE \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE]) + +#define RomDriver_SF_Ctrl_AES_Set_Region \ + ((void (*) (uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) + +#define RomDriver_SF_Ctrl_AES_Set_Key \ + ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + +#define RomDriver_SF_Ctrl_AES_Set_Key_BE \ + ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + +#define RomDriver_SF_Ctrl_AES_Set_IV \ + ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) + +#define RomDriver_SF_Ctrl_AES_Set_IV_BE \ + ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]) + +#define RomDriver_SF_Ctrl_AES_Enable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable]) + +#define RomDriver_SF_Ctrl_AES_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable]) + +#define RomDriver_SF_Ctrl_Is_AES_Enable \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) + +#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \ + ((void (*) (uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ + ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) + +#define RomDriver_SF_Ctrl_SendCmd \ + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + +#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \ + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]) + +#define RomDriver_SF_Ctrl_Psram_Write_Icache_Set \ + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set]) + +#define RomDriver_SF_Ctrl_Psram_Read_Icache_Set \ + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set]) + +#define RomDriver_SF_Ctrl_GetBusyState \ + ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) + +#define RomDriver_SFlash_Init \ + ((void (*) (const struct sf_ctrl_cfg_type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + +#define RomDriver_SFlash_SetSPIMode \ + ((BL_Err_Type (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + +#define RomDriver_SFlash_Read_Reg \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + +#define RomDriver_SFlash_Write_Reg \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + +#define RomDriver_SFlash_Read_Reg_With_Cmd \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + +#define RomDriver_SFlash_Write_Reg_With_Cmd \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + +#define RomDriver_SFlash_Clear_Status_Register \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Clear_Status_Register]) + +#define RomDriver_SFlash_Busy \ + ((BL_Sts_Type (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + +#define RomDriver_SFlash_Write_Enable \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + +#define RomDriver_SFlash_Qspi_Enable \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + +#define RomDriver_SFlash_Volatile_Reg_Write_Enable \ + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + +#define RomDriver_SFlash_Chip_Erase \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + +#define RomDriver_SFlash_Sector_Erase \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + +#define RomDriver_SFlash_Blk32_Erase \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + +#define RomDriver_SFlash_Blk64_Erase \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + +#define RomDriver_SFlash_Erase \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + +#define RomDriver_SFlash_Program \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + +#define RomDriver_SFlash_GetUniqueId \ + ((void (*) (uint8_t *data, uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) + +#define RomDriver_SFlash_GetJedecId \ + ((void (*) (spi_flash_cfg_type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + +#define RomDriver_SFlash_GetDeviceId \ + ((void (*) (uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) + +#define RomDriver_SFlash_Powerdown \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) + +#define RomDriver_SFlash_Releae_Powerdown \ + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) + +#define RomDriver_SFlash_Restore_From_Powerdown \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t flashContRead))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + +#define RomDriver_SFlash_SetBurstWrap \ + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + +#define RomDriver_SFlash_DisableBurstWrap \ + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + +#define RomDriver_SFlash_Software_Reset \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + +#define RomDriver_SFlash_Reset_Continue_Read \ + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + +#define RomDriver_SFlash_Set_IDbus_Cfg \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + +#define RomDriver_SFlash_IDbus_Read_Enable \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + +#define RomDriver_SFlash_Cache_Read_Enable \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) + +#define RomDriver_SFlash_Cache_Read_Disable \ + ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) + +#define RomDriver_SFlash_Read \ + ((BL_Err_Type (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + +#define RomDriver_UART_SetBaudRate \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint32_t baudRate))ROM_APITABLE[ROM_API_INDEX_UART_SetBaudRate]) + +#define RomDriver_UART_Init \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_CFG_Type *uartCfg))ROM_APITABLE[ROM_API_INDEX_UART_Init]) + +#define RomDriver_UART_DeInit \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_DeInit]) + +#define RomDriver_UART_FifoConfig \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg))ROM_APITABLE[ROM_API_INDEX_UART_FifoConfig]) + +#define RomDriver_UART_Enable \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_Direction_Type direct))ROM_APITABLE[ROM_API_INDEX_UART_Enable]) + +#define RomDriver_UART_Disable \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_Direction_Type direct))ROM_APITABLE[ROM_API_INDEX_UART_Disable]) + +#define RomDriver_UART_SetTxDataLength \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t length))ROM_APITABLE[ROM_API_INDEX_UART_SetTxDataLength]) + +#define RomDriver_UART_SetRxDataLength \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t length))ROM_APITABLE[ROM_API_INDEX_UART_SetRxDataLength]) + +#define RomDriver_UART_SetRxTimeoutValue \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t time))ROM_APITABLE[ROM_API_INDEX_UART_SetRxTimeoutValue]) + +#define RomDriver_UART_SetRxByteCount \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t count))ROM_APITABLE[ROM_API_INDEX_UART_SetRxByteCount]) + +#define RomDriver_UART_SetDeglitchCount \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t deglitchCnt))ROM_APITABLE[ROM_API_INDEX_UART_SetDeglitchCount]) + +#define RomDriver_UART_ApplyAbrResult \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet))ROM_APITABLE[ROM_API_INDEX_UART_ApplyAbrResult]) + +#define RomDriver_UART_SetRtsValue \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_SetRtsValue]) + +#define RomDriver_UART_ClrRtsValue \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_ClrRtsValue]) + +#define RomDriver_UART_SetTxValue \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_SetTxValue]) + +#define RomDriver_UART_ClrTxValue \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_ClrTxValue]) + +#define RomDriver_UART_TxFreeRun \ + ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type txFreeRun))ROM_APITABLE[ROM_API_INDEX_UART_TxFreeRun]) + +#define RomDriver_UART_AutoBaudDetection \ + ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type autoBaud))ROM_APITABLE[ROM_API_INDEX_UART_AutoBaudDetection]) + +#define RomDriver_UART_SetAllowableError0X55 \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t allowableError))ROM_APITABLE[ROM_API_INDEX_UART_SetAllowableError0X55]) + +#define RomDriver_UART_GetBitWidth0X55 \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint16_t *width))ROM_APITABLE[ROM_API_INDEX_UART_GetBitWidth0X55]) + +#define RomDriver_UART_SetRS485 \ + ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity))ROM_APITABLE[ROM_API_INDEX_UART_SetRS485]) + +#define RomDriver_UART_TxFifoClear \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_TxFifoClear]) + +#define RomDriver_UART_RxFifoClear \ + ((BL_Err_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_RxFifoClear]) + +#define RomDriver_UART_IntMask \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_UART_IntMask]) + +#define RomDriver_UART_IntClear \ + ((BL_Err_Type (*) (UART_ID_Type uartId, UART_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_UART_IntClear]) + +#define RomDriver_UART_SendData \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_UART_SendData]) + +#define RomDriver_UART_SendDataBlock \ + ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_UART_SendDataBlock]) + +#define RomDriver_UART_ReceiveData \ + ((uint32_t (*) (UART_ID_Type uartId, uint8_t *data, uint32_t maxLen))ROM_APITABLE[ROM_API_INDEX_UART_ReceiveData]) + +#define RomDriver_UART_GetAutoBaudCount \ + ((uint16_t (*) (UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet))ROM_APITABLE[ROM_API_INDEX_UART_GetAutoBaudCount]) + +#define RomDriver_UART_GetRxByteCount \ + ((uint16_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetRxByteCount]) + +#define RomDriver_UART_GetTxFifoCount \ + ((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxFifoCount]) + +#define RomDriver_UART_GetRxFifoCount \ + ((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetRxFifoCount]) + +#define RomDriver_UART_GetIntStatus \ + ((BL_Sts_Type (*) (UART_ID_Type uartId, UART_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_UART_GetIntStatus]) + +#define RomDriver_UART_GetTxBusBusyStatus \ + ((BL_Sts_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxBusBusyStatus]) + +#define RomDriver_UART_GetRxBusBusyStatus \ + ((BL_Sts_Type (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetRxBusBusyStatus]) + +#define RomDriver_UART_GetOverflowStatus \ + ((BL_Sts_Type (*) (UART_ID_Type uartId, UART_Overflow_Type overflow))ROM_APITABLE[ROM_API_INDEX_UART_GetOverflowStatus]) + +#define RomDriver_XIP_SFlash_Opt_Enter \ + ((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter]) + +#define RomDriver_XIP_SFlash_Opt_Exit \ + ((void (*) (uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit]) + +#define RomDriver_XIP_SFlash_State_Save \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t *offset))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + +#define RomDriver_XIP_SFlash_State_Restore \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t offset))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + +#define RomDriver_XIP_SFlash_Erase_Need_Lock \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + +#define RomDriver_XIP_SFlash_Write_Need_Lock \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Need_Lock \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + +#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + +#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ + ((BL_Err_Type (*) (uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) + +#define RomDriver_XIP_SFlash_Clear_Status_Register_Need_Lock\ + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Clear_Status_Register_Need_Lock]) + +#define RomDriver_IR_TxInit \ + ((BL_Err_Type (*) (IR_TxCfg_Type *irTxCfg))ROM_APITABLE[ROM_API_INDEX_IR_TxInit]) + +#define RomDriver_IR_TxPulseWidthConfig \ + ((BL_Err_Type (*) (IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg))ROM_APITABLE[ROM_API_INDEX_IR_TxPulseWidthConfig]) + +#define RomDriver_IR_FifoConfig \ + ((BL_Err_Type (*) (IR_FifoCfg_Type *fifoCfg))ROM_APITABLE[ROM_API_INDEX_IR_FifoConfig]) + +#define RomDriver_IR_DeInit \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_IR_DeInit]) + +#define RomDriver_IR_Enable \ + ((BL_Err_Type (*) (IR_Direction_Type direct))ROM_APITABLE[ROM_API_INDEX_IR_Enable]) + +#define RomDriver_IR_Disable \ + ((BL_Err_Type (*) (IR_Direction_Type direct))ROM_APITABLE[ROM_API_INDEX_IR_Disable]) + +#define RomDriver_IR_TxSWM \ + ((BL_Err_Type (*) (BL_Fun_Type txSWM))ROM_APITABLE[ROM_API_INDEX_IR_TxSWM]) + +#define RomDriver_IR_TxFifoClear \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_IR_TxFifoClear]) + +#define RomDriver_IR_SendData \ + ((BL_Err_Type (*) (uint32_t *data, uint8_t length))ROM_APITABLE[ROM_API_INDEX_IR_SendData]) + +#define RomDriver_IR_SWMSendData \ + ((BL_Err_Type (*) (uint16_t *data, uint8_t length))ROM_APITABLE[ROM_API_INDEX_IR_SWMSendData]) + +#define RomDriver_IR_SendCommand \ + ((BL_Err_Type (*) (uint32_t *data, uint8_t length))ROM_APITABLE[ROM_API_INDEX_IR_SendCommand]) + +#define RomDriver_IR_SWMSendCommand \ + ((BL_Err_Type (*) (uint16_t *data, uint8_t length))ROM_APITABLE[ROM_API_INDEX_IR_SWMSendCommand]) + +#define RomDriver_IR_SendNEC \ + ((BL_Err_Type (*) (uint8_t address, uint8_t command))ROM_APITABLE[ROM_API_INDEX_IR_SendNEC]) + +#define RomDriver_IR_IntMask \ + ((BL_Err_Type (*) (IR_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_IR_IntMask]) + +#define RomDriver_IR_ClrIntStatus \ + ((BL_Err_Type (*) (IR_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_IR_ClrIntStatus]) + +#define RomDriver_IR_GetIntStatus \ + ((BL_Sts_Type (*) (IR_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_IR_GetIntStatus]) + +#define RomDriver_IR_GetFifoStatus \ + ((BL_Sts_Type (*) (IR_FifoStatus_Type fifoSts))ROM_APITABLE[ROM_API_INDEX_IR_GetFifoStatus]) + +#define RomDriver_IR_GetTxFifoCount \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_IR_GetTxFifoCount]) + +#define RomDriver_IR_LEDInit \ + ((BL_Err_Type (*) (uint8_t clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L))ROM_APITABLE[ROM_API_INDEX_IR_LEDInit]) + +#define RomDriver_IR_LEDSend \ + ((BL_Err_Type (*) (uint32_t data))ROM_APITABLE[ROM_API_INDEX_IR_LEDSend]) + +#define RomDriver_KYS_Init \ + ((BL_Err_Type (*) (KYS_CFG_Type *kysCfg))ROM_APITABLE[ROM_API_INDEX_KYS_Init]) + +#define RomDriver_KYS_Enable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_KYS_Enable]) + +#define RomDriver_KYS_Disable \ + ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_KYS_Disable]) + +#define RomDriver_KYS_IntMask \ + ((BL_Err_Type (*) (KYS_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_KYS_IntMask]) + +#define RomDriver_KYS_IntClear \ + ((BL_Err_Type (*) (KYS_INT_CLR_Type intType))ROM_APITABLE[ROM_API_INDEX_KYS_IntClear]) + +#define RomDriver_KYS_GetIntStatus \ + ((BL_Sts_Type (*) (KYS_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_KYS_GetIntStatus]) + +#define RomDriver_KYS_Get_FIFO_Idx \ + ((void (*) (uint8_t *fifo_head, uint8_t *fifo_tail))ROM_APITABLE[ROM_API_INDEX_KYS_Get_FIFO_Idx]) + +#define RomDriver_KYS_ReadKeyfifo \ + ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_KYS_ReadKeyfifo]) + +#define RomDriver_Psram_Init \ + ((void (*) (SPI_Psram_Cfg_Type *psramCfg, struct sf_ctrl_cmds_cfg *cmdsCfg, struct sf_ctrl_psram_cfg *sfCtrlPsramCfg))ROM_APITABLE[ROM_API_INDEX_Psram_Init]) + +#define RomDriver_Psram_ReadReg \ + ((void (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue))ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg]) + +#define RomDriver_Psram_WriteReg \ + ((void (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue))ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg]) + +#define RomDriver_Psram_SetDriveStrength \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg))ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength]) + +#define RomDriver_Psram_SetBurstWrap \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg))ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap]) + +#define RomDriver_Psram_ReadId \ + ((void (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_Psram_ReadId]) + +#define RomDriver_Psram_EnterQuadMode \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg))ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode]) + +#define RomDriver_Psram_ExitQuadMode \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg))ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode]) + +#define RomDriver_Psram_ToggleBurstLength \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode))ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength]) + +#define RomDriver_Psram_SoftwareReset \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode))ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset]) + +#define RomDriver_Psram_Set_IDbus_Cfg \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t ioMode, uint32_t addr, uint32_t len))ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg]) + +#define RomDriver_Psram_Cache_Write_Set \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set]) + +#define RomDriver_Psram_Write \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_Psram_Write]) + +#define RomDriver_Psram_Read \ + ((BL_Err_Type (*) (SPI_Psram_Cfg_Type *psramCfg, uint8_t ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_Psram_Read]) + +#define RomDriver_TIMER_GetCompValue \ + ((uint32_t (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo))ROM_APITABLE[ROM_API_INDEX_TIMER_GetCompValue]) + +#define RomDriver_TIMER_SetCompValue \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val))ROM_APITABLE[ROM_API_INDEX_TIMER_SetCompValue]) + +#define RomDriver_TIMER_CompValueEffectImmediately \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable))ROM_APITABLE[ROM_API_INDEX_TIMER_CompValueEffectImmediately]) + +#define RomDriver_TIMER_GetCounterValue \ + ((uint32_t (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh))ROM_APITABLE[ROM_API_INDEX_TIMER_GetCounterValue]) + +#define RomDriver_TIMER_ResetCounterValue \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh))ROM_APITABLE[ROM_API_INDEX_TIMER_ResetCounterValue]) + +#define RomDriver_TIMER_GetMatchStatus \ + ((BL_Sts_Type (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo))ROM_APITABLE[ROM_API_INDEX_TIMER_GetMatchStatus]) + +#define RomDriver_TIMER_GetPreloadValue \ + ((uint32_t (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh))ROM_APITABLE[ROM_API_INDEX_TIMER_GetPreloadValue]) + +#define RomDriver_TIMER_SetPreloadValue \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val))ROM_APITABLE[ROM_API_INDEX_TIMER_SetPreloadValue]) + +#define RomDriver_TIMER_SetPreloadTrigSrc \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc))ROM_APITABLE[ROM_API_INDEX_TIMER_SetPreloadTrigSrc]) + +#define RomDriver_TIMER_SetCountMode \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode))ROM_APITABLE[ROM_API_INDEX_TIMER_SetCountMode]) + +#define RomDriver_TIMER_ClearIntStatus \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo))ROM_APITABLE[ROM_API_INDEX_TIMER_ClearIntStatus]) + +#define RomDriver_TIMER_Init \ + ((BL_Err_Type (*) (TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg))ROM_APITABLE[ROM_API_INDEX_TIMER_Init]) + +#define RomDriver_TIMER_DeInit \ + ((BL_Err_Type (*) (TIMER_ID_Type timerId))ROM_APITABLE[ROM_API_INDEX_TIMER_DeInit]) + +#define RomDriver_TIMER_Enable \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh))ROM_APITABLE[ROM_API_INDEX_TIMER_Enable]) + +#define RomDriver_TIMER_Disable \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh))ROM_APITABLE[ROM_API_INDEX_TIMER_Disable]) + +#define RomDriver_TIMER_IntMask \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_TIMER_IntMask]) + +#define RomDriver_TIMER_GPIOSetPolarity \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity))ROM_APITABLE[ROM_API_INDEX_TIMER_GPIOSetPolarity]) + +#define RomDriver_TIMER_CH0_SetMeasurePulseWidth \ + ((void (*) (TIMER_ID_Type timerId, BL_Fun_Type enable))ROM_APITABLE[ROM_API_INDEX_TIMER_CH0_SetMeasurePulseWidth]) + +#define RomDriver_TIMER_CH0_GetMeasurePulseWidth \ + ((uint32_t (*) (TIMER_ID_Type timerId))ROM_APITABLE[ROM_API_INDEX_TIMER_CH0_GetMeasurePulseWidth]) + +#define RomDriver_TIMER_ForceClockDivision \ + ((void (*) (TIMER_ID_Type timerId, TIMER_Chan_Type timerCh))ROM_APITABLE[ROM_API_INDEX_TIMER_ForceClockDivision]) + +#define RomDriver_WDT_Set_Clock \ + ((void (*) (WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div))ROM_APITABLE[ROM_API_INDEX_WDT_Set_Clock]) + +#define RomDriver_WDT_GetMatchValue \ + ((uint16_t (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_GetMatchValue]) + +#define RomDriver_WDT_SetCompValue \ + ((void (*) (WDT_ID_Type wdtId, uint16_t val))ROM_APITABLE[ROM_API_INDEX_WDT_SetCompValue]) + +#define RomDriver_WDT_CompValueEffectImmediately \ + ((void (*) (WDT_ID_Type wdtId, BL_Fun_Type enable))ROM_APITABLE[ROM_API_INDEX_WDT_CompValueEffectImmediately]) + +#define RomDriver_WDT_GetCounterValue \ + ((uint16_t (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_GetCounterValue]) + +#define RomDriver_WDT_ResetCounterValue \ + ((void (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_ResetCounterValue]) + +#define RomDriver_WDT_GetResetStatus \ + ((BL_Sts_Type (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_GetResetStatus]) + +#define RomDriver_WDT_ClearResetStatus \ + ((void (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_ClearResetStatus]) + +#define RomDriver_WDT_Enable \ + ((void (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_Enable]) + +#define RomDriver_WDT_Disable \ + ((void (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_Disable]) + +#define RomDriver_WDT_ForceClockDivision \ + ((void (*) (WDT_ID_Type wdtId))ROM_APITABLE[ROM_API_INDEX_WDT_ForceClockDivision]) + +#define RomDriver_WDT_IntMask \ + ((void (*) (WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_WDT_IntMask]) + +#define RomDriver_WDT_GPIOSetPolarity \ + ((void (*) (WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity))ROM_APITABLE[ROM_API_INDEX_WDT_GPIOSetPolarity]) + +#define RomDriver_arch_memcpy \ + ((void * (*) (void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_arch_memcpy]) + +#define RomDriver_arch_memcpy4 \ + ((uint32_t * (*) (uint32_t *dst, const uint32_t *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_arch_memcpy4]) + +#define RomDriver_arch_memcpy_fast \ + ((void * (*) (void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_arch_memcpy_fast]) + +#define RomDriver_arch_memset \ + ((void * (*) (void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_arch_memset]) + +#define RomDriver_arch_memset4 \ + ((uint32_t * (*) (uint32_t *dst, const uint32_t val, uint32_t n))ROM_APITABLE[ROM_API_INDEX_arch_memset4]) + +#define RomDriver_arch_memcmp \ + ((int (*) (const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_arch_memcmp]) + +#define RomDriver_memcopy_to_fifo \ + ((void (*) (void *fifo_addr, uint8_t *data, uint32_t length))ROM_APITABLE[ROM_API_INDEX_memcopy_to_fifo]) + +#define RomDriver_fifocopy_to_mem \ + ((void (*) (void *fifo_addr, uint8_t *data, uint32_t length))ROM_APITABLE[ROM_API_INDEX_fifocopy_to_mem]) + +#define RomDriver_BFLB_Soft_CRC32_Ex \ + ((uint32_t (*) (uint32_t initial, void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32_Ex]) + +#define RomDriver_BFLB_Soft_CRC32 \ + ((uint32_t (*) (void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32]) + +/*@} end of group ROMDRIVER_Public_Macros */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_ROMDRIVER_H__ */ diff --git a/drivers/soc/bl702l/std/include/bl702l_tzc_sec.h b/drivers/soc/bl702l/std/include/bl702l_tzc_sec.h new file mode 100644 index 000000000..ee4f06941 --- /dev/null +++ b/drivers/soc/bl702l/std/include/bl702l_tzc_sec.h @@ -0,0 +1,92 @@ +/** + ****************************************************************************** + * @file bl702l_tzc_sec.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL702L_TZC_SEC_H__ +#define __BL702L_TZC_SEC_H__ + +#include "tzc_sec_reg.h" +#include "bl702l_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup TZC_SEC + * @{ + */ + +/** @defgroup TZC_SEC_Public_Types + * @{ + */ + +/*@} end of group TZC_SEC_Public_Types */ + +/** @defgroup TZC_SEC_Public_Constants + * @{ + */ + +/*@} end of group TZC_SEC_Public_Constants */ + +/** @defgroup TZC_SEC_Public_Macros + * @{ + */ + +/*@} end of group TZC_SEC_Public_Macros */ + +/** @defgroup TZC_SEC_Public_Functions + * @{ + */ + +void TZC_Sboot_Set(uint8_t Val); +void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t length); +void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t length); +void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t length); +void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t length); + +/*@} end of group TZC_SEC_Public_Functions */ + +/*@} end of group TZC_SEC */ + +/*@} end of group BL702L_Peripheral_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BL702L_TZC_SEC_H__ */ diff --git a/drivers/soc/bl702l/std/include/hardware/aon_reg.h b/drivers/soc/bl702l/std/include/hardware/aon_reg.h new file mode 100644 index 000000000..88c3057b0 --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/aon_reg.h @@ -0,0 +1,1103 @@ +/** + ****************************************************************************** + * @file aon_reg.h + * @version V1.0 + * @date 2022-06-29 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __AON_REG_H__ +#define __AON_REG_H__ + +#include "bl702l.h" + +/* 0x800 : aon */ +#define AON_OFFSET (0x800) +#define AON_RESV AON_RESV +#define AON_RESV_POS (0U) +#define AON_RESV_LEN (8U) +#define AON_RESV_MSK (((1U< + +/** + * @} + */ + +#endif diff --git a/drivers/soc/bl702l/std/include/hardware/ef_ctrl_reg.h b/drivers/soc/bl702l/std/include/hardware/ef_ctrl_reg.h new file mode 100644 index 000000000..09a4f0d8b --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/ef_ctrl_reg.h @@ -0,0 +1,812 @@ +/** + ****************************************************************************** + * @file ef_ctrl_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_CTRL_REG_H__ +#define __EF_CTRL_REG_H__ + +#include "bl702l.h" + +/* 0x800 : ef_if_ctrl_0 */ +#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS) +#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)) +#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY +#define EF_CTRL_EF_IF_0_BUSY_POS (2U) +#define EF_CTRL_EF_IF_0_BUSY_LEN (1U) +#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS) +#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)) +#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW +#define EF_CTRL_EF_IF_0_RW_POS (3U) +#define EF_CTRL_EF_IF_0_RW_LEN (1U) +#define EF_CTRL_EF_IF_0_RW_MSK (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS) +#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)) +#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG +#define EF_CTRL_EF_IF_0_TRIG_POS (4U) +#define EF_CTRL_EF_IF_0_TRIG_LEN (1U) +#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS) +#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)) +#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN +#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS) +#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)) +#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY +#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) +#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)) +#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG +#define EF_CTRL_EF_IF_POR_DIG_POS (16U) +#define EF_CTRL_EF_IF_POR_DIG_LEN (1U) +#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS) +#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS) +#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)) +#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN +#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U) +#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS) +#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS) +#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)) +#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT +#define EF_CTRL_EF_IF_0_INT_POS (20U) +#define EF_CTRL_EF_IF_0_INT_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_MSK (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS) +#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)) +#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR +#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U) +#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS) +#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)) +#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET +#define EF_CTRL_EF_IF_0_INT_SET_POS (22U) +#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U) +#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS) +#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC +#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS) +#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)) + +/* 0x804 : ef_if_cyc_0 */ +#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804) +#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY +#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS) +#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)) +#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT +#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS) +#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)) +#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR +#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS) +#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS +#define EF_CTRL_EF_IF_CYC_CS_POS (18U) +#define EF_CTRL_EF_IF_CYC_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS) +#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S +#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)) + +/* 0x808 : ef_if_cyc_1 */ +#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808) +#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI +#define EF_CTRL_EF_IF_CYC_PI_POS (0U) +#define EF_CTRL_EF_IF_CYC_PI_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS) +#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)) +#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP +#define EF_CTRL_EF_IF_CYC_PP_POS (6U) +#define EF_CTRL_EF_IF_CYC_PP_LEN (8U) +#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS) +#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)) +#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR +#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U) +#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS) +#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)) +#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS +#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U) +#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS) +#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)) +#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H +#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS) +#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)) + +/* 0x80C : ef_if_0_manual */ +#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C) +#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A +#define EF_CTRL_EF_IF_A_POS (0U) +#define EF_CTRL_EF_IF_A_LEN (10U) +#define EF_CTRL_EF_IF_A_MSK (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS) +#define EF_CTRL_EF_IF_A_UMSK (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)) +#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD +#define EF_CTRL_EF_IF_PD_POS (10U) +#define EF_CTRL_EF_IF_PD_LEN (1U) +#define EF_CTRL_EF_IF_PD_MSK (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS) +#define EF_CTRL_EF_IF_PD_UMSK (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)) +#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS +#define EF_CTRL_EF_IF_PS_POS (11U) +#define EF_CTRL_EF_IF_PS_LEN (1U) +#define EF_CTRL_EF_IF_PS_MSK (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS) +#define EF_CTRL_EF_IF_PS_UMSK (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)) +#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE +#define EF_CTRL_EF_IF_STROBE_POS (12U) +#define EF_CTRL_EF_IF_STROBE_LEN (1U) +#define EF_CTRL_EF_IF_STROBE_MSK (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS) +#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)) +#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB +#define EF_CTRL_EF_IF_PGENB_POS (13U) +#define EF_CTRL_EF_IF_PGENB_LEN (1U) +#define EF_CTRL_EF_IF_PGENB_MSK (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS) +#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)) +#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD +#define EF_CTRL_EF_IF_LOAD_POS (14U) +#define EF_CTRL_EF_IF_LOAD_LEN (1U) +#define EF_CTRL_EF_IF_LOAD_MSK (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS) +#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)) +#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB +#define EF_CTRL_EF_IF_CSB_POS (15U) +#define EF_CTRL_EF_IF_CSB_LEN (1U) +#define EF_CTRL_EF_IF_CSB_MSK (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS) +#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)) +#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q +#define EF_CTRL_EF_IF_0_Q_POS (16U) +#define EF_CTRL_EF_IF_0_Q_LEN (8U) +#define EF_CTRL_EF_IF_0_Q_MSK (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS) +#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS) +#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)) + +/* 0x810 : ef_if_0_status */ +#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810) +#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS +#define EF_CTRL_EF_IF_0_STATUS_POS (0U) +#define EF_CTRL_EF_IF_0_STATUS_LEN (32U) +#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS) +#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)) + +/* 0x814 : ef_if_cfg_0 */ +#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814) +#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE +#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS) +#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE EF_CTRL_EF_IF_SBOOT_SIGN_MODE +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN +#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS) +#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)) +#define EF_CTRL_EF_IF_CPU1_ENC_EN EF_CTRL_EF_IF_CPU1_ENC_EN +#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CPU0_ENC_EN EF_CTRL_EF_IF_CPU0_ENC_EN +#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_IF_BOOT_SEL EF_CTRL_EF_IF_BOOT_SEL +#define EF_CTRL_EF_IF_BOOT_SEL_POS (8U) +#define EF_CTRL_EF_IF_BOOT_SEL_LEN (4U) +#define EF_CTRL_EF_IF_BOOT_SEL_MSK (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS) +#define EF_CTRL_EF_IF_BOOT_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL EF_CTRL_EF_IF_SF_KEY_0_SEL +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_POS (12U) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN (2U) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_MSK (((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS) +#define EF_CTRL_EF_IF_SF_KEY_0_SEL_UMSK (~(((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS)) +#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS +#define EF_CTRL_EF_IF_SDU_DIS_POS (14U) +#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS) +#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)) +#define EF_CTRL_EF_IF_BLE_DIS EF_CTRL_EF_IF_BLE_DIS +#define EF_CTRL_EF_IF_BLE_DIS_POS (15U) +#define EF_CTRL_EF_IF_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_IF_BLE_DIS_MSK (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS) +#define EF_CTRL_EF_IF_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)) +#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS +#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS) +#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS +#define EF_CTRL_EF_IF_CAM_DIS_POS (18U) +#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS) +#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)) +#define EF_CTRL_EF_IF_M154_DIS EF_CTRL_EF_IF_M154_DIS +#define EF_CTRL_EF_IF_M154_DIS_POS (19U) +#define EF_CTRL_EF_IF_M154_DIS_LEN (1U) +#define EF_CTRL_EF_IF_M154_DIS_MSK (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS) +#define EF_CTRL_EF_IF_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)) +#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS +#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS) +#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS +#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE +#define EF_CTRL_EF_IF_DBG_MODE_POS (28U) +#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS) +#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)) + +/* 0x818 : ef_sw_cfg_0 */ +#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818) +#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE +#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U) +#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS) +#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE EF_CTRL_EF_SW_SBOOT_SIGN_MODE +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS) +#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)) +#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN +#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U) +#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U) +#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS) +#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)) +#define EF_CTRL_EF_SW_CPU1_ENC_EN EF_CTRL_EF_SW_CPU1_ENC_EN +#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS (6U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CPU0_ENC_EN EF_CTRL_EF_SW_CPU0_ENC_EN +#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS (7U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS) +#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL EF_CTRL_EF_SW_SF_KEY_0_SEL +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_POS (12U) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN (2U) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_MSK (((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS) +#define EF_CTRL_EF_SW_SF_KEY_0_SEL_UMSK (~(((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS)) +#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS +#define EF_CTRL_EF_SW_SDU_DIS_POS (14U) +#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS) +#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)) +#define EF_CTRL_EF_SW_BLE_DIS EF_CTRL_EF_SW_BLE_DIS +#define EF_CTRL_EF_SW_BLE_DIS_POS (15U) +#define EF_CTRL_EF_SW_BLE_DIS_LEN (1U) +#define EF_CTRL_EF_SW_BLE_DIS_MSK (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS) +#define EF_CTRL_EF_SW_BLE_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)) +#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS +#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U) +#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U) +#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS) +#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS) +#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)) +#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS +#define EF_CTRL_EF_SW_CAM_DIS_POS (18U) +#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS) +#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)) +#define EF_CTRL_EF_SW_M154_DIS EF_CTRL_EF_SW_M154_DIS +#define EF_CTRL_EF_SW_M154_DIS_POS (19U) +#define EF_CTRL_EF_SW_M154_DIS_LEN (1U) +#define EF_CTRL_EF_SW_M154_DIS_MSK (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS) +#define EF_CTRL_EF_SW_M154_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)) +#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS +#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U) +#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS) +#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS) +#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS +#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS) +#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS) +#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)) +#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE +#define EF_CTRL_EF_SW_DBG_MODE_POS (28U) +#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U) +#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS) +#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)) + +/* 0x81C : ef_reserved */ +#define EF_CTRL_EF_RESERVED_OFFSET (0x81C) +#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED +#define EF_CTRL_EF_RESERVED_POS (0U) +#define EF_CTRL_EF_RESERVED_LEN (32U) +#define EF_CTRL_EF_RESERVED_MSK (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS) +#define EF_CTRL_EF_RESERVED_UMSK (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)) + +/* 0x820 : ef_if_ana_trim_0 */ +#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820) +#define EF_CTRL_EF_IF_ANA_TRIM_0 EF_CTRL_EF_IF_ANA_TRIM_0 +#define EF_CTRL_EF_IF_ANA_TRIM_0_POS (0U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN (32U) +#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS) +#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)) + +/* 0x824 : ef_if_sw_usage_0 */ +#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824) +#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0 +#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U) +#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U) +#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS) +#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)) + +/* 0xA00 : ef_crc_ctrl_0 */ +#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00) +#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY +#define EF_CTRL_EF_CRC_BUSY_POS (0U) +#define EF_CTRL_EF_CRC_BUSY_LEN (1U) +#define EF_CTRL_EF_CRC_BUSY_MSK (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS) +#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)) +#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG +#define EF_CTRL_EF_CRC_TRIG_POS (1U) +#define EF_CTRL_EF_CRC_TRIG_LEN (1U) +#define EF_CTRL_EF_CRC_TRIG_MSK (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS) +#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)) +#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN +#define EF_CTRL_EF_CRC_EN_POS (2U) +#define EF_CTRL_EF_CRC_EN_LEN (1U) +#define EF_CTRL_EF_CRC_EN_MSK (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS) +#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)) +#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE +#define EF_CTRL_EF_CRC_MODE_POS (3U) +#define EF_CTRL_EF_CRC_MODE_LEN (1U) +#define EF_CTRL_EF_CRC_MODE_MSK (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS) +#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)) +#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR +#define EF_CTRL_EF_CRC_ERROR_POS (4U) +#define EF_CTRL_EF_CRC_ERROR_LEN (1U) +#define EF_CTRL_EF_CRC_ERROR_MSK (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS) +#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)) +#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN +#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS) +#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN +#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS) +#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)) +#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT +#define EF_CTRL_EF_CRC_INT_POS (8U) +#define EF_CTRL_EF_CRC_INT_LEN (1U) +#define EF_CTRL_EF_CRC_INT_MSK (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS) +#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)) +#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR +#define EF_CTRL_EF_CRC_INT_CLR_POS (9U) +#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U) +#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS) +#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)) +#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET +#define EF_CTRL_EF_CRC_INT_SET_POS (10U) +#define EF_CTRL_EF_CRC_INT_SET_LEN (1U) +#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS) +#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)) +#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK +#define EF_CTRL_EF_CRC_LOCK_POS (11U) +#define EF_CTRL_EF_CRC_LOCK_LEN (1U) +#define EF_CTRL_EF_CRC_LOCK_MSK (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS) +#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)) +#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N +#define EF_CTRL_EF_CRC_SLP_N_POS (16U) +#define EF_CTRL_EF_CRC_SLP_N_LEN (16U) +#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS) +#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)) + +/* 0xA04 : ef_crc_ctrl_1 */ +#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04) +#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN +#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS) +#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)) + +/* 0xA08 : ef_crc_ctrl_2 */ +#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08) +#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN +#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U) +#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U) +#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS) +#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)) + +/* 0xA0C : ef_crc_ctrl_3 */ +#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C) +#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV +#define EF_CTRL_EF_CRC_IV_POS (0U) +#define EF_CTRL_EF_CRC_IV_LEN (32U) +#define EF_CTRL_EF_CRC_IV_MSK (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS) +#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)) + +/* 0xA10 : ef_crc_ctrl_4 */ +#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10) +#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN +#define EF_CTRL_EF_CRC_GOLDEN_POS (0U) +#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U) +#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS) +#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)) + +/* 0xA14 : ef_crc_ctrl_5 */ +#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14) +#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT +#define EF_CTRL_EF_CRC_DOUT_POS (0U) +#define EF_CTRL_EF_CRC_DOUT_LEN (32U) +#define EF_CTRL_EF_CRC_DOUT_MSK (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS) +#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)) + +struct ef_ctrl_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[2048]; + + /* 0x800 : ef_if_ctrl_0 */ + union { + struct + { + uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */ + uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */ + uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */ + uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */ + uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */ + uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_sel : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */ + uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_clk_sahb_data_gate : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */ + uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */ + uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ctrl_0; + + /* 0x804 : ef_if_cyc_0 */ + union { + struct + { + uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */ + uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */ + uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */ + uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */ + uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */ + } BF; + uint32_t WORD; + } ef_if_cyc_0; + + /* 0x808 : ef_if_cyc_1 */ + union { + struct + { + uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */ + uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */ + uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */ + uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */ + uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cyc_1; + + /* 0x80C : ef_if_0_manual */ + union { + struct + { + uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */ + uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */ + uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */ + uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */ + uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */ + uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */ + uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */ + uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */ + uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_0_manual; + + /* 0x810 : ef_if_0_status */ + union { + struct + { + uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */ + } BF; + uint32_t WORD; + } ef_if_0_status; + + /* 0x814 : ef_if_cfg_0 */ + union { + struct + { + uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */ + uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2], r, 0x0 */ + uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */ + uint32_t ef_if_cpu1_enc_en : 1; /* [ 6], r, 0x0 */ + uint32_t ef_if_cpu0_enc_en : 1; /* [ 7], r, 0x0 */ + uint32_t ef_if_boot_sel : 4; /* [11: 8], r, 0x0 */ + uint32_t ef_if_sf_key_0_sel : 2; /* [13:12], r, 0x0 */ + uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */ + uint32_t ef_if_ble_dis : 1; /* [ 15], r, 0x0 */ + uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */ + uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */ + uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */ + uint32_t ef_if_m154_dis : 1; /* [ 19], r, 0x0 */ + uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */ + uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */ + uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */ + uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */ + uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */ + uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */ + uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_cfg_0; + + /* 0x818 : ef_sw_cfg_0 */ + union { + struct + { + uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t ef_sw_cpu1_enc_en : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_sw_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ + uint32_t ef_sw_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */ + uint32_t ef_sw_ble_dis : 1; /* [ 15], r/w, 0x0 */ + uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */ + uint32_t ef_sw_m154_dis : 1; /* [ 19], r/w, 0x0 */ + uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */ + uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */ + uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */ + uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */ + uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_cfg_0; + + /* 0x81C : ef_reserved */ + union { + struct + { + uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */ + } BF; + uint32_t WORD; + } ef_reserved; + + /* 0x820 : ef_if_ana_trim_0 */ + union { + struct + { + uint32_t ef_if_ana_trim_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_ana_trim_0; + + /* 0x824 : ef_if_sw_usage_0 */ + union { + struct + { + uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } ef_if_sw_usage_0; + + /* 0x828 reserved */ + uint8_t RESERVED0x828[472]; + + /* 0xA00 : ef_crc_ctrl_0 */ + union { + struct + { + uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */ + uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */ + uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */ + uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */ + uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */ + uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */ + uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */ + uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */ + uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_0; + + /* 0xA04 : ef_crc_ctrl_1 */ + union { + struct + { + uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_1; + + /* 0xA08 : ef_crc_ctrl_2 */ + union { + struct + { + uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_2; + + /* 0xA0C : ef_crc_ctrl_3 */ + union { + struct + { + uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_3; + + /* 0xA10 : ef_crc_ctrl_4 */ + union { + struct + { + uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_4; + + /* 0xA14 : ef_crc_ctrl_5 */ + union { + struct + { + uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */ + } BF; + uint32_t WORD; + } ef_crc_ctrl_5; +}; + +typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t; + +#endif /* __EF_CTRL_REG_H__ */ diff --git a/drivers/soc/bl702l/std/include/hardware/ef_data_reg.h b/drivers/soc/bl702l/std/include/hardware/ef_data_reg.h new file mode 100644 index 000000000..35371d9eb --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/ef_data_reg.h @@ -0,0 +1,762 @@ +/** + ****************************************************************************** + * @file EF_DATA_reg.h + * @version V1.2 + * @date 2020-04-30 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __EF_DATA_REG_H__ +#define __EF_DATA_REG_H__ + +#include "bl702l.h" + +/* 0x0 : ef_cfg_0 */ +#define EF_DATA_EF_CFG_0_OFFSET (0x0) +#define EF_DATA_EF_SF_AES_MODE EF_DATA_EF_SF_AES_MODE +#define EF_DATA_EF_SF_AES_MODE_POS (0U) +#define EF_DATA_EF_SF_AES_MODE_LEN (2U) +#define EF_DATA_EF_SF_AES_MODE_MSK (((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS) +#define EF_DATA_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS)) +#define EF_DATA_EF_SBOOT_SIGN_MODE EF_DATA_EF_SBOOT_SIGN_MODE +#define EF_DATA_EF_SBOOT_SIGN_MODE_POS (2U) +#define EF_DATA_EF_SBOOT_SIGN_MODE_LEN (2U) +#define EF_DATA_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS) +#define EF_DATA_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS)) +#define EF_DATA_EF_SBOOT_EN EF_DATA_EF_SBOOT_EN +#define EF_DATA_EF_SBOOT_EN_POS (4U) +#define EF_DATA_EF_SBOOT_EN_LEN (2U) +#define EF_DATA_EF_SBOOT_EN_MSK (((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS) +#define EF_DATA_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS)) +#define EF_DATA_EF_CPU0_ENC_EN EF_DATA_EF_CPU0_ENC_EN +#define EF_DATA_EF_CPU0_ENC_EN_POS (7U) +#define EF_DATA_EF_CPU0_ENC_EN_LEN (1U) +#define EF_DATA_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS) +#define EF_DATA_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS)) +#define EF_DATA_EF_BOOT_SEL EF_DATA_EF_BOOT_SEL +#define EF_DATA_EF_BOOT_SEL_POS (8U) +#define EF_DATA_EF_BOOT_SEL_LEN (4U) +#define EF_DATA_EF_BOOT_SEL_MSK (((1U << EF_DATA_EF_BOOT_SEL_LEN) - 1) << EF_DATA_EF_BOOT_SEL_POS) +#define EF_DATA_EF_BOOT_SEL_UMSK (~(((1U << EF_DATA_EF_BOOT_SEL_LEN) - 1) << EF_DATA_EF_BOOT_SEL_POS)) +#define EF_DATA_EF_SF_KEY_0_SEL EF_DATA_EF_SF_KEY_0_SEL +#define EF_DATA_EF_SF_KEY_0_SEL_POS (12U) +#define EF_DATA_EF_SF_KEY_0_SEL_LEN (2U) +#define EF_DATA_EF_SF_KEY_0_SEL_MSK (((1U << EF_DATA_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_EF_SF_KEY_0_SEL_POS) +#define EF_DATA_EF_SF_KEY_0_SEL_UMSK (~(((1U << EF_DATA_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_EF_SF_KEY_0_SEL_POS)) +#define EF_DATA_EF_0_KEY_ENC_EN EF_DATA_EF_0_KEY_ENC_EN +#define EF_DATA_EF_0_KEY_ENC_EN_POS (17U) +#define EF_DATA_EF_0_KEY_ENC_EN_LEN (1U) +#define EF_DATA_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS) +#define EF_DATA_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS)) +#define EF_DATA_EF_DBG_JTAG_0_DIS EF_DATA_EF_DBG_JTAG_0_DIS +#define EF_DATA_EF_DBG_JTAG_0_DIS_POS (26U) +#define EF_DATA_EF_DBG_JTAG_0_DIS_LEN (2U) +#define EF_DATA_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS) +#define EF_DATA_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS)) +#define EF_DATA_EF_DBG_MODE EF_DATA_EF_DBG_MODE +#define EF_DATA_EF_DBG_MODE_POS (28U) +#define EF_DATA_EF_DBG_MODE_LEN (4U) +#define EF_DATA_EF_DBG_MODE_MSK (((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS) +#define EF_DATA_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS)) + +/* 0x4 : ef_dbg_pwd_low */ +#define EF_DATA_EF_DBG_PWD_LOW_OFFSET (0x4) +#define EF_DATA_EF_DBG_PWD_LOW EF_DATA_EF_DBG_PWD_LOW +#define EF_DATA_EF_DBG_PWD_LOW_POS (0U) +#define EF_DATA_EF_DBG_PWD_LOW_LEN (32U) +#define EF_DATA_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS) +#define EF_DATA_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS)) + +/* 0x8 : ef_dbg_pwd_high */ +#define EF_DATA_EF_DBG_PWD_HIGH_OFFSET (0x8) +#define EF_DATA_EF_DBG_PWD_HIGH EF_DATA_EF_DBG_PWD_HIGH +#define EF_DATA_EF_DBG_PWD_HIGH_POS (0U) +#define EF_DATA_EF_DBG_PWD_HIGH_LEN (32U) +#define EF_DATA_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS) +#define EF_DATA_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS)) + +/* 0xC : ef_ana_trim_0 */ +#define EF_DATA_EF_ANA_TRIM_0_OFFSET (0xC) +#define EF_DATA_EF_ANA_TRIM_0 EF_DATA_EF_ANA_TRIM_0 +#define EF_DATA_EF_ANA_TRIM_0_POS (0U) +#define EF_DATA_EF_ANA_TRIM_0_LEN (32U) +#define EF_DATA_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS) +#define EF_DATA_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS)) + +/* 0x10 : ef_sw_usage_0 */ +#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x10) +#define EF_DATA_EF_SW_USAGE_0 EF_DATA_EF_SW_USAGE_0 +#define EF_DATA_EF_SW_USAGE_0_POS (0U) +#define EF_DATA_EF_SW_USAGE_0_LEN (32U) +#define EF_DATA_EF_SW_USAGE_0_MSK (((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS) +#define EF_DATA_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS)) + +/* 0x14 : ef_wifi_mac_low */ +#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14) +#define EF_DATA_EF_WIFI_MAC_LOW EF_DATA_EF_WIFI_MAC_LOW +#define EF_DATA_EF_WIFI_MAC_LOW_POS (0U) +#define EF_DATA_EF_WIFI_MAC_LOW_LEN (32U) +#define EF_DATA_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS) +#define EF_DATA_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS)) + +/* 0x18 : ef_wifi_mac_high */ +#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18) +#define EF_DATA_EF_WIFI_MAC_HIGH EF_DATA_EF_WIFI_MAC_HIGH +#define EF_DATA_EF_WIFI_MAC_HIGH_POS (0U) +#define EF_DATA_EF_WIFI_MAC_HIGH_LEN (32U) +#define EF_DATA_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS) +#define EF_DATA_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS)) + +/* 0x1C : ef_key_slot_0_w0 */ +#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C) +#define EF_DATA_EF_KEY_SLOT_0_W0 EF_DATA_EF_KEY_SLOT_0_W0 +#define EF_DATA_EF_KEY_SLOT_0_W0_POS (0U) +#define EF_DATA_EF_KEY_SLOT_0_W0_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS) +#define EF_DATA_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS)) + +/* 0x20 : ef_key_slot_0_w1 */ +#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20) +#define EF_DATA_EF_KEY_SLOT_0_W1 EF_DATA_EF_KEY_SLOT_0_W1 +#define EF_DATA_EF_KEY_SLOT_0_W1_POS (0U) +#define EF_DATA_EF_KEY_SLOT_0_W1_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS) +#define EF_DATA_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS)) + +/* 0x24 : ef_key_slot_0_w2 */ +#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24) +#define EF_DATA_EF_KEY_SLOT_0_W2 EF_DATA_EF_KEY_SLOT_0_W2 +#define EF_DATA_EF_KEY_SLOT_0_W2_POS (0U) +#define EF_DATA_EF_KEY_SLOT_0_W2_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS) +#define EF_DATA_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS)) + +/* 0x28 : ef_key_slot_0_w3 */ +#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28) +#define EF_DATA_EF_KEY_SLOT_0_W3 EF_DATA_EF_KEY_SLOT_0_W3 +#define EF_DATA_EF_KEY_SLOT_0_W3_POS (0U) +#define EF_DATA_EF_KEY_SLOT_0_W3_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS) +#define EF_DATA_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS)) + +/* 0x2C : ef_key_slot_1_w0 */ +#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C) +#define EF_DATA_EF_KEY_SLOT_1_W0 EF_DATA_EF_KEY_SLOT_1_W0 +#define EF_DATA_EF_KEY_SLOT_1_W0_POS (0U) +#define EF_DATA_EF_KEY_SLOT_1_W0_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS) +#define EF_DATA_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS)) + +/* 0x30 : ef_key_slot_1_w1 */ +#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30) +#define EF_DATA_EF_KEY_SLOT_1_W1 EF_DATA_EF_KEY_SLOT_1_W1 +#define EF_DATA_EF_KEY_SLOT_1_W1_POS (0U) +#define EF_DATA_EF_KEY_SLOT_1_W1_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS) +#define EF_DATA_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS)) + +/* 0x34 : ef_key_slot_1_w2 */ +#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34) +#define EF_DATA_EF_KEY_SLOT_1_W2 EF_DATA_EF_KEY_SLOT_1_W2 +#define EF_DATA_EF_KEY_SLOT_1_W2_POS (0U) +#define EF_DATA_EF_KEY_SLOT_1_W2_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS) +#define EF_DATA_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS)) + +/* 0x38 : ef_key_slot_1_w3 */ +#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38) +#define EF_DATA_EF_KEY_SLOT_1_W3 EF_DATA_EF_KEY_SLOT_1_W3 +#define EF_DATA_EF_KEY_SLOT_1_W3_POS (0U) +#define EF_DATA_EF_KEY_SLOT_1_W3_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS) +#define EF_DATA_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS)) + +/* 0x3C : ef_key_slot_2_w0 */ +#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C) +#define EF_DATA_EF_KEY_SLOT_2_W0 EF_DATA_EF_KEY_SLOT_2_W0 +#define EF_DATA_EF_KEY_SLOT_2_W0_POS (0U) +#define EF_DATA_EF_KEY_SLOT_2_W0_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS) +#define EF_DATA_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS)) + +/* 0x40 : ef_key_slot_2_w1 */ +#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40) +#define EF_DATA_EF_KEY_SLOT_2_W1 EF_DATA_EF_KEY_SLOT_2_W1 +#define EF_DATA_EF_KEY_SLOT_2_W1_POS (0U) +#define EF_DATA_EF_KEY_SLOT_2_W1_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS) +#define EF_DATA_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS)) + +/* 0x44 : ef_key_slot_2_w2 */ +#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44) +#define EF_DATA_EF_KEY_SLOT_2_W2 EF_DATA_EF_KEY_SLOT_2_W2 +#define EF_DATA_EF_KEY_SLOT_2_W2_POS (0U) +#define EF_DATA_EF_KEY_SLOT_2_W2_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS) +#define EF_DATA_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS)) + +/* 0x48 : ef_key_slot_2_w3 */ +#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48) +#define EF_DATA_EF_KEY_SLOT_2_W3 EF_DATA_EF_KEY_SLOT_2_W3 +#define EF_DATA_EF_KEY_SLOT_2_W3_POS (0U) +#define EF_DATA_EF_KEY_SLOT_2_W3_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS) +#define EF_DATA_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS)) + +/* 0x4C : ef_key_slot_3_w0 */ +#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C) +#define EF_DATA_EF_KEY_SLOT_3_W0 EF_DATA_EF_KEY_SLOT_3_W0 +#define EF_DATA_EF_KEY_SLOT_3_W0_POS (0U) +#define EF_DATA_EF_KEY_SLOT_3_W0_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS) +#define EF_DATA_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS)) + +/* 0x50 : ef_key_slot_3_w1 */ +#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50) +#define EF_DATA_EF_KEY_SLOT_3_W1 EF_DATA_EF_KEY_SLOT_3_W1 +#define EF_DATA_EF_KEY_SLOT_3_W1_POS (0U) +#define EF_DATA_EF_KEY_SLOT_3_W1_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS) +#define EF_DATA_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS)) + +/* 0x54 : ef_key_slot_3_w2 */ +#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54) +#define EF_DATA_EF_KEY_SLOT_3_W2 EF_DATA_EF_KEY_SLOT_3_W2 +#define EF_DATA_EF_KEY_SLOT_3_W2_POS (0U) +#define EF_DATA_EF_KEY_SLOT_3_W2_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS) +#define EF_DATA_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS)) + +/* 0x58 : ef_key_slot_3_w3 */ +#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58) +#define EF_DATA_EF_KEY_SLOT_3_W3 EF_DATA_EF_KEY_SLOT_3_W3 +#define EF_DATA_EF_KEY_SLOT_3_W3_POS (0U) +#define EF_DATA_EF_KEY_SLOT_3_W3_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS) +#define EF_DATA_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS)) + +/* 0x5C : ef_key_slot_4_w0 */ +#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C) +#define EF_DATA_EF_KEY_SLOT_4_W0 EF_DATA_EF_KEY_SLOT_4_W0 +#define EF_DATA_EF_KEY_SLOT_4_W0_POS (0U) +#define EF_DATA_EF_KEY_SLOT_4_W0_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS) +#define EF_DATA_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS)) + +/* 0x60 : ef_key_slot_4_w1 */ +#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60) +#define EF_DATA_EF_KEY_SLOT_4_W1 EF_DATA_EF_KEY_SLOT_4_W1 +#define EF_DATA_EF_KEY_SLOT_4_W1_POS (0U) +#define EF_DATA_EF_KEY_SLOT_4_W1_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS) +#define EF_DATA_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS)) + +/* 0x64 : ef_key_slot_4_w2 */ +#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64) +#define EF_DATA_EF_KEY_SLOT_4_W2 EF_DATA_EF_KEY_SLOT_4_W2 +#define EF_DATA_EF_KEY_SLOT_4_W2_POS (0U) +#define EF_DATA_EF_KEY_SLOT_4_W2_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS) +#define EF_DATA_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS)) + +/* 0x68 : ef_key_slot_4_w3 */ +#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68) +#define EF_DATA_EF_KEY_SLOT_4_W3 EF_DATA_EF_KEY_SLOT_4_W3 +#define EF_DATA_EF_KEY_SLOT_4_W3_POS (0U) +#define EF_DATA_EF_KEY_SLOT_4_W3_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS) +#define EF_DATA_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS)) + +/* 0x6C : ef_key_slot_5_w0 */ +#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C) +#define EF_DATA_EF_KEY_SLOT_5_W0 EF_DATA_EF_KEY_SLOT_5_W0 +#define EF_DATA_EF_KEY_SLOT_5_W0_POS (0U) +#define EF_DATA_EF_KEY_SLOT_5_W0_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS) +#define EF_DATA_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS)) + +/* 0x70 : ef_key_slot_5_w1 */ +#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70) +#define EF_DATA_EF_KEY_SLOT_5_W1 EF_DATA_EF_KEY_SLOT_5_W1 +#define EF_DATA_EF_KEY_SLOT_5_W1_POS (0U) +#define EF_DATA_EF_KEY_SLOT_5_W1_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS) +#define EF_DATA_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS)) + +/* 0x74 : ef_key_slot_5_w2 */ +#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74) +#define EF_DATA_EF_KEY_SLOT_5_W2 EF_DATA_EF_KEY_SLOT_5_W2 +#define EF_DATA_EF_KEY_SLOT_5_W2_POS (0U) +#define EF_DATA_EF_KEY_SLOT_5_W2_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS) +#define EF_DATA_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS)) + +/* 0x78 : ef_key_slot_5_w3 */ +#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78) +#define EF_DATA_EF_KEY_SLOT_5_W3 EF_DATA_EF_KEY_SLOT_5_W3 +#define EF_DATA_EF_KEY_SLOT_5_W3_POS (0U) +#define EF_DATA_EF_KEY_SLOT_5_W3_LEN (32U) +#define EF_DATA_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS) +#define EF_DATA_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS)) + +/* 0x7C : EF_DATA_lock */ +#define EF_DATA_LOCK_OFFSET (0x7C) +#define EF_DATA_EF_ANA_TRIM_1 EF_DATA_EF_ANA_TRIM_1 +#define EF_DATA_EF_ANA_TRIM_1_POS (0U) +#define EF_DATA_EF_ANA_TRIM_1_LEN (13U) +#define EF_DATA_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS) +#define EF_DATA_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_L EF_DATA_WR_LOCK_KEY_SLOT_4_L +#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS (13U) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_L EF_DATA_WR_LOCK_KEY_SLOT_5_L +#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS (14U) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS)) +#define EF_DATA_WR_LOCK_BOOT_MODE EF_DATA_WR_LOCK_BOOT_MODE +#define EF_DATA_WR_LOCK_BOOT_MODE_POS (15U) +#define EF_DATA_WR_LOCK_BOOT_MODE_LEN (1U) +#define EF_DATA_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS) +#define EF_DATA_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS)) +#define EF_DATA_WR_LOCK_DBG_PWD EF_DATA_WR_LOCK_DBG_PWD +#define EF_DATA_WR_LOCK_DBG_PWD_POS (16U) +#define EF_DATA_WR_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS) +#define EF_DATA_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS)) +#define EF_DATA_WR_LOCK_SW_USAGE_0 EF_DATA_WR_LOCK_SW_USAGE_0 +#define EF_DATA_WR_LOCK_SW_USAGE_0_POS (17U) +#define EF_DATA_WR_LOCK_SW_USAGE_0_LEN (1U) +#define EF_DATA_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS) +#define EF_DATA_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS)) +#define EF_DATA_WR_LOCK_WIFI_MAC EF_DATA_WR_LOCK_WIFI_MAC +#define EF_DATA_WR_LOCK_WIFI_MAC_POS (18U) +#define EF_DATA_WR_LOCK_WIFI_MAC_LEN (1U) +#define EF_DATA_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS) +#define EF_DATA_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_0 EF_DATA_WR_LOCK_KEY_SLOT_0 +#define EF_DATA_WR_LOCK_KEY_SLOT_0_POS (19U) +#define EF_DATA_WR_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_1 EF_DATA_WR_LOCK_KEY_SLOT_1 +#define EF_DATA_WR_LOCK_KEY_SLOT_1_POS (20U) +#define EF_DATA_WR_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_2 EF_DATA_WR_LOCK_KEY_SLOT_2 +#define EF_DATA_WR_LOCK_KEY_SLOT_2_POS (21U) +#define EF_DATA_WR_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_3 EF_DATA_WR_LOCK_KEY_SLOT_3 +#define EF_DATA_WR_LOCK_KEY_SLOT_3_POS (22U) +#define EF_DATA_WR_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_H EF_DATA_WR_LOCK_KEY_SLOT_4_H +#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS (23U) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS)) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_H EF_DATA_WR_LOCK_KEY_SLOT_5_H +#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS (24U) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN (1U) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS) +#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS)) +#define EF_DATA_RD_LOCK_DBG_PWD EF_DATA_RD_LOCK_DBG_PWD +#define EF_DATA_RD_LOCK_DBG_PWD_POS (25U) +#define EF_DATA_RD_LOCK_DBG_PWD_LEN (1U) +#define EF_DATA_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS) +#define EF_DATA_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS)) +#define EF_DATA_RD_LOCK_KEY_SLOT_0 EF_DATA_RD_LOCK_KEY_SLOT_0 +#define EF_DATA_RD_LOCK_KEY_SLOT_0_POS (26U) +#define EF_DATA_RD_LOCK_KEY_SLOT_0_LEN (1U) +#define EF_DATA_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS) +#define EF_DATA_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS)) +#define EF_DATA_RD_LOCK_KEY_SLOT_1 EF_DATA_RD_LOCK_KEY_SLOT_1 +#define EF_DATA_RD_LOCK_KEY_SLOT_1_POS (27U) +#define EF_DATA_RD_LOCK_KEY_SLOT_1_LEN (1U) +#define EF_DATA_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS) +#define EF_DATA_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS)) +#define EF_DATA_RD_LOCK_KEY_SLOT_2 EF_DATA_RD_LOCK_KEY_SLOT_2 +#define EF_DATA_RD_LOCK_KEY_SLOT_2_POS (28U) +#define EF_DATA_RD_LOCK_KEY_SLOT_2_LEN (1U) +#define EF_DATA_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS) +#define EF_DATA_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS)) +#define EF_DATA_RD_LOCK_KEY_SLOT_3 EF_DATA_RD_LOCK_KEY_SLOT_3 +#define EF_DATA_RD_LOCK_KEY_SLOT_3_POS (29U) +#define EF_DATA_RD_LOCK_KEY_SLOT_3_LEN (1U) +#define EF_DATA_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS) +#define EF_DATA_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS)) +#define EF_DATA_RD_LOCK_KEY_SLOT_4 EF_DATA_RD_LOCK_KEY_SLOT_4 +#define EF_DATA_RD_LOCK_KEY_SLOT_4_POS (30U) +#define EF_DATA_RD_LOCK_KEY_SLOT_4_LEN (1U) +#define EF_DATA_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS) +#define EF_DATA_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS)) +#define EF_DATA_RD_LOCK_KEY_SLOT_5 EF_DATA_RD_LOCK_KEY_SLOT_5 +#define EF_DATA_RD_LOCK_KEY_SLOT_5_POS (31U) +#define EF_DATA_RD_LOCK_KEY_SLOT_5_LEN (1U) +#define EF_DATA_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS) +#define EF_DATA_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS)) + +struct EF_DATA_reg { + /* 0x0 : ef_cfg_0 */ + union { + struct + { + uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ + uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ + uint32_t rsvd0 : 2; /* [ 5: 4], r/w, 0x0 */ + uint32_t rsvd1 : 1; /* [ 6], r/w, 0x0 */ + uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ + uint32_t ef_boot_sel : 4; /* [11: 8], r/w, 0x0 */ + uint32_t ef_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */ + uint32_t rsvd2 : 1; /* [ 14], r/w, 0x0 */ + uint32_t rsvd3 : 1; /* [ 15], r/w, 0x0 */ + uint32_t rsvd4 : 1; /* [ 16], r/w, 0x0 */ + uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t rsvd5 : 1; /* [ 18], r/w, 0x0 */ + uint32_t rsvd6 : 1; /* [ 19], r/w, 0x0 */ + uint32_t rsvd7 : 1; /* [ 20], r/w, 0x0 */ + uint32_t rsvd8 : 1; /* [ 21], r/w, 0x0 */ + uint32_t rsvd9 : 1; /* [ 22], r/w, 0x0 */ + uint32_t rsvd10 : 1; /* [ 23], r/w, 0x0 */ + uint32_t rsvd11 : 2; /* [25:24], r/w, 0x0 */ + uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ + uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_cfg_0; + + /* 0x4 : ef_dbg_pwd_low */ + union { + struct + { + uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_low; + + /* 0x8 : ef_dbg_pwd_high */ + union { + struct + { + uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_dbg_pwd_high; + + /* 0xC : ef_ana_trim_0 */ + union { + struct + { + uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_ana_trim_0; + + /* 0x10 : ef_sw_usage_0 */ + union { + struct + { + uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_sw_usage_0; + + /* 0x14 : ef_wifi_mac_low */ + union { + struct + { + uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_low; + + /* 0x18 : ef_wifi_mac_high */ + union { + struct + { + uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_wifi_mac_high; + + /* 0x1C : ef_key_slot_0_w0 */ + union { + struct + { + uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w0; + + /* 0x20 : ef_key_slot_0_w1 */ + union { + struct + { + uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w1; + + /* 0x24 : ef_key_slot_0_w2 */ + union { + struct + { + uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w2; + + /* 0x28 : ef_key_slot_0_w3 */ + union { + struct + { + uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_0_w3; + + /* 0x2C : ef_key_slot_1_w0 */ + union { + struct + { + uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w0; + + /* 0x30 : ef_key_slot_1_w1 */ + union { + struct + { + uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w1; + + /* 0x34 : ef_key_slot_1_w2 */ + union { + struct + { + uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w2; + + /* 0x38 : ef_key_slot_1_w3 */ + union { + struct + { + uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_1_w3; + + /* 0x3C : ef_key_slot_2_w0 */ + union { + struct + { + uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w0; + + /* 0x40 : ef_key_slot_2_w1 */ + union { + struct + { + uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w1; + + /* 0x44 : ef_key_slot_2_w2 */ + union { + struct + { + uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w2; + + /* 0x48 : ef_key_slot_2_w3 */ + union { + struct + { + uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_2_w3; + + /* 0x4C : ef_key_slot_3_w0 */ + union { + struct + { + uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w0; + + /* 0x50 : ef_key_slot_3_w1 */ + union { + struct + { + uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w1; + + /* 0x54 : ef_key_slot_3_w2 */ + union { + struct + { + uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w2; + + /* 0x58 : ef_key_slot_3_w3 */ + union { + struct + { + uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_3_w3; + + /* 0x5C : ef_key_slot_4_w0 */ + union { + struct + { + uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w0; + + /* 0x60 : ef_key_slot_4_w1 */ + union { + struct + { + uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w1; + + /* 0x64 : ef_key_slot_4_w2 */ + union { + struct + { + uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w2; + + /* 0x68 : ef_key_slot_4_w3 */ + union { + struct + { + uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_4_w3; + + /* 0x6C : ef_key_slot_5_w0 */ + union { + struct + { + uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w0; + + /* 0x70 : ef_key_slot_5_w1 */ + union { + struct + { + uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w1; + + /* 0x74 : ef_key_slot_5_w2 */ + union { + struct + { + uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w2; + + /* 0x78 : ef_key_slot_5_w3 */ + union { + struct + { + uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */ + } BF; + uint32_t WORD; + } ef_key_slot_5_w3; + + /* 0x7C : EF_DATA_lock */ + union { + struct + { + uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */ + uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */ + uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */ + uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */ + uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */ + uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */ + uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */ + uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */ + uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */ + uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */ + uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */ + uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */ + uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */ + uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */ + uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */ + uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */ + uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */ + uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */ + } BF; + uint32_t WORD; + } EF_DATA_lock; +}; + +typedef volatile struct EF_DATA_reg EF_DATA_reg_t; + +#endif /* __EF_DATA_REG_H__ */ diff --git a/drivers/soc/bl702l/std/include/hardware/glb_reg.h b/drivers/soc/bl702l/std/include/hardware/glb_reg.h new file mode 100644 index 000000000..3c88dbd00 --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/glb_reg.h @@ -0,0 +1,6720 @@ +/** + ****************************************************************************** + * @file glb_reg.h + * @version V1.0 + * @date 2022-07-14 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __GLB_REG_H__ +#define __GLB_REG_H__ + +#include "bl702l.h" + +/* 0x0 : clk_cfg0 */ +#define GLB_CLK_CFG0_OFFSET (0x0) +#define GLB_REG_PLL_EN GLB_REG_PLL_EN +#define GLB_REG_PLL_EN_POS (0U) +#define GLB_REG_PLL_EN_LEN (1U) +#define GLB_REG_PLL_EN_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HBN_REG_H__ +#define __HBN_REG_H__ + +#include "bl702l.h" + +/* 0x0 : HBN_CTL */ +#define HBN_CTL_OFFSET (0x0) +#define HBN_RTC_CTL HBN_RTC_CTL +#define HBN_RTC_CTL_POS (0U) +#define HBN_RTC_CTL_LEN (4U) +#define HBN_RTC_CTL_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without + *modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + *ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + *LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + *INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + *CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + *ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + *POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __KYS_REG_H__ +#define __KYS_REG_H__ + +#include "bl702l.h" + +/* 0x0 : ks_ctrl */ +#define KYS_KS_CTRL_OFFSET (0x0) +#define KYS_KS_EN KYS_KS_EN +#define KYS_KS_EN_POS (0U) +#define KYS_KS_EN_LEN (1U) +#define KYS_KS_EN_MSK (((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS) +#define KYS_KS_EN_UMSK (~(((1U << KYS_KS_EN_LEN) - 1) << KYS_KS_EN_POS)) +#define KYS_FIFO_MODE KYS_FIFO_MODE +#define KYS_FIFO_MODE_POS (1U) +#define KYS_FIFO_MODE_LEN (1U) +#define KYS_FIFO_MODE_MSK (((1U << KYS_FIFO_MODE_LEN) - 1) << KYS_FIFO_MODE_POS) +#define KYS_FIFO_MODE_UMSK (~(((1U << KYS_FIFO_MODE_LEN) - 1) << KYS_FIFO_MODE_POS)) +#define KYS_GHOST_EN KYS_GHOST_EN +#define KYS_GHOST_EN_POS (2U) +#define KYS_GHOST_EN_LEN (1U) +#define KYS_GHOST_EN_MSK (((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS) +#define KYS_GHOST_EN_UMSK (~(((1U << KYS_GHOST_EN_LEN) - 1) << KYS_GHOST_EN_POS)) +#define KYS_DEG_EN KYS_DEG_EN +#define KYS_DEG_EN_POS (3U) +#define KYS_DEG_EN_LEN (1U) +#define KYS_DEG_EN_MSK (((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS) +#define KYS_DEG_EN_UMSK (~(((1U << KYS_DEG_EN_LEN) - 1) << KYS_DEG_EN_POS)) +#define KYS_DEG_CNT KYS_DEG_CNT +#define KYS_DEG_CNT_POS (4U) +#define KYS_DEG_CNT_LEN (4U) +#define KYS_DEG_CNT_MSK (((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS) +#define KYS_DEG_CNT_UMSK (~(((1U << KYS_DEG_CNT_LEN) - 1) << KYS_DEG_CNT_POS)) +#define KYS_RC_EXT KYS_RC_EXT +#define KYS_RC_EXT_POS (8U) +#define KYS_RC_EXT_LEN (2U) +#define KYS_RC_EXT_MSK (((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS) +#define KYS_RC_EXT_UMSK (~(((1U << KYS_RC_EXT_LEN) - 1) << KYS_RC_EXT_POS)) +#define KYS_ROW_NUM KYS_ROW_NUM +#define KYS_ROW_NUM_POS (16U) +#define KYS_ROW_NUM_LEN (3U) +#define KYS_ROW_NUM_MSK (((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS) +#define KYS_ROW_NUM_UMSK (~(((1U << KYS_ROW_NUM_LEN) - 1) << KYS_ROW_NUM_POS)) +#define KYS_COL_NUM KYS_COL_NUM +#define KYS_COL_NUM_POS (20U) +#define KYS_COL_NUM_LEN (3U) +#define KYS_COL_NUM_MSK (((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS) +#define KYS_COL_NUM_UMSK (~(((1U << KYS_COL_NUM_LEN) - 1) << KYS_COL_NUM_POS)) + +/* 0x10 : ks_int_en */ +#define KYS_KS_INT_EN_OFFSET (0x10) +#define KYS_KS_DONE_INT_EN KYS_KS_DONE_INT_EN +#define KYS_KS_DONE_INT_EN_POS (7U) +#define KYS_KS_DONE_INT_EN_LEN (1U) +#define KYS_KS_DONE_INT_EN_MSK (((1U << KYS_KS_DONE_INT_EN_LEN) - 1) << KYS_KS_DONE_INT_EN_POS) +#define KYS_KS_DONE_INT_EN_UMSK (~(((1U << KYS_KS_DONE_INT_EN_LEN) - 1) << KYS_KS_DONE_INT_EN_POS)) +#define KYS_KEYFIFO_INT_EN KYS_KEYFIFO_INT_EN +#define KYS_KEYFIFO_INT_EN_POS (8U) +#define KYS_KEYFIFO_INT_EN_LEN (4U) +#define KYS_KEYFIFO_INT_EN_MSK (((1U << KYS_KEYFIFO_INT_EN_LEN) - 1) << KYS_KEYFIFO_INT_EN_POS) +#define KYS_KEYFIFO_INT_EN_UMSK (~(((1U << KYS_KEYFIFO_INT_EN_LEN) - 1) << KYS_KEYFIFO_INT_EN_POS)) +#define KYS_GHOST_INT_EN KYS_GHOST_INT_EN +#define KYS_GHOST_INT_EN_POS (12U) +#define KYS_GHOST_INT_EN_LEN (1U) +#define KYS_GHOST_INT_EN_MSK (((1U << KYS_GHOST_INT_EN_LEN) - 1) << KYS_GHOST_INT_EN_POS) +#define KYS_GHOST_INT_EN_UMSK (~(((1U << KYS_GHOST_INT_EN_LEN) - 1) << KYS_GHOST_INT_EN_POS)) + +/* 0x14 : ks_int_sts */ +#define KYS_KS_INT_STS_OFFSET (0x14) +#define KYS_KEYCODE_DONE KYS_KEYCODE_DONE +#define KYS_KEYCODE_DONE_POS (7U) +#define KYS_KEYCODE_DONE_LEN (1U) +#define KYS_KEYCODE_DONE_MSK (((1U << KYS_KEYCODE_DONE_LEN) - 1) << KYS_KEYCODE_DONE_POS) +#define KYS_KEYCODE_DONE_UMSK (~(((1U << KYS_KEYCODE_DONE_LEN) - 1) << KYS_KEYCODE_DONE_POS)) +#define KYS_KEYFIFO_FULL KYS_KEYFIFO_FULL +#define KYS_KEYFIFO_FULL_POS (8U) +#define KYS_KEYFIFO_FULL_LEN (1U) +#define KYS_KEYFIFO_FULL_MSK (((1U << KYS_KEYFIFO_FULL_LEN) - 1) << KYS_KEYFIFO_FULL_POS) +#define KYS_KEYFIFO_FULL_UMSK (~(((1U << KYS_KEYFIFO_FULL_LEN) - 1) << KYS_KEYFIFO_FULL_POS)) +#define KYS_KEYFIFO_HALF KYS_KEYFIFO_HALF +#define KYS_KEYFIFO_HALF_POS (9U) +#define KYS_KEYFIFO_HALF_LEN (1U) +#define KYS_KEYFIFO_HALF_MSK (((1U << KYS_KEYFIFO_HALF_LEN) - 1) << KYS_KEYFIFO_HALF_POS) +#define KYS_KEYFIFO_HALF_UMSK (~(((1U << KYS_KEYFIFO_HALF_LEN) - 1) << KYS_KEYFIFO_HALF_POS)) +#define KYS_KEYFIFO_QUARTER KYS_KEYFIFO_QUARTER +#define KYS_KEYFIFO_QUARTER_POS (10U) +#define KYS_KEYFIFO_QUARTER_LEN (1U) +#define KYS_KEYFIFO_QUARTER_MSK (((1U << KYS_KEYFIFO_QUARTER_LEN) - 1) << KYS_KEYFIFO_QUARTER_POS) +#define KYS_KEYFIFO_QUARTER_UMSK (~(((1U << KYS_KEYFIFO_QUARTER_LEN) - 1) << KYS_KEYFIFO_QUARTER_POS)) +#define KYS_KEYFIFO_NONEMPTY KYS_KEYFIFO_NONEMPTY +#define KYS_KEYFIFO_NONEMPTY_POS (11U) +#define KYS_KEYFIFO_NONEMPTY_LEN (1U) +#define KYS_KEYFIFO_NONEMPTY_MSK (((1U << KYS_KEYFIFO_NONEMPTY_LEN) - 1) << KYS_KEYFIFO_NONEMPTY_POS) +#define KYS_KEYFIFO_NONEMPTY_UMSK (~(((1U << KYS_KEYFIFO_NONEMPTY_LEN) - 1) << KYS_KEYFIFO_NONEMPTY_POS)) +#define KYS_GHOST_DET KYS_GHOST_DET +#define KYS_GHOST_DET_POS (12U) +#define KYS_GHOST_DET_LEN (1U) +#define KYS_GHOST_DET_MSK (((1U << KYS_GHOST_DET_LEN) - 1) << KYS_GHOST_DET_POS) +#define KYS_GHOST_DET_UMSK (~(((1U << KYS_GHOST_DET_LEN) - 1) << KYS_GHOST_DET_POS)) + +/* 0x18 : keycode_clr */ +#define KYS_KEYCODE_CLR_OFFSET (0x18) +#define KYS_KS_DONE_CLR KYS_KS_DONE_CLR +#define KYS_KS_DONE_CLR_POS (7U) +#define KYS_KS_DONE_CLR_LEN (1U) +#define KYS_KS_DONE_CLR_MSK (((1U << KYS_KS_DONE_CLR_LEN) - 1) << KYS_KS_DONE_CLR_POS) +#define KYS_KS_DONE_CLR_UMSK (~(((1U << KYS_KS_DONE_CLR_LEN) - 1) << KYS_KS_DONE_CLR_POS)) +#define KYS_KEYFIFO_FULL_CLR KYS_KEYFIFO_FULL_CLR +#define KYS_KEYFIFO_FULL_CLR_POS (8U) +#define KYS_KEYFIFO_FULL_CLR_LEN (1U) +#define KYS_KEYFIFO_FULL_CLR_MSK (((1U << KYS_KEYFIFO_FULL_CLR_LEN) - 1) << KYS_KEYFIFO_FULL_CLR_POS) +#define KYS_KEYFIFO_FULL_CLR_UMSK (~(((1U << KYS_KEYFIFO_FULL_CLR_LEN) - 1) << KYS_KEYFIFO_FULL_CLR_POS)) +#define KYS_GHOST_CLR KYS_GHOST_CLR +#define KYS_GHOST_CLR_POS (12U) +#define KYS_GHOST_CLR_LEN (1U) +#define KYS_GHOST_CLR_MSK (((1U << KYS_GHOST_CLR_LEN) - 1) << KYS_GHOST_CLR_POS) +#define KYS_GHOST_CLR_UMSK (~(((1U << KYS_GHOST_CLR_LEN) - 1) << KYS_GHOST_CLR_POS)) + +/* 0x30 : keyfifo_idx */ +#define KYS_KEYFIFO_IDX_OFFSET (0x30) +#define KYS_KEYFIFO_HEAD KYS_KEYFIFO_HEAD +#define KYS_KEYFIFO_HEAD_POS (0U) +#define KYS_KEYFIFO_HEAD_LEN (3U) +#define KYS_KEYFIFO_HEAD_MSK (((1U << KYS_KEYFIFO_HEAD_LEN) - 1) << KYS_KEYFIFO_HEAD_POS) +#define KYS_KEYFIFO_HEAD_UMSK (~(((1U << KYS_KEYFIFO_HEAD_LEN) - 1) << KYS_KEYFIFO_HEAD_POS)) +#define KYS_KEYFIFO_TAIL KYS_KEYFIFO_TAIL +#define KYS_KEYFIFO_TAIL_POS (8U) +#define KYS_KEYFIFO_TAIL_LEN (3U) +#define KYS_KEYFIFO_TAIL_MSK (((1U << KYS_KEYFIFO_TAIL_LEN) - 1) << KYS_KEYFIFO_TAIL_POS) +#define KYS_KEYFIFO_TAIL_UMSK (~(((1U << KYS_KEYFIFO_TAIL_LEN) - 1) << KYS_KEYFIFO_TAIL_POS)) + +/* 0x34 : keyfifo_value */ +#define KYS_KEYFIFO_VALUE_OFFSET (0x34) +#define KYS_KEYFIFO_VALUE KYS_KEYFIFO_VALUE +#define KYS_KEYFIFO_VALUE_POS (0U) +#define KYS_KEYFIFO_VALUE_LEN (8U) +#define KYS_KEYFIFO_VALUE_MSK (((1U << KYS_KEYFIFO_VALUE_LEN) - 1) << KYS_KEYFIFO_VALUE_POS) +#define KYS_KEYFIFO_VALUE_UMSK (~(((1U << KYS_KEYFIFO_VALUE_LEN) - 1) << KYS_KEYFIFO_VALUE_POS)) + +/* 0x3C : ks_ctrl2 */ +#define KYS_KS_CTRL2_OFFSET (0x3C) +#define KYS_COL_START KYS_COL_START +#define KYS_COL_START_POS (0U) +#define KYS_COL_START_LEN (4U) +#define KYS_COL_START_MSK (((1U << KYS_COL_START_LEN) - 1) << KYS_COL_START_POS) +#define KYS_COL_START_UMSK (~(((1U << KYS_COL_START_LEN) - 1) << KYS_COL_START_POS)) +#define KYS_ROW_START KYS_ROW_START +#define KYS_ROW_START_POS (20U) +#define KYS_ROW_START_LEN (2U) +#define KYS_ROW_START_MSK (((1U << KYS_ROW_START_LEN) - 1) << KYS_ROW_START_POS) +#define KYS_ROW_START_UMSK (~(((1U << KYS_ROW_START_LEN) - 1) << KYS_ROW_START_POS)) + +struct kys_reg { + /* 0x0 : ks_ctrl */ + union { + struct { + uint32_t ks_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t fifo_mode : 1; /* [ 1], r/w, 0x0 */ + uint32_t ghost_en : 1; /* [ 2], r/w, 0x0 */ + uint32_t deg_en : 1; /* [ 3], r/w, 0x0 */ + uint32_t deg_cnt : 4; /* [ 7: 4], r/w, 0x0 */ + uint32_t rc_ext : 2; /* [ 9: 8], r/w, 0x3 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t row_num : 3; /* [18:16], r/w, 0x7 */ + uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ + uint32_t col_num : 3; /* [22:20], r/w, 0x7 */ + uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ks_ctrl; + + /* 0x4 reserved */ + uint8_t RESERVED0x4[12]; + + /* 0x10 : ks_int_en */ + union { + struct { + uint32_t reserved_0_6 : 7; /* [ 6: 0], rsvd, 0x0 */ + uint32_t ks_done_int_en : 1; /* [ 7], r/w, 0x1 */ + uint32_t keyfifo_int_en : 4; /* [11: 8], r/w, 0x0 */ + uint32_t ghost_int_en : 1; /* [ 12], r/w, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ks_int_en; + + /* 0x14 : ks_int_sts */ + union { + struct { + uint32_t reserved_0_6 : 7; /* [ 6: 0], rsvd, 0x0 */ + uint32_t ks_done : 1; /* [ 7], r, 0x0 */ + uint32_t keyfifo_full : 1; /* [ 8], r, 0x0 */ + uint32_t keyfifo_half : 1; /* [ 9], r, 0x0 */ + uint32_t keyfifo_quarter : 1; /* [ 10], r, 0x0 */ + uint32_t keyfifo_nonempty : 1; /* [ 11], r, 0x0 */ + uint32_t ghost_det : 1; /* [ 12], r, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } ks_int_sts; + + /* 0x18 : keycode_clr */ + union { + struct { + uint32_t reserved_0_6 : 7; /* [ 6: 0], rsvd, 0x0 */ + uint32_t ks_done_clr : 1; /* [ 7], w1c, 0x0 */ + uint32_t keyfifo_clr : 1; /* [ 8], w1c, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t ghost_clr : 1; /* [ 12], w1c, 0x0 */ + uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } keycode_clr; + + /* 0x1C : reserved */ + uint8_t RESERVED0x1C[20]; + + /* 0x30 : keyfifo_idx */ + union { + struct { + uint32_t keyfifo_head : 3; /* [ 2: 0], r, 0x0 */ + uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ + uint32_t keyfifo_tail : 3; /* [10: 8], r, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } keyfifo_idx; + + /* 0x34 : keyfifo_value */ + union { + struct { + uint32_t keyfifo_value : 8; /* [ 7: 0], r, 0xff */ + uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } keyfifo_value; +}; + +typedef volatile struct kys_reg kys_reg_t; + +#endif /* __KYS_REG_H__ */ diff --git a/drivers/soc/bl702l/std/include/hardware/l1c_reg.h b/drivers/soc/bl702l/std/include/hardware/l1c_reg.h new file mode 100644 index 000000000..65479127a --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/l1c_reg.h @@ -0,0 +1,331 @@ +/** + ****************************************************************************** + * @file l1c_reg.h + * @version V1.0 + * @date 2022-06-28 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __L1C_REG_H__ +#define __L1C_REG_H__ + +#include "bl702l.h" + +/* 0x0 : l1c_config */ +#define L1C_CONFIG_OFFSET (0x0) +#define L1C_CACHEABLE L1C_CACHEABLE +#define L1C_CACHEABLE_POS (0U) +#define L1C_CACHEABLE_LEN (1U) +#define L1C_CACHEABLE_MSK (((1U<
© COPYRIGHT(c) 2019 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDM_REG_H__ +#define __PDM_REG_H__ + +#include "bl702l.h" + +/* 0x0 : pdm_datapath_config */ +#define PDM_DATAPATH_CONFIG_OFFSET (0x0) +#define PDM_EN PDM_EN +#define PDM_EN_POS (0U) +#define PDM_EN_LEN (1U) +#define PDM_EN_MSK (((1U << PDM_EN_LEN) - 1) << PDM_EN_POS) +#define PDM_EN_UMSK (~(((1U << PDM_EN_LEN) - 1) << PDM_EN_POS)) +#define PDM_RX_SEL_128FS PDM_RX_SEL_128FS +#define PDM_RX_SEL_128FS_POS (2U) +#define PDM_RX_SEL_128FS_LEN (1U) +#define PDM_RX_SEL_128FS_MSK (((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS) +#define PDM_RX_SEL_128FS_UMSK (~(((1U << PDM_RX_SEL_128FS_LEN) - 1) << PDM_RX_SEL_128FS_POS)) +#define PDM_TX_SEL_128FS PDM_TX_SEL_128FS +#define PDM_TX_SEL_128FS_POS (3U) +#define PDM_TX_SEL_128FS_LEN (1U) +#define PDM_TX_SEL_128FS_MSK (((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS) +#define PDM_TX_SEL_128FS_UMSK (~(((1U << PDM_TX_SEL_128FS_LEN) - 1) << PDM_TX_SEL_128FS_POS)) +#define PDM_DC_MUL PDM_DC_MUL +#define PDM_DC_MUL_POS (4U) +#define PDM_DC_MUL_LEN (8U) +#define PDM_DC_MUL_MSK (((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS) +#define PDM_DC_MUL_UMSK (~(((1U << PDM_DC_MUL_LEN) - 1) << PDM_DC_MUL_POS)) +#define PDM_SCALE_SEL PDM_SCALE_SEL +#define PDM_SCALE_SEL_POS (12U) +#define PDM_SCALE_SEL_LEN (3U) +#define PDM_SCALE_SEL_MSK (((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS) +#define PDM_SCALE_SEL_UMSK (~(((1U << PDM_SCALE_SEL_LEN) - 1) << PDM_SCALE_SEL_POS)) +#define PDM_DITHER_SEL PDM_DITHER_SEL +#define PDM_DITHER_SEL_POS (16U) +#define PDM_DITHER_SEL_LEN (2U) +#define PDM_DITHER_SEL_MSK (((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS) +#define PDM_DITHER_SEL_UMSK (~(((1U << PDM_DITHER_SEL_LEN) - 1) << PDM_DITHER_SEL_POS)) +#define PDM_FORCE_LR PDM_FORCE_LR +#define PDM_FORCE_LR_POS (20U) +#define PDM_FORCE_LR_LEN (1U) +#define PDM_FORCE_LR_MSK (((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS) +#define PDM_FORCE_LR_UMSK (~(((1U << PDM_FORCE_LR_LEN) - 1) << PDM_FORCE_LR_POS)) +#define PDM_FORCE_SEL PDM_FORCE_SEL +#define PDM_FORCE_SEL_POS (21U) +#define PDM_FORCE_SEL_LEN (1U) +#define PDM_FORCE_SEL_MSK (((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS) +#define PDM_FORCE_SEL_UMSK (~(((1U << PDM_FORCE_SEL_LEN) - 1) << PDM_FORCE_SEL_POS)) +#define PDM_DSD_SWAP PDM_DSD_SWAP +#define PDM_DSD_SWAP_POS (22U) +#define PDM_DSD_SWAP_LEN (1U) +#define PDM_DSD_SWAP_MSK (((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS) +#define PDM_DSD_SWAP_UMSK (~(((1U << PDM_DSD_SWAP_LEN) - 1) << PDM_DSD_SWAP_POS)) +#define PDM_OUT_DAT_DLY PDM_OUT_DAT_DLY +#define PDM_OUT_DAT_DLY_POS (24U) +#define PDM_OUT_DAT_DLY_LEN (2U) +#define PDM_OUT_DAT_DLY_MSK (((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS) +#define PDM_OUT_DAT_DLY_UMSK (~(((1U << PDM_OUT_DAT_DLY_LEN) - 1) << PDM_OUT_DAT_DLY_POS)) +#define PDM_OUT_SEL_DLY PDM_OUT_SEL_DLY +#define PDM_OUT_SEL_DLY_POS (26U) +#define PDM_OUT_SEL_DLY_LEN (2U) +#define PDM_OUT_SEL_DLY_MSK (((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS) +#define PDM_OUT_SEL_DLY_UMSK (~(((1U << PDM_OUT_SEL_DLY_LEN) - 1) << PDM_OUT_SEL_DLY_POS)) +#define PDM_OUT_SEL_INV PDM_OUT_SEL_INV +#define PDM_OUT_SEL_INV_POS (28U) +#define PDM_OUT_SEL_INV_LEN (1U) +#define PDM_OUT_SEL_INV_MSK (((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS) +#define PDM_OUT_SEL_INV_UMSK (~(((1U << PDM_OUT_SEL_INV_LEN) - 1) << PDM_OUT_SEL_INV_POS)) + +/* 0x4 : pdm_dma_config */ +#define PDM_DMA_CONFIG_OFFSET (0x4) +#define PDM_DMA_RX_EN PDM_DMA_RX_EN +#define PDM_DMA_RX_EN_POS (0U) +#define PDM_DMA_RX_EN_LEN (1U) +#define PDM_DMA_RX_EN_MSK (((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS) +#define PDM_DMA_RX_EN_UMSK (~(((1U << PDM_DMA_RX_EN_LEN) - 1) << PDM_DMA_RX_EN_POS)) +#define PDM_RX_FORMAT PDM_RX_FORMAT +#define PDM_RX_FORMAT_POS (4U) +#define PDM_RX_FORMAT_LEN (3U) +#define PDM_RX_FORMAT_MSK (((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS) +#define PDM_RX_FORMAT_UMSK (~(((1U << PDM_RX_FORMAT_LEN) - 1) << PDM_RX_FORMAT_POS)) +#define PDM_DMA_TX_EN PDM_DMA_TX_EN +#define PDM_DMA_TX_EN_POS (8U) +#define PDM_DMA_TX_EN_LEN (1U) +#define PDM_DMA_TX_EN_MSK (((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS) +#define PDM_DMA_TX_EN_UMSK (~(((1U << PDM_DMA_TX_EN_LEN) - 1) << PDM_DMA_TX_EN_POS)) +#define PDM_TX_FORMAT PDM_TX_FORMAT +#define PDM_TX_FORMAT_POS (12U) +#define PDM_TX_FORMAT_LEN (3U) +#define PDM_TX_FORMAT_MSK (((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS) +#define PDM_TX_FORMAT_UMSK (~(((1U << PDM_TX_FORMAT_LEN) - 1) << PDM_TX_FORMAT_POS)) +#define PDM_TX_DATA_SHIFT PDM_TX_DATA_SHIFT +#define PDM_TX_DATA_SHIFT_POS (16U) +#define PDM_TX_DATA_SHIFT_LEN (5U) +#define PDM_TX_DATA_SHIFT_MSK (((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS) +#define PDM_TX_DATA_SHIFT_UMSK (~(((1U << PDM_TX_DATA_SHIFT_LEN) - 1) << PDM_TX_DATA_SHIFT_POS)) + +/* 0x8 : pdm_dma_wdata2 */ +#define PDM_DMA_WDATA2_OFFSET (0x8) +#define PDM_DMA_WDATA2 PDM_DMA_WDATA2 +#define PDM_DMA_WDATA2_POS (0U) +#define PDM_DMA_WDATA2_LEN (32U) +#define PDM_DMA_WDATA2_MSK (((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS) +#define PDM_DMA_WDATA2_UMSK (~(((1U << PDM_DMA_WDATA2_LEN) - 1) << PDM_DMA_WDATA2_POS)) + +/* 0x10 : pdm_dma_wdata */ +#define PDM_DMA_WDATA_OFFSET (0x10) +#define PDM_DMA_WDATA PDM_DMA_WDATA +#define PDM_DMA_WDATA_POS (0U) +#define PDM_DMA_WDATA_LEN (32U) +#define PDM_DMA_WDATA_MSK (((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS) +#define PDM_DMA_WDATA_UMSK (~(((1U << PDM_DMA_WDATA_LEN) - 1) << PDM_DMA_WDATA_POS)) + +/* 0x14 : pdm_dma_rdata */ +#define PDM_DMA_RDATA_OFFSET (0x14) +#define PDM_DMA_RDATA PDM_DMA_RDATA +#define PDM_DMA_RDATA_POS (0U) +#define PDM_DMA_RDATA_LEN (32U) +#define PDM_DMA_RDATA_MSK (((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS) +#define PDM_DMA_RDATA_UMSK (~(((1U << PDM_DMA_RDATA_LEN) - 1) << PDM_DMA_RDATA_POS)) + +/* 0x18 : pdm_tx_fifo_status */ +#define PDM_TX_FIFO_STATUS_OFFSET (0x18) +#define PDM_TX_FIFO_EMPTY PDM_TX_FIFO_EMPTY +#define PDM_TX_FIFO_EMPTY_POS (0U) +#define PDM_TX_FIFO_EMPTY_LEN (1U) +#define PDM_TX_FIFO_EMPTY_MSK (((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS) +#define PDM_TX_FIFO_EMPTY_UMSK (~(((1U << PDM_TX_FIFO_EMPTY_LEN) - 1) << PDM_TX_FIFO_EMPTY_POS)) +#define PDM_TX_FIFO_FULL PDM_TX_FIFO_FULL +#define PDM_TX_FIFO_FULL_POS (1U) +#define PDM_TX_FIFO_FULL_LEN (1U) +#define PDM_TX_FIFO_FULL_MSK (((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS) +#define PDM_TX_FIFO_FULL_UMSK (~(((1U << PDM_TX_FIFO_FULL_LEN) - 1) << PDM_TX_FIFO_FULL_POS)) +#define PDM_TX_CS PDM_TX_CS +#define PDM_TX_CS_POS (2U) +#define PDM_TX_CS_LEN (2U) +#define PDM_TX_CS_MSK (((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS) +#define PDM_TX_CS_UMSK (~(((1U << PDM_TX_CS_LEN) - 1) << PDM_TX_CS_POS)) +#define PDM_TXFIFORDPTR PDM_TXFIFORDPTR +#define PDM_TXFIFORDPTR_POS (4U) +#define PDM_TXFIFORDPTR_LEN (3U) +#define PDM_TXFIFORDPTR_MSK (((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS) +#define PDM_TXFIFORDPTR_UMSK (~(((1U << PDM_TXFIFORDPTR_LEN) - 1) << PDM_TXFIFORDPTR_POS)) +#define PDM_TXFIFOWRPTR PDM_TXFIFOWRPTR +#define PDM_TXFIFOWRPTR_POS (8U) +#define PDM_TXFIFOWRPTR_LEN (2U) +#define PDM_TXFIFOWRPTR_MSK (((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS) +#define PDM_TXFIFOWRPTR_UMSK (~(((1U << PDM_TXFIFOWRPTR_LEN) - 1) << PDM_TXFIFOWRPTR_POS)) +#define PDM_TX2_FIFO_EMPTY PDM_TX2_FIFO_EMPTY +#define PDM_TX2_FIFO_EMPTY_POS (16U) +#define PDM_TX2_FIFO_EMPTY_LEN (1U) +#define PDM_TX2_FIFO_EMPTY_MSK (((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS) +#define PDM_TX2_FIFO_EMPTY_UMSK (~(((1U << PDM_TX2_FIFO_EMPTY_LEN) - 1) << PDM_TX2_FIFO_EMPTY_POS)) +#define PDM_TX2_FIFO_FULL PDM_TX2_FIFO_FULL +#define PDM_TX2_FIFO_FULL_POS (17U) +#define PDM_TX2_FIFO_FULL_LEN (1U) +#define PDM_TX2_FIFO_FULL_MSK (((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS) +#define PDM_TX2_FIFO_FULL_UMSK (~(((1U << PDM_TX2_FIFO_FULL_LEN) - 1) << PDM_TX2_FIFO_FULL_POS)) +#define PDM_TX2_CS PDM_TX2_CS +#define PDM_TX2_CS_POS (18U) +#define PDM_TX2_CS_LEN (2U) +#define PDM_TX2_CS_MSK (((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS) +#define PDM_TX2_CS_UMSK (~(((1U << PDM_TX2_CS_LEN) - 1) << PDM_TX2_CS_POS)) +#define PDM_TX2FIFORDPTR PDM_TX2FIFORDPTR +#define PDM_TX2FIFORDPTR_POS (20U) +#define PDM_TX2FIFORDPTR_LEN (3U) +#define PDM_TX2FIFORDPTR_MSK (((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS) +#define PDM_TX2FIFORDPTR_UMSK (~(((1U << PDM_TX2FIFORDPTR_LEN) - 1) << PDM_TX2FIFORDPTR_POS)) +#define PDM_TX2FIFOWRPTR PDM_TX2FIFOWRPTR +#define PDM_TX2FIFOWRPTR_POS (24U) +#define PDM_TX2FIFOWRPTR_LEN (2U) +#define PDM_TX2FIFOWRPTR_MSK (((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS) +#define PDM_TX2FIFOWRPTR_UMSK (~(((1U << PDM_TX2FIFOWRPTR_LEN) - 1) << PDM_TX2FIFOWRPTR_POS)) + +/* 0x1C : pdm_rx_fifo_status */ +#define PDM_RX_FIFO_STATUS_OFFSET (0x1C) +#define PDM_RX_FIFO_EMPTY PDM_RX_FIFO_EMPTY +#define PDM_RX_FIFO_EMPTY_POS (0U) +#define PDM_RX_FIFO_EMPTY_LEN (1U) +#define PDM_RX_FIFO_EMPTY_MSK (((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS) +#define PDM_RX_FIFO_EMPTY_UMSK (~(((1U << PDM_RX_FIFO_EMPTY_LEN) - 1) << PDM_RX_FIFO_EMPTY_POS)) +#define PDM_RX_FIFO_FULL PDM_RX_FIFO_FULL +#define PDM_RX_FIFO_FULL_POS (1U) +#define PDM_RX_FIFO_FULL_LEN (1U) +#define PDM_RX_FIFO_FULL_MSK (((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS) +#define PDM_RX_FIFO_FULL_UMSK (~(((1U << PDM_RX_FIFO_FULL_LEN) - 1) << PDM_RX_FIFO_FULL_POS)) +#define PDM_RX_CS PDM_RX_CS +#define PDM_RX_CS_POS (2U) +#define PDM_RX_CS_LEN (2U) +#define PDM_RX_CS_MSK (((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS) +#define PDM_RX_CS_UMSK (~(((1U << PDM_RX_CS_LEN) - 1) << PDM_RX_CS_POS)) +#define PDM_RXFIFORDPTR PDM_RXFIFORDPTR +#define PDM_RXFIFORDPTR_POS (4U) +#define PDM_RXFIFORDPTR_LEN (2U) +#define PDM_RXFIFORDPTR_MSK (((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS) +#define PDM_RXFIFORDPTR_UMSK (~(((1U << PDM_RXFIFORDPTR_LEN) - 1) << PDM_RXFIFORDPTR_POS)) +#define PDM_RXFIFOWRPTR PDM_RXFIFOWRPTR +#define PDM_RXFIFOWRPTR_POS (8U) +#define PDM_RXFIFOWRPTR_LEN (3U) +#define PDM_RXFIFOWRPTR_MSK (((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS) +#define PDM_RXFIFOWRPTR_UMSK (~(((1U << PDM_RXFIFOWRPTR_LEN) - 1) << PDM_RXFIFOWRPTR_POS)) + +struct pdm_reg { + /* 0x0 : pdm_datapath_config */ + union { + struct + { + uint32_t pdm_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ + uint32_t rx_sel_128fs : 1; /* [ 2], r/w, 0x0 */ + uint32_t tx_sel_128fs : 1; /* [ 3], r/w, 0x0 */ + uint32_t dc_mul : 8; /* [11: 4], r/w, 0x64 */ + uint32_t scale_sel : 3; /* [14:12], r/w, 0x5 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t dither_sel : 2; /* [17:16], r/w, 0x1 */ + uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ + uint32_t force_lr : 1; /* [ 20], r/w, 0x0 */ + uint32_t force_sel : 1; /* [ 21], r/w, 0x0 */ + uint32_t dsd_swap : 1; /* [ 22], r/w, 0x0 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t out_dat_dly : 2; /* [25:24], r/w, 0x0 */ + uint32_t out_sel_dly : 2; /* [27:26], r/w, 0x0 */ + uint32_t out_sel_inv : 1; /* [ 28], r/w, 0x0 */ + uint32_t rsvd_31_29 : 3; /* [31:29], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_datapath_config; + + /* 0x4 : pdm_dma_config */ + union { + struct + { + uint32_t pdm_dma_rx_en : 1; /* [ 0], r/w, 0x0 */ + uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ + uint32_t rx_format : 3; /* [ 6: 4], r/w, 0x3 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t pdm_dma_tx_en : 1; /* [ 8], r/w, 0x0 */ + uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ + uint32_t tx_format : 3; /* [14:12], r/w, 0x3 */ + uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ + uint32_t tx_data_shift : 5; /* [20:16], r/w, 0x0 */ + uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_dma_config; + + /* 0x8 : pdm_dma_wdata2 */ + union { + struct + { + uint32_t pdm_dma_wdata2 : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } pdm_dma_wdata2; + + /* 0xc reserved */ + uint8_t RESERVED0xc[4]; + + /* 0x10 : pdm_dma_wdata */ + union { + struct + { + uint32_t pdm_dma_wdata : 32; /* [31: 0], w, x */ + } BF; + uint32_t WORD; + } pdm_dma_wdata; + + /* 0x14 : pdm_dma_rdata */ + union { + struct + { + uint32_t pdm_dma_rdata : 32; /* [31: 0], r, 0x0 */ + } BF; + uint32_t WORD; + } pdm_dma_rdata; + + /* 0x18 : pdm_tx_fifo_status */ + union { + struct + { + uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */ + uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */ + uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */ + uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */ + uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ + uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */ + uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ + uint32_t tx2_fifo_empty : 1; /* [ 16], r, 0x0 */ + uint32_t tx2_fifo_full : 1; /* [ 17], r, 0x0 */ + uint32_t tx2_cs : 2; /* [19:18], r, 0x0 */ + uint32_t Tx2FifoRdPtr : 3; /* [22:20], r, 0x4 */ + uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ + uint32_t Tx2FifoWrPtr : 2; /* [25:24], r, 0x0 */ + uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_tx_fifo_status; + + /* 0x1C : pdm_rx_fifo_status */ + union { + struct + { + uint32_t rx_fifo_empty : 1; /* [ 0], r, 0x1 */ + uint32_t rx_fifo_full : 1; /* [ 1], r, 0x0 */ + uint32_t rx_cs : 2; /* [ 3: 2], r, 0x0 */ + uint32_t RxFifoRdPtr : 2; /* [ 5: 4], r, 0x3 */ + uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ + uint32_t RxFifoWrPtr : 3; /* [10: 8], r, 0x0 */ + uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ + } BF; + uint32_t WORD; + } pdm_rx_fifo_status; +}; + +typedef volatile struct pdm_reg pdm_reg_t; + +#endif /* __PDM_REG_H__ */ diff --git a/drivers/soc/bl702l/std/include/hardware/pds_reg.h b/drivers/soc/bl702l/std/include/hardware/pds_reg.h new file mode 100644 index 000000000..bb2d30049 --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/pds_reg.h @@ -0,0 +1,1826 @@ +/** + ****************************************************************************** + * @file pds_reg.h + * @version V1.0 + * @date 2022-07-01 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __PDS_REG_H__ +#define __PDS_REG_H__ + +#include "bl702l.h" + +/* 0x0 : PDS_CTL */ +#define PDS_CTL_OFFSET (0x0) +#define PDS_START_PS PDS_START_PS +#define PDS_START_PS_POS (0U) +#define PDS_START_PS_LEN (1U) +#define PDS_START_PS_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SF_CTRL_REG_H__ +#define __SF_CTRL_REG_H__ + +#include "bl702l.h" + +/* 0x0 : sf_ctrl_0 */ +#define SF_CTRL_0_OFFSET (0x0) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U) +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TZC_NSEC_REG_H__ +#define __TZC_NSEC_REG_H__ + +#include "bl702l.h" + +/* 0x40 : tzc_rom_ctrl */ +#define TZC_NSEC_TZC_ROM_CTRL_OFFSET (0x40) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN TZC_NSEC_TZC_ROM0_R0_ID0_EN +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS (0U) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_MSK (((1U << TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS) +#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS)) +#define TZC_NSEC_TZC_ROM0_R1_ID0_EN TZC_NSEC_TZC_ROM0_R1_ID0_EN +#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_POS (1U) +#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_MSK (((1U << TZC_NSEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_ID0_EN_POS) +#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_ID0_EN_POS)) +#define TZC_NSEC_TZC_ROM1_R0_ID0_EN TZC_NSEC_TZC_ROM1_R0_ID0_EN +#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_POS (2U) +#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_MSK (((1U << TZC_NSEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_ID0_EN_POS) +#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_ID0_EN_POS)) +#define TZC_NSEC_TZC_ROM1_R1_ID0_EN TZC_NSEC_TZC_ROM1_R1_ID0_EN +#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_POS (3U) +#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_MSK (((1U << TZC_NSEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_ID0_EN_POS) +#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_ID0_EN_POS)) +#define TZC_NSEC_TZC_ROM0_R0_ID1_EN TZC_NSEC_TZC_ROM0_R0_ID1_EN +#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_POS (8U) +#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_MSK (((1U << TZC_NSEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_ID1_EN_POS) +#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_ID1_EN_POS)) +#define TZC_NSEC_TZC_ROM0_R1_ID1_EN TZC_NSEC_TZC_ROM0_R1_ID1_EN +#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_POS (9U) +#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_MSK (((1U << TZC_NSEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_ID1_EN_POS) +#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_ID1_EN_POS)) +#define TZC_NSEC_TZC_ROM1_R0_ID1_EN TZC_NSEC_TZC_ROM1_R0_ID1_EN +#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_POS (10U) +#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_MSK (((1U << TZC_NSEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_ID1_EN_POS) +#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_ID1_EN_POS)) +#define TZC_NSEC_TZC_ROM1_R1_ID1_EN TZC_NSEC_TZC_ROM1_R1_ID1_EN +#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_POS (11U) +#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_MSK (((1U << TZC_NSEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_ID1_EN_POS) +#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_ID1_EN_POS)) +#define TZC_NSEC_TZC_ROM0_R0_EN TZC_NSEC_TZC_ROM0_R0_EN +#define TZC_NSEC_TZC_ROM0_R0_EN_POS (16U) +#define TZC_NSEC_TZC_ROM0_R0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R0_EN_MSK (((1U << TZC_NSEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_EN_POS) +#define TZC_NSEC_TZC_ROM0_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_EN_POS)) +#define TZC_NSEC_TZC_ROM0_R1_EN TZC_NSEC_TZC_ROM0_R1_EN +#define TZC_NSEC_TZC_ROM0_R1_EN_POS (17U) +#define TZC_NSEC_TZC_ROM0_R1_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R1_EN_MSK (((1U << TZC_NSEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_EN_POS) +#define TZC_NSEC_TZC_ROM0_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_EN_POS)) +#define TZC_NSEC_TZC_ROM1_R0_EN TZC_NSEC_TZC_ROM1_R0_EN +#define TZC_NSEC_TZC_ROM1_R0_EN_POS (18U) +#define TZC_NSEC_TZC_ROM1_R0_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R0_EN_MSK (((1U << TZC_NSEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_EN_POS) +#define TZC_NSEC_TZC_ROM1_R0_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_EN_POS)) +#define TZC_NSEC_TZC_ROM1_R1_EN TZC_NSEC_TZC_ROM1_R1_EN +#define TZC_NSEC_TZC_ROM1_R1_EN_POS (19U) +#define TZC_NSEC_TZC_ROM1_R1_EN_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R1_EN_MSK (((1U << TZC_NSEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_EN_POS) +#define TZC_NSEC_TZC_ROM1_R1_EN_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_EN_POS)) +#define TZC_NSEC_TZC_ROM0_R0_LOCK TZC_NSEC_TZC_ROM0_R0_LOCK +#define TZC_NSEC_TZC_ROM0_R0_LOCK_POS (24U) +#define TZC_NSEC_TZC_ROM0_R0_LOCK_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_LOCK_POS) +#define TZC_NSEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_LOCK_POS)) +#define TZC_NSEC_TZC_ROM0_R1_LOCK TZC_NSEC_TZC_ROM0_R1_LOCK +#define TZC_NSEC_TZC_ROM0_R1_LOCK_POS (25U) +#define TZC_NSEC_TZC_ROM0_R1_LOCK_LEN (1U) +#define TZC_NSEC_TZC_ROM0_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_LOCK_POS) +#define TZC_NSEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_LOCK_POS)) +#define TZC_NSEC_TZC_ROM1_R0_LOCK TZC_NSEC_TZC_ROM1_R0_LOCK +#define TZC_NSEC_TZC_ROM1_R0_LOCK_POS (26U) +#define TZC_NSEC_TZC_ROM1_R0_LOCK_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R0_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_LOCK_POS) +#define TZC_NSEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_LOCK_POS)) +#define TZC_NSEC_TZC_ROM1_R1_LOCK TZC_NSEC_TZC_ROM1_R1_LOCK +#define TZC_NSEC_TZC_ROM1_R1_LOCK_POS (27U) +#define TZC_NSEC_TZC_ROM1_R1_LOCK_LEN (1U) +#define TZC_NSEC_TZC_ROM1_R1_LOCK_MSK (((1U << TZC_NSEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_LOCK_POS) +#define TZC_NSEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_LOCK_POS)) +#define TZC_NSEC_TZC_SBOOT_DONE TZC_NSEC_TZC_SBOOT_DONE +#define TZC_NSEC_TZC_SBOOT_DONE_POS (28U) +#define TZC_NSEC_TZC_SBOOT_DONE_LEN (4U) +#define TZC_NSEC_TZC_SBOOT_DONE_MSK (((1U << TZC_NSEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_NSEC_TZC_SBOOT_DONE_POS) +#define TZC_NSEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_NSEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_NSEC_TZC_SBOOT_DONE_POS)) + +/* 0x44 : tzc_rom0_r0 */ +#define TZC_NSEC_TZC_ROM0_R0_OFFSET (0x44) +#define TZC_NSEC_TZC_ROM0_R0_END TZC_NSEC_TZC_ROM0_R0_END +#define TZC_NSEC_TZC_ROM0_R0_END_POS (0U) +#define TZC_NSEC_TZC_ROM0_R0_END_LEN (16U) +#define TZC_NSEC_TZC_ROM0_R0_END_MSK (((1U << TZC_NSEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_END_POS) +#define TZC_NSEC_TZC_ROM0_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_END_POS)) +#define TZC_NSEC_TZC_ROM0_R0_START TZC_NSEC_TZC_ROM0_R0_START +#define TZC_NSEC_TZC_ROM0_R0_START_POS (16U) +#define TZC_NSEC_TZC_ROM0_R0_START_LEN (16U) +#define TZC_NSEC_TZC_ROM0_R0_START_MSK (((1U << TZC_NSEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_START_POS) +#define TZC_NSEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_NSEC_TZC_ROM0_R0_START_POS)) + +/* 0x48 : tzc_rom0_r1 */ +#define TZC_NSEC_TZC_ROM0_R1_OFFSET (0x48) +#define TZC_NSEC_TZC_ROM0_R1_END TZC_NSEC_TZC_ROM0_R1_END +#define TZC_NSEC_TZC_ROM0_R1_END_POS (0U) +#define TZC_NSEC_TZC_ROM0_R1_END_LEN (16U) +#define TZC_NSEC_TZC_ROM0_R1_END_MSK (((1U << TZC_NSEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_END_POS) +#define TZC_NSEC_TZC_ROM0_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_END_POS)) +#define TZC_NSEC_TZC_ROM0_R1_START TZC_NSEC_TZC_ROM0_R1_START +#define TZC_NSEC_TZC_ROM0_R1_START_POS (16U) +#define TZC_NSEC_TZC_ROM0_R1_START_LEN (16U) +#define TZC_NSEC_TZC_ROM0_R1_START_MSK (((1U << TZC_NSEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_START_POS) +#define TZC_NSEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_NSEC_TZC_ROM0_R1_START_POS)) + +/* 0x4C : tzc_rom1_r0 */ +#define TZC_NSEC_TZC_ROM1_R0_OFFSET (0x4C) +#define TZC_NSEC_TZC_ROM1_R0_END TZC_NSEC_TZC_ROM1_R0_END +#define TZC_NSEC_TZC_ROM1_R0_END_POS (0U) +#define TZC_NSEC_TZC_ROM1_R0_END_LEN (16U) +#define TZC_NSEC_TZC_ROM1_R0_END_MSK (((1U << TZC_NSEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_END_POS) +#define TZC_NSEC_TZC_ROM1_R0_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_END_POS)) +#define TZC_NSEC_TZC_ROM1_R0_START TZC_NSEC_TZC_ROM1_R0_START +#define TZC_NSEC_TZC_ROM1_R0_START_POS (16U) +#define TZC_NSEC_TZC_ROM1_R0_START_LEN (16U) +#define TZC_NSEC_TZC_ROM1_R0_START_MSK (((1U << TZC_NSEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_START_POS) +#define TZC_NSEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_NSEC_TZC_ROM1_R0_START_POS)) + +/* 0x50 : tzc_rom1_r1 */ +#define TZC_NSEC_TZC_ROM1_R1_OFFSET (0x50) +#define TZC_NSEC_TZC_ROM1_R1_END TZC_NSEC_TZC_ROM1_R1_END +#define TZC_NSEC_TZC_ROM1_R1_END_POS (0U) +#define TZC_NSEC_TZC_ROM1_R1_END_LEN (16U) +#define TZC_NSEC_TZC_ROM1_R1_END_MSK (((1U << TZC_NSEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_END_POS) +#define TZC_NSEC_TZC_ROM1_R1_END_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_END_POS)) +#define TZC_NSEC_TZC_ROM1_R1_START TZC_NSEC_TZC_ROM1_R1_START +#define TZC_NSEC_TZC_ROM1_R1_START_POS (16U) +#define TZC_NSEC_TZC_ROM1_R1_START_LEN (16U) +#define TZC_NSEC_TZC_ROM1_R1_START_MSK (((1U << TZC_NSEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_START_POS) +#define TZC_NSEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_NSEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_NSEC_TZC_ROM1_R1_START_POS)) + +struct tzc_nsec_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[64]; + + /* 0x40 : tzc_rom_ctrl */ + union { + struct { + uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r, 0x1 */ + uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r, 0x1 */ + uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r, 0x1 */ + uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r, 0x1 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r, 0x1 */ + uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r, 0x1 */ + uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r, 0x1 */ + uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r, 0x1 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_en : 1; /* [ 16], r, 0x0 */ + uint32_t tzc_rom0_r1_en : 1; /* [ 17], r, 0x0 */ + uint32_t tzc_rom1_r0_en : 1; /* [ 18], r, 0x0 */ + uint32_t tzc_rom1_r1_en : 1; /* [ 19], r, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r, 0x0 */ + uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r, 0x0 */ + uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r, 0x0 */ + uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r, 0x0 */ + uint32_t tzc_sboot_done : 4; /* [31:28], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom_ctrl; + + /* 0x44 : tzc_rom0_r0 */ + union { + struct { + uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r, 0xffff */ + uint32_t tzc_rom0_r0_start : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r0; + + /* 0x48 : tzc_rom0_r1 */ + union { + struct { + uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r, 0xffff */ + uint32_t tzc_rom0_r1_start : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r1; + + /* 0x4C : tzc_rom1_r0 */ + union { + struct { + uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r, 0xffff */ + uint32_t tzc_rom1_r0_start : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r0; + + /* 0x50 : tzc_rom1_r1 */ + union { + struct { + uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r, 0xffff */ + uint32_t tzc_rom1_r1_start : 16; /* [31:16], r, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r1; +}; + +typedef volatile struct tzc_nsec_reg tzc_nsec_reg_t; + +#endif /* __TZC_NSEC_REG_H__ */ diff --git a/drivers/soc/bl702l/std/include/hardware/tzc_sec_reg.h b/drivers/soc/bl702l/std/include/hardware/tzc_sec_reg.h new file mode 100644 index 000000000..6e0558364 --- /dev/null +++ b/drivers/soc/bl702l/std/include/hardware/tzc_sec_reg.h @@ -0,0 +1,251 @@ +/** + ****************************************************************************** + * @file tzc_sec_reg.h + * @version V1.0 + * @date 2022-05-16 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __TZC_SEC_REG_H__ +#define __TZC_SEC_REG_H__ + +#include "bl702l.h" + +/* 0x40 : tzc_rom_ctrl */ +#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN TZC_SEC_TZC_ROM0_R1_ID0_EN +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS (1U) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN TZC_SEC_TZC_ROM1_R0_ID0_EN +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS (2U) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN TZC_SEC_TZC_ROM1_R1_ID0_EN +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS (3U) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN TZC_SEC_TZC_ROM0_R0_ID1_EN +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS (8U) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN TZC_SEC_TZC_ROM0_R1_ID1_EN +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS (9U) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN TZC_SEC_TZC_ROM1_R0_ID1_EN +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS (10U) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN TZC_SEC_TZC_ROM1_R1_ID1_EN +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS (11U) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_EN TZC_SEC_TZC_ROM0_R0_EN +#define TZC_SEC_TZC_ROM0_R0_EN_POS (16U) +#define TZC_SEC_TZC_ROM0_R0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS) +#define TZC_SEC_TZC_ROM0_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)) +#define TZC_SEC_TZC_ROM0_R1_EN TZC_SEC_TZC_ROM0_R1_EN +#define TZC_SEC_TZC_ROM0_R1_EN_POS (17U) +#define TZC_SEC_TZC_ROM0_R1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS) +#define TZC_SEC_TZC_ROM0_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)) +#define TZC_SEC_TZC_ROM1_R0_EN TZC_SEC_TZC_ROM1_R0_EN +#define TZC_SEC_TZC_ROM1_R0_EN_POS (18U) +#define TZC_SEC_TZC_ROM1_R0_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS) +#define TZC_SEC_TZC_ROM1_R0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)) +#define TZC_SEC_TZC_ROM1_R1_EN TZC_SEC_TZC_ROM1_R1_EN +#define TZC_SEC_TZC_ROM1_R1_EN_POS (19U) +#define TZC_SEC_TZC_ROM1_R1_EN_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_EN_MSK (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS) +#define TZC_SEC_TZC_ROM1_R1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)) +#define TZC_SEC_TZC_ROM0_R0_LOCK TZC_SEC_TZC_ROM0_R0_LOCK +#define TZC_SEC_TZC_ROM0_R0_LOCK_POS (24U) +#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS) +#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)) +#define TZC_SEC_TZC_ROM0_R1_LOCK TZC_SEC_TZC_ROM0_R1_LOCK +#define TZC_SEC_TZC_ROM0_R1_LOCK_POS (25U) +#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS) +#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)) +#define TZC_SEC_TZC_ROM1_R0_LOCK TZC_SEC_TZC_ROM1_R0_LOCK +#define TZC_SEC_TZC_ROM1_R0_LOCK_POS (26U) +#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS) +#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)) +#define TZC_SEC_TZC_ROM1_R1_LOCK TZC_SEC_TZC_ROM1_R1_LOCK +#define TZC_SEC_TZC_ROM1_R1_LOCK_POS (27U) +#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN (1U) +#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS) +#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)) +#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE +#define TZC_SEC_TZC_SBOOT_DONE_POS (28U) +#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U) +#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS) +#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)) + +/* 0x44 : tzc_rom0_r0 */ +#define TZC_SEC_TZC_ROM0_R0_OFFSET (0x44) +#define TZC_SEC_TZC_ROM0_R0_END TZC_SEC_TZC_ROM0_R0_END +#define TZC_SEC_TZC_ROM0_R0_END_POS (0U) +#define TZC_SEC_TZC_ROM0_R0_END_LEN (16U) +#define TZC_SEC_TZC_ROM0_R0_END_MSK (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS) +#define TZC_SEC_TZC_ROM0_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)) +#define TZC_SEC_TZC_ROM0_R0_START TZC_SEC_TZC_ROM0_R0_START +#define TZC_SEC_TZC_ROM0_R0_START_POS (16U) +#define TZC_SEC_TZC_ROM0_R0_START_LEN (16U) +#define TZC_SEC_TZC_ROM0_R0_START_MSK (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS) +#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)) + +/* 0x48 : tzc_rom0_r1 */ +#define TZC_SEC_TZC_ROM0_R1_OFFSET (0x48) +#define TZC_SEC_TZC_ROM0_R1_END TZC_SEC_TZC_ROM0_R1_END +#define TZC_SEC_TZC_ROM0_R1_END_POS (0U) +#define TZC_SEC_TZC_ROM0_R1_END_LEN (16U) +#define TZC_SEC_TZC_ROM0_R1_END_MSK (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS) +#define TZC_SEC_TZC_ROM0_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)) +#define TZC_SEC_TZC_ROM0_R1_START TZC_SEC_TZC_ROM0_R1_START +#define TZC_SEC_TZC_ROM0_R1_START_POS (16U) +#define TZC_SEC_TZC_ROM0_R1_START_LEN (16U) +#define TZC_SEC_TZC_ROM0_R1_START_MSK (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS) +#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)) + +/* 0x4C : tzc_rom1_r0 */ +#define TZC_SEC_TZC_ROM1_R0_OFFSET (0x4C) +#define TZC_SEC_TZC_ROM1_R0_END TZC_SEC_TZC_ROM1_R0_END +#define TZC_SEC_TZC_ROM1_R0_END_POS (0U) +#define TZC_SEC_TZC_ROM1_R0_END_LEN (16U) +#define TZC_SEC_TZC_ROM1_R0_END_MSK (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS) +#define TZC_SEC_TZC_ROM1_R0_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)) +#define TZC_SEC_TZC_ROM1_R0_START TZC_SEC_TZC_ROM1_R0_START +#define TZC_SEC_TZC_ROM1_R0_START_POS (16U) +#define TZC_SEC_TZC_ROM1_R0_START_LEN (16U) +#define TZC_SEC_TZC_ROM1_R0_START_MSK (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS) +#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)) + +/* 0x50 : tzc_rom1_r1 */ +#define TZC_SEC_TZC_ROM1_R1_OFFSET (0x50) +#define TZC_SEC_TZC_ROM1_R1_END TZC_SEC_TZC_ROM1_R1_END +#define TZC_SEC_TZC_ROM1_R1_END_POS (0U) +#define TZC_SEC_TZC_ROM1_R1_END_LEN (16U) +#define TZC_SEC_TZC_ROM1_R1_END_MSK (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS) +#define TZC_SEC_TZC_ROM1_R1_END_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)) +#define TZC_SEC_TZC_ROM1_R1_START TZC_SEC_TZC_ROM1_R1_START +#define TZC_SEC_TZC_ROM1_R1_START_POS (16U) +#define TZC_SEC_TZC_ROM1_R1_START_LEN (16U) +#define TZC_SEC_TZC_ROM1_R1_START_MSK (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS) +#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)) + +struct tzc_sec_reg { + /* 0x0 reserved */ + uint8_t RESERVED0x0[64]; + + /* 0x40 : tzc_rom_ctrl */ + union { + struct { + uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r/w, 0x1 */ + uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r/w, 0x1 */ + uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r/w, 0x1 */ + uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r/w, 0x1 */ + uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r/w, 0x1 */ + uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r/w, 0x1 */ + uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r/w, 0x1 */ + uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r/w, 0x1 */ + uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_en : 1; /* [ 16], r/w, 0x0 */ + uint32_t tzc_rom0_r1_en : 1; /* [ 17], r/w, 0x0 */ + uint32_t tzc_rom1_r0_en : 1; /* [ 18], r/w, 0x0 */ + uint32_t tzc_rom1_r1_en : 1; /* [ 19], r/w, 0x0 */ + uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ + uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r/w, 0x0 */ + uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r/w, 0x0 */ + uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r/w, 0x0 */ + uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r/w, 0x0 */ + uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom_ctrl; + + /* 0x44 : tzc_rom0_r0 */ + union { + struct { + uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom0_r0_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r0; + + /* 0x48 : tzc_rom0_r1 */ + union { + struct { + uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom0_r1_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom0_r1; + + /* 0x4C : tzc_rom1_r0 */ + union { + struct { + uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom1_r0_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r0; + + /* 0x50 : tzc_rom1_r1 */ + union { + struct { + uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r/w, 0xffff */ + uint32_t tzc_rom1_r1_start : 16; /* [31:16], r/w, 0x0 */ + } BF; + uint32_t WORD; + } tzc_rom1_r1; +}; + +typedef volatile struct tzc_sec_reg tzc_sec_reg_t; + +#endif /* __TZC_SEC_REG_H__ */ diff --git a/drivers/soc/bl702l/std/port/bl702l_clock.c b/drivers/soc/bl702l/std/port/bl702l_clock.c new file mode 100644 index 000000000..cabf20911 --- /dev/null +++ b/drivers/soc/bl702l/std/port/bl702l_clock.c @@ -0,0 +1,19 @@ +#include "bflb_clock.h" +#include "bl702l_clock.h" + +uint32_t bflb_clk_get_system_clock(uint8_t type) +{ + return 0; +} + +uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx) +{ + if (type == BFLB_DEVICE_TYPE_UART) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0); + } else if (type == BFLB_DEVICE_TYPE_SPI) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0); + } else if (type == BFLB_DEVICE_TYPE_I2C) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0); + } + return 0; +} \ No newline at end of file diff --git a/drivers/soc/bl702l/std/src/bl702l_aon.c b/drivers/soc/bl702l/std/src/bl702l_aon.c new file mode 100644 index 000000000..ca3dc5c40 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_aon.c @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file bl702l_aon.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_aon.h" +#include "bl702l_ef_cfg.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup AON + * @{ + */ + +/** @defgroup AON_Private_Macros + * @{ + */ +#define AON_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group AON_Private_Macros */ + +/** @defgroup AON_Private_Types + * @{ + */ + +/*@} end of group AON_Private_Types */ + +/** @defgroup AON_Private_Variables + * @{ + */ + +/*@} end of group AON_Private_Variables */ + +/** @defgroup AON_Global_Variables + * @{ + */ + +/*@} end of group AON_Global_Variables */ + +/** @defgroup AON_Private_Fun_Declaration + * @{ + */ + +/*@} end of group AON_Private_Fun_Declaration */ + +/** @defgroup AON_Private_Functions + * @{ + */ + +/*@} end of group AON_Private_Functions */ + +/** @defgroup AON_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Power on MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702L_Delay_US(55); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power off MXX band gap + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void) +{ + uint32_t tmpVal = 0; + + /* Power OFF */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void) +{ + uint32_t tmpVal = 0; + uint32_t timeOut = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_HF_RC32M_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + /* Polling for ready */ + do { + BL702L_Delay_US(10); + timeOut++; + tmpVal = BL_RD_REG(AON_BASE, AON_TSEN); + } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120); + + if (timeOut >= 120) { + return TIMEOUT; + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set XTAL cap code + * + * @param capIn: Cap code in + * @param capOut: Cap code out + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_HF_CAPCODE_IN_AON, capIn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_HF_CAPCODE_OUT_AON, capOut); + BL_WR_REG(AON_BASE, AON_XTAL_CFG2, tmpVal); + + BL702L_Delay_US(100); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get XTAL cap code + * + * @param None + * + * @return Cap code + * +*******************************************************************************/ +uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_HF_CAPCODE_IN_AON); +} + +/****************************************************************************/ /** + * @brief Set XTAL cap code + * + * @param extra: cap cpde extra aon + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode_Extra(uint8_t extra) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG); + if (extra) { + tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON); + } + BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off XTAL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_HF_RC32M_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power on bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal); + + BL702L_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off bandgap system + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void) +{ + uint32_t tmpVal = 0; + + /* power up RF for PLL to work */ + tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON); + BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal); + + BL702L_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_TOP); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE, AON_LDO11SOC_TOP, tmpVal); + + BL702L_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off LDO11 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_TOP); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON); + BL_WR_REG(AON_BASE, AON_LDO11SOC_TOP, tmpVal); + + BL702L_Delay_US(55); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power on source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power on sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702L_Delay_US(10); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power off source follow regular + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void) +{ + uint32_t tmpVal = 0; + + /* power off sfreg */ + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off the power can be shut down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void) +{ + uint32_t tmpVal = 0; + + /* power off bz */ + tmpVal = BL_RD_REG(AON_BASE, AON_MISC); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_BZ_EN_AON); + BL_WR_REG(AON_BASE, AON_MISC, tmpVal); + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON); +#if 0 + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); +#endif + tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + /* gating Clock, no more use */ + //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0); + //tmpVal=tmpVal&(~(1<<6)); + //tmpVal=tmpVal&(~(1<<7)); + //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on the power powered down in PDS0 + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702L_Delay_US(20); + +#if 0 + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON); +#endif + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702L_Delay_US(60); + + tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON); + BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal); + + BL702L_Delay_US(20); + + /* power on bz */ + tmpVal = BL_RD_REG(AON_BASE, AON_MISC); + tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_BZ_EN_AON); + BL_WR_REG(AON_BASE, AON_MISC, tmpVal); + + /* ungating Clock, no more use */ + //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0); + //tmpVal=tmpVal|((1<<6)); + //tmpVal=tmpVal|((1<<7)); + //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on the power powered down in PDS0 + * + * @param delay: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((delay <= 0x3)); + + /* config ldo11soc_sstart_delay_aon */ + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_TOP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay); + BL_WR_REG(AON_BASE, AON_LDO11SOC_TOP, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DCDC14 voltage and vpfm + * + * @param voutSel output voltage selection + * @param vpfm pfm mode threshold + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type AON_Set_DCDC14_Top_0(uint8_t voutSel, uint8_t vpfm) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0); + //dcdc18_vout_sel_aon, 1.425V*1.05=1.5V + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VOUT_SEL_AON, voutSel); + //dcdc18_vpfm_aon + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VPFM_AON, vpfm); + BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief trim LDO11SOC vout + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo11socVoutTrim(void) +{ + bflb_ef_ctrl_com_trim_t trim; + int32_t tmpVal = 0; + + bflb_ef_ctrl_read_common_trim(NULL, "ldo11_trim", &trim, 1); + if (trim.en) { + if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) { + tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_TOP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_VOUT_TRIM_AON, trim.value); + BL_WR_REG(AON_BASE, AON_LDO11SOC_TOP, tmpVal); + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief trim LDO14 vout + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo14VoutTrim(void) +{ + bflb_ef_ctrl_com_trim_t trim; + int32_t tmpVal = 0; + + bflb_ef_ctrl_read_common_trim(NULL, "ldo14_trim", &trim, 1); + if (trim.en) { + if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) { + tmpVal = BL_RD_REG(AON_BASE, AON_LDO14_TOP); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO14_VOUT_TRIM_AON, trim.value); + BL_WR_REG(AON_BASE, AON_LDO14_TOP, tmpVal); + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief trim LDO14 vout + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION AON_Trim_Dcdc14VoutTrim(void) +{ + bflb_ef_ctrl_com_trim_t trim; + int32_t tmpVal = 0; + + bflb_ef_ctrl_read_common_trim(NULL, "ldo14_trim", &trim, 1); + if (trim.en) { + if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) { + tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VOUT_TRIM_AON, trim.value); + BL_WR_REG(AON_BASE, AON_DCDC_TOP_2, tmpVal); + return SUCCESS; + } + } + + return ERROR; +} +/*@} end of group AON_Public_Functions */ + +/*@} end of group AON */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_clock.c b/drivers/soc/bl702l/std/src/bl702l_clock.c new file mode 100644 index 000000000..522a23d16 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_clock.c @@ -0,0 +1,1167 @@ +/** + ****************************************************************************** + * @file bl702l_clock.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_clock.h" +// #include "pwm_reg.h" +// #include "timer_reg.h" +// #include "risc-v/Core/Include/clic.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup CLOCK + * @{ + */ + +/** @defgroup CLOCK_Private_Macros + * @{ + */ + +/*@} end of group CLOCK_Private_Macros */ + +/** @defgroup CLOCK_Private_Types + * @{ + */ + +/*@} end of group CLOCK_Private_Types */ + +/** @defgroup CLOCK_Private_Variables + * @{ + */ + +/*@} end of group CLOCK_Private_Variables */ + +/** @defgroup CLOCK_Global_Variables + * @{ + */ + +/*@} end of group CLOCK_Global_Variables */ + +/** @defgroup CLOCK_Private_Fun_Declaration + * @{ + */ + +/*@} end of group CLOCK_Private_Fun_Declaration */ + +/** @defgroup CLOCK_Private_Functions + * @{ + */ + +/*@} end of group CLOCK_Private_Functions */ + +/** @defgroup CLOCK_Public_Functions + * @{ + */ + +/******************************* clock source *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_RC_LowFreq_Output(void) +{ + return (32768); /* RC32K */ +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_RC_HighFreq_Output(void) +{ + return (32 * 1000 * 1000); /* RC32M */ +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_XTAL_LowFreq_Output(void) +{ + return (32768); /* 32.768KHz */ +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_XTAL_HighFreq_Output(void) +{ + return (32 * 1000 * 1000); /* 32MHz */ +} + +/******************************* dll clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_DLL_Output(uint32_t div) +{ + if (div == 1) { + return (128 * 1000 * 1000); + } else if (div == 2) { + return (64 * 1000 * 1000); + } else if (div == 3) { + return (42666667); + } else if (div == 5) { + return (25600000); + } else if (div == 21) { + return (6095238); + } else if (div == 63) { + return (2031746); + } else { + return 0; + } +} + +/******************************* xclk clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_XCLK_Output(uint32_t sel) +{ + if (sel == 0) { + return Clock_RC_HighFreq_Output(); + } else if (sel == 1) { + return Clock_XTAL_HighFreq_Output(); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_XCLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL); + + return (tmpVal & 0x1); +} + +/******************************* dig32k clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_DIG32K_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN) == 0) { + return 0; + } + if (sel == 0) { + return (Clock_XTAL_HighFreq_Output() / div); /* XTAL32M source */ + } else if (sel == 1) { + return (Clock_RC_HighFreq_Output() / div); /* RC32M source */ + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_DIG32K_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_DIG32K_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV); +} + +/******************************* f32k clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_F32K_Output(uint32_t sel) +{ + if (sel == 0 || sel == 2) { + return Clock_RC_LowFreq_Output(); + } else if (sel == 1) { + return Clock_XTAL_LowFreq_Output(); + } else if (sel == 3) { + return Clock_DIG32K_Output(Clock_DIG32K_Sel(), Clock_DIG32K_Div()); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_F32K_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + + return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); +} + +/******************************* root clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_ROOT_Output(uint32_t selRoot, uint32_t selPll) +{ + if (selRoot == 0) { + return Clock_RC_HighFreq_Output(); + } else if (selRoot == 1) { + return Clock_XTAL_HighFreq_Output(); + } else if (selRoot == 2 || selRoot == 3) { + if (selPll == 0) { + return Clock_DLL_Output(5); + } else if (selPll == 1) { + return Clock_DLL_Output(3); + } else if (selPll == 2) { + return Clock_DLL_Output(2); + } else if (selPll == 3) { + return Clock_DLL_Output(1); + } else { + return 0; + } + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_ROOT_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL); + + return tmpVal; +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_ROOT_DLL_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL); + + return tmpVal; +} + +/******************************* fclk clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_FCLK_Output(uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_FCLK_EN) == 0) { + return 0; + } else { + return Clock_ROOT_Output(Clock_ROOT_Sel(), Clock_ROOT_DLL_Sel()) / (div + 1); + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_FCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); +} + +/******************************* hclk clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_HCLK_Output(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_EN) == 0) { + return 0; + } else { + return Clock_FCLK_Output(Clock_FCLK_Div()); + } +} + +/******************************* bclk clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_BCLK_Output(uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_EN) == 0) { + return 0; + } else { + return Clock_HCLK_Output() / (div + 1); + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_BCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); +} + +/******************************* mtimer clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_MTIMER_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + if (sel == 0) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_EN) == 0) { + return 0; + } else { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } + } else if (sel == 1) { + return Clock_F32K_Output(Clock_F32K_Sel()) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_MTIMER_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_MTIMER_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV); +} + +/****************************************************************************/ /** + * @brief Get System Clock + * + * @param type: System clock type + * + * @return System clock value + * +*******************************************************************************/ +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type) +{ + switch (type) { + case BL_SYSTEM_CLOCK_XCLK: + /*!< mcu xclk clock */ + return Clock_XCLK_Output(Clock_XCLK_Sel()); + + case BL_SYSTEM_CLOCK_ROOT: + /*!< mcu root clock */ + return Clock_ROOT_Output(Clock_ROOT_Sel(), Clock_ROOT_DLL_Sel()); + + case BL_SYSTEM_CLOCK_FCLK: + return Clock_FCLK_Output(Clock_FCLK_Div()); + + case BL_SYSTEM_CLOCK_HCLK: + return Clock_HCLK_Output(); + + case BL_SYSTEM_CLOCK_BCLK: + /*!< mcu peri bus clock */ + return Clock_BCLK_Output(Clock_BCLK_Div()); + + case BL_SYSTEM_CLOCK_XTAL: + /*!< xtal clock */ + return Clock_XTAL_HighFreq_Output(); + + case BL_SYSTEM_CLOCK_F32K: + /*!< f32k clock */ + return Clock_F32K_Output(Clock_F32K_Sel()); + + case BL_SYSTEM_CLOCK_DIG32K: + return Clock_DIG32K_Output(Clock_DIG32K_Sel(), Clock_DIG32K_Div()); + + case BL_SYSTEM_CLOCK_MTIMER: + /*!< mtimer clock */ + return Clock_MTIMER_Output(Clock_MTIMER_Sel(), Clock_MTIMER_Div()); + + default: + return 0; + } +} + +/******************************* SF clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_SF_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_EN) == 0) { + return 0; + } + if (sel == 0) { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } else if (sel == 1) { + return Clock_DLL_Output(2) / (div + 1); + } else if (sel == 2) { + return Clock_BCLK_Output(Clock_BCLK_Div()) / (div + 1); + } else if (sel == 3) { + return Clock_DLL_Output(3) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_SF_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_SF_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); +} + +/******************************* PKA clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_PKA_Output(uint32_t sel) +{ + if (sel == 0) { + return Clock_HCLK_Output(); + } else if (sel == 1) { + return Clock_DLL_Output(1); + } else if (sel == 2) { + return Clock_DLL_Output(2); + } else if (sel == 3) { + return Clock_DLL_Output(3); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_PKA_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL); +} + +/******************************* UART clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_UART_Output(uint32_t sel, uint32_t sel2, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CGEN_S1A0) == 0) { + return 0; + } + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_EN) == 0) { + return 0; + } + if (sel2 == 0) { + if (sel == 0) { + return Clock_FCLK_Output(Clock_FCLK_Div()) / (div + 1); + } else if (sel == 1) { + return Clock_DLL_Output(2) / (div + 1); + } else { + return 0; + } + } else if (sel2 == 1) { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_UART_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_UART_Sel2(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_UART_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); +} + +/******************************* SPI clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_SPI_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_EN) == 0) { + return 0; + } + if (sel == 0) { + return Clock_BCLK_Output(Clock_BCLK_Div()) / (div + 1); + } else if (sel == 1) { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_SPI_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_SPI_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); +} + +/******************************* I2C clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_I2C_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CGEN_S1A3) == 0) { + return 0; + } + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_EN) == 0) { + return 0; + } + if (sel == 0) { + return Clock_BCLK_Output(Clock_BCLK_Div()) / (div + 1); + } else if (sel == 1) { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_I2C_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_I2C_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); +} + +/******************************* IR clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_IR_Output(uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_EN) == 0) { + return 0; + } + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_IR_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); +} + +/******************************* ADC clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_DIV_EN) == 0) { + return 0; + } + if (sel == 0) { + return Clock_F32K_Output(Clock_F32K_Sel()) / (div + 1); + } else if (sel == 1) { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); +} + +/******************************* pwm clock *******************************/ +// static inline uint32_t ATTR_CLOCK_SECTION Clock_PWM_Output(uint32_t sel, uint32_t div) +// { +// if (div == 0) { +// div = 1; +// } + +// if (sel == 0) { +// return Clock_XCLK_Output(Clock_XCLK_Sel()) / div; +// } else if (sel == 1) { +// return Clock_BCLK_Output(Clock_BCLK_Div()) / div; +// } else if (sel == 2 || sel == 3) { +// return Clock_F32K_Output(Clock_F32K_Sel()) / div; +// } else { +// return 0; +// } +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_PWM_SC0_Sel(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(PWM_BASE, PWM0_SC0_CONFIG); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_SC0_REG_CLK_SEL); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_PWM_SC0_Div(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(PWM_BASE, PWM0_SC0_CLKDIV); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_SC0_CLK_DIV); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_PWM_MC0_Sel(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(PWM_BASE, PWM_MC0_CONFIG0); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_PWM_MC0_Div(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(PWM_BASE, PWM_MC0_CONFIG0); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV); + +// return tmpVal; +// } + +/******************************* key scan clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_KYS_Output(uint32_t sel, uint32_t div) +{ + if (sel == 0) { + return Clock_XCLK_Output(Clock_XCLK_Sel()) / (div + 1); + } else if (sel == 1) { + return Clock_F32K_Output(Clock_F32K_Sel()) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_KYS_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_KYS_1M_CLK_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_KYS_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_KYS_1M_CLK_DIV); +} + +/******************************* audio clock *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_AUDIO_Output(uint32_t sel, uint32_t div) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_CLK_DIV_EN) == 0) { + return 0; + } + if (sel == 0) { + return Clock_DLL_Output(63) / (div + 1); + } else if (sel == 1) { + return Clock_DLL_Output(21) / (div + 1); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_AUDIO_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_CLK_SRC_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_AUDIO_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_CLK_DIV); +} + +/******************************* chip clock out *******************************/ +static inline uint32_t ATTR_CLOCK_SECTION Clock_CHIP0_Output(uint32_t sel) +{ + if (sel == 1) { + return Clock_DLL_Output(63); + } else if (sel == 2) { + return Clock_DLL_Output(21); + } else if (sel == 3) { + return Clock_XCLK_Output(Clock_XCLK_Sel()); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_CHIP1_Output(uint32_t sel) +{ + if (sel == 1) { + return Clock_F32K_Output(Clock_F32K_Sel()); + } else if (sel == 2 || sel == 3) { + return Clock_XTAL_HighFreq_Output(); + } else { + return 0; + } +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_CHIP0_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL); +} + +static inline uint32_t ATTR_CLOCK_SECTION Clock_CHIP1_Sel(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL); +} + +/******************************* timer clock *******************************/ +// static inline uint32_t ATTR_CLOCK_SECTION Clock_TIMER_Output(uint32_t sel, uint32_t div) +// { +// if (sel == 0) { +// return Clock_FCLK_Output(Clock_FCLK_Div()) / (div + 1); +// } else if (sel == 1) { +// return Clock_F32K_Output(Clock_F32K_Sel()) / (div + 1); +// } else if (sel == 2) { +// return Clock_F32K_Output(Clock_F32K_Sel()) * 1000 / (div + 1) / 32768; +// } else if (sel == 3) { +// return Clock_XTAL_HighFreq_Output() / (div + 1); +// } else { +// return 0; +// } +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_TIMER0_CH0_Sel(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_TIMER0_CH0_Div(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_TIMER0_CH1_Sel(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_3); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_TIMER0_CH1_Div(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_WDT_Sel(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT); + +// return tmpVal; +// } + +// static inline uint32_t ATTR_CLOCK_SECTION Clock_WDT_Div(void) +// { +// uint32_t tmpVal; + +// tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_WCDR); + +// return tmpVal; +// } + +/****************************************************************************/ /** + * @brief Get Peripheral Clock + * + * @param type: Peripheral clock type + * + * @return Peripheral clock value + * +*******************************************************************************/ +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) +{ + uint32_t clock = 0; + + switch (type) { + case BL_PERIPHERAL_CLOCK_UART0: + clock = Clock_UART_Output(Clock_UART_Sel(), Clock_UART_Sel2(), Clock_UART_Div()); + break; + + case BL_PERIPHERAL_CLOCK_SPI0: + clock = Clock_SPI_Output(Clock_SPI_Sel(), Clock_SPI_Div()); + break; + + case BL_PERIPHERAL_CLOCK_I2C0: + clock = Clock_I2C_Output(Clock_I2C_Sel(), Clock_I2C_Div()); + break; + + case BL_PERIPHERAL_CLOCK_GPADC: + clock = Clock_GPADC_Output(Clock_GPADC_Sel(), Clock_GPADC_Div()); + break; + + // case BL_PERIPHERAL_CLOCK_PWMSC: + // clock = Clock_PWM_Output(Clock_PWM_SC0_Sel(), Clock_PWM_SC0_Div()); + // break; + + // case BL_PERIPHERAL_CLOCK_PWM: + // clock = Clock_PWM_Output(Clock_PWM_MC0_Sel(), Clock_PWM_MC0_Div()); + // break; + + case BL_PERIPHERAL_CLOCK_IR: + clock = Clock_IR_Output(Clock_IR_Div()); + break; + + case BL_PERIPHERAL_CLOCK_FLASH: + clock = Clock_SF_Output(Clock_SF_Sel(), Clock_SF_Div()); + break; + + // case BL_PERIPHERAL_CLOCK_TIMER0_CH0: + // clock = Clock_TIMER_Output(Clock_TIMER0_CH0_Sel(), Clock_TIMER0_CH0_Div()); + // break; + + // case BL_PERIPHERAL_CLOCK_TIMER0_CH1: + // clock = Clock_TIMER_Output(Clock_TIMER0_CH1_Sel(), Clock_TIMER0_CH1_Div()); + // break; + + // case BL_PERIPHERAL_CLOCK_WDT: + // clock = Clock_TIMER_Output(Clock_WDT_Sel(), Clock_WDT_Div()); + // break; + + case BL_PERIPHERAL_CLOCK_AUDIO: + clock = Clock_AUDIO_Output(Clock_AUDIO_Sel(), Clock_AUDIO_Div()); + break; + + case BL_PERIPHERAL_CLOCK_CHIPOUT0: + clock = Clock_CHIP0_Output(Clock_CHIP0_Sel()); + break; + + case BL_PERIPHERAL_CLOCK_CHIPOUT1: + clock = Clock_CHIP1_Output(Clock_CHIP1_Sel()); + break; + + case BL_PERIPHERAL_CLOCK_PKA: + clock = Clock_PKA_Output(Clock_PKA_Sel()); + break; + + case BL_PERIPHERAL_CLOCK_KYS: + clock = Clock_KYS_Output(Clock_KYS_Sel(), Clock_KYS_Div()); + break; + + default: + clock = 0; + } + return clock; +} + +/****************************************************************************/ /** + * @brief get system core clock + * + * @param None + * + * @return system core clock value + * +*******************************************************************************/ +uint32_t ATTR_CLOCK_SECTION SystemCoreClockGet(void) +{ + uint32_t clockVal = 0; + + clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK); + + clockVal = clockVal ? clockVal : (32 * 1000 * 1000); + + return clockVal; +} + +/****************************************************************************/ /** + * @brief get mcu rtc clock + * + * @param None + * + * @return mcu rtc counter clock + * +*******************************************************************************/ +uint32_t CPU_Get_MTimer_Clock(void) +{ + return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MTIMER); +} + +/****************************************************************************/ /** + * @brief get mcu rtc counter + * + * @param None + * + * @return mcu rtc counter + * +*******************************************************************************/ +// uint64_t CPU_Get_MTimer_Counter(void) +// { +// volatile uint64_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1; +// uint8_t cnt = 0; + +// do { +// tmpValHigh = (uint64_t)(*(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4)); +// tmpValLow = (uint64_t)(*(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME)); +// tmpValLow1 = (uint64_t)(*(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME)); +// tmpValHigh1 = (uint64_t)(*(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4)); +// cnt++; +// if (cnt > 4) { +// break; +// } +// } while (tmpValLow > tmpValLow1 || tmpValHigh != tmpValHigh1); + +// return (uint64_t)((tmpValHigh1 << 32) + tmpValLow1); +// } + +/****************************************************************************/ /** + * @brief get mcu cycle + * + * @param None + * + * @return mcu cycle + * +*******************************************************************************/ +uint64_t CPU_Get_CPU_Cycle(void) +{ +#if (__riscv_xlen == 64) + return (uint64_t)__get_MCYCLE(); +#else + volatile uint64_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1; + uint32_t result; + uint8_t cnt = 0; + + do { + __ASM volatile("csrr %0, mcycleh" + : "=r"(result)); + tmpValHigh = (uint64_t)result; + __ASM volatile("csrr %0, mcycle" + : "=r"(result)); + tmpValLow = (uint64_t)result; + __ASM volatile("csrr %0, mcycle" + : "=r"(result)); + tmpValLow1 = (uint64_t)result; + __ASM volatile("csrr %0, mcycleh" + : "=r"(result)); + tmpValHigh1 = (uint64_t)result; + cnt++; + if (cnt > 4) { + break; + } + } while (tmpValLow > tmpValLow1 || tmpValHigh != tmpValHigh1); + + return (uint64_t)((tmpValHigh1 << 32) + tmpValLow1); +#endif +} + +/****************************************************************************/ /** + * @brief get mcu rtc counter in us + * + * @param None + * + * @return mcu rtc counter in us + * +*******************************************************************************/ +uint64_t CPU_Get_MTimer_US(void) +{ + uint32_t clk = CPU_Get_MTimer_Clock(); + uint64_t mtimer_counter = CPU_Get_MTimer_Counter(); + if (mtimer_counter == 0) { + mtimer_counter = CPU_Get_CPU_Cycle(); + clk = SystemCoreClockGet(); + } + + if (clk < 1000 * 1000) { + return mtimer_counter * 1000 / (clk / 1000); + } else { + return mtimer_counter / (clk / 1000 / 1000); + } +} + +/****************************************************************************/ /** + * @brief get mcu rtc counter in ms + * + * @param None + * + * @return mcu rtc counter in ms + * +*******************************************************************************/ +uint64_t CPU_Get_MTimer_MS(void) +{ + uint32_t clk = CPU_Get_MTimer_Clock(); + uint64_t mtimer_counter = CPU_Get_MTimer_Counter(); + if (mtimer_counter == 0) { + mtimer_counter = CPU_Get_CPU_Cycle(); + clk = SystemCoreClockGet(); + } + + return mtimer_counter / (clk / 1000); +} + +/****************************************************************************/ /** + * @brief mcu timer delay us + * + * @param cnt: us + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type CPU_MTimer_Delay_US(uint32_t cnt) +{ + volatile uint64_t us1 = 0; + volatile uint64_t us2 = 0; + + us1 = CPU_Get_MTimer_US(); + do { + us2 = CPU_Get_MTimer_US(); + } while (((us2 - us1) < (uint64_t)(cnt))); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief mcu timer delay ms + * + * @param cnt: ms + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type CPU_MTimer_Delay_MS(uint32_t cnt) +{ + volatile uint64_t ms1 = 0; + volatile uint64_t ms2 = 0; + + ms1 = CPU_Get_MTimer_MS(); + do { + ms2 = CPU_Get_MTimer_MS(); + } while (((ms2 - ms1) < (uint64_t)(cnt))); + + return SUCCESS; +} + +/*@} end of group CLOCK_Public_Functions */ + +/*@} end of group CLOCK */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_common.c b/drivers/soc/bl702l/std/src/bl702l_common.c new file mode 100644 index 000000000..fd5b1b348 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_common.c @@ -0,0 +1,202 @@ +/** + ****************************************************************************** + * @file bl702l_common.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "l1c_reg.h" +#include "bl702l_clock.h" +#include "bl702l_common.h" + +/** @addtogroup BL702L_Periph_Driver + * @{ + */ + +/****************************************************************************/ /** + * @brief delay us + * + * @param[in] core: systemcoreclock + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +#ifdef ARCH_ARM +#ifndef __GNUC__ +__WEAK +__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr +} +#else +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + __asm__ __volatile__( + "lsr r0,#0x10\n\t" + "mul r0,r1,r0\n\t" + "mov r2,r0\n\t" + "lsr r2,#0x04\n\t" + "lsr r2,#0x03\n\t" + "cmp r2,#0x01\n\t" + "beq end\n\t" + "cmp r2,#0x00\n\t" + "beq end\n" + "loop :" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "mov r0,r0\n\t" + "sub r2,r2,#0x01\n\t" + "cmp r2,#0x00\n\t" + "bne loop\n" + "end :" + "mov r0,r0\n\t"); +} +#endif +#endif +#ifdef ARCH_RISCV +__WEAK +void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt) +{ + uint32_t codeAddress = 0; + uint32_t divVal = 40; + + codeAddress = (uint32_t)&ASM_Delay_Us; + + /* 1M=100K*10, so multiple is 10 */ + /* loop function take 4 instructions, so instructionNum is 4 */ + /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */ + /* divVal = multiple*instructionNum*irom2TAccess */ + if (((codeAddress & (0xF << 24)) >> 24) == 0x01) { + /* IROM space */ + if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { + /* instruction 2T */ + divVal = 80; + } + } + + __asm__ __volatile__( + ".align 4\n\t" + "lw a4,%1\n\t" + "lui a5,0x18\n\t" + "addi a5,a5,1696\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%0\n\t" + "mul a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a4,%1\n\t" + "lw a5,%2\n\t" + "divu a5,a4,a5\n\t" + "sw a5,%1\n\t" + "lw a5,%1\n\t" + "li a4,0x1\n\t" + "beq a5,zero,end\n\t" + "beq a5,a4,end\n\t" + "nop\n\t" + "nop\n\t" + ".align 4\n\t" + "loop :\n" + "addi a4,a5,-1\n\t" + "mv a5,a4\n\t" + "bnez a5,loop\n\t" + "nop\n\t" + "end :\n\t" + "nop\n" + : /* output */ + : "m"(cnt), "m"(core), "m"(divVal) /* input */ + : "t1", "a4", "a5" /* destruct description */ + ); +} +#endif +#endif + +/****************************************************************************/ /** + * @brief delay us + * + * @param[in] cnt: delay cnt us + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION BL702L_Delay_US(uint32_t cnt) +{ + ASM_Delay_Us(SystemCoreClockGet(), cnt); +} +#endif +/****************************************************************************/ /** + * @brief delay ms + * + * @param[in] cnt: delay cnt ms + * + * @return none + * + *******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION BL702L_Delay_MS(uint32_t cnt) +{ + uint32_t i = 0; + uint32_t count = 0; + + if (cnt >= 1024) { + /* delay (n*1024) ms */ + for (i = 0; i < (cnt / 1024); i++) { + BL702L_Delay_US(1024 * 1000); + } + } + + count = cnt & 0x3FF; + + if (count) { + /* delay (1-1023)ms */ + BL702L_Delay_US(count * 1000); + } +} +#endif + +/* +char *_sbrk(int incr) +{} +*/ +/*@} end of group DRIVER_Public_Functions */ + +/*@} end of group DRIVER_COMMON */ + +/*@} end of group BL702L_Periph_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_ef_cfg.c b/drivers/soc/bl702l/std/src/bl702l_ef_cfg.c new file mode 100644 index 000000000..25074d386 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_ef_cfg.c @@ -0,0 +1,429 @@ +/** + ****************************************************************************** + * @file bl702l_ef_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "bflb_efuse.h" +#include "bl702l_ef_cfg.h" +#include "bl702l_glb.h" +#include "hardware/ef_data_reg.h" + +static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = { + { + .name = "rc32m", + .en_addr = 0x0C * 8 + 19, + .parity_addr = 0x0C * 8 + 18, + .value_addr = 0x0C * 8 + 10, + .value_len = 8, + }, + { + .name = "rc32k", + .en_addr = 0x0C * 8 + 31, + .parity_addr = 0x0C * 8 + 30, + .value_addr = 0x0C * 8 + 20, + .value_len = 10, + }, + { + .name = "ldo14_trim", + .en_addr = 0x0C * 8 + 31, + .parity_addr = 0x0C * 8 + 30, + .value_addr = 0x0C * 8 + 26, + .value_len = 4, + }, + { + .name = "xtal", + .en_addr = 0x58 * 8 + 9, + .parity_addr = 0x58 * 8 + 8, + .value_addr = 0x58 * 8 + 0, + .value_len = 8, + }, + { + .name = "ldo11_trim", + .en_addr = 0x78 * 8 + 20, + .parity_addr = 0x78 * 8 + 19, + .value_addr = 0x78 * 8 + 15, + .value_len = 4, + }, + { + .name = "gpadc_gain", + .en_addr = 0x78 * 8 + 14, + .parity_addr = 0x78 * 8 + 13, + .value_addr = 0x78 * 8 + 1, + .value_len = 12, + }, + { + .name = "tsen", + .en_addr = 0x78 * 8 + 0, + .parity_addr = 0x7C * 8 + 12, + .value_addr = 0x7C * 8 + 0, + .value_len = 12, + } +}; + +static GLB_ROOT_CLK_Type rtClk; +static uint8_t bdiv, hdiv; + +/****************************************************************************/ /** + * @brief Efuse read write switch clock save + * + * @param deviceInfo: info pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_save(void) +{ + /* all API should be place at tcm section */ + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + rtClk = GLB_Get_Root_CLK_Sel(); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + GLB_Set_System_CLK_Div(0, 0); +} + +/****************************************************************************/ /** + * @brief Efuse read write switch clock restore + * + * @param deviceInfo: info pointer + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_restore(void) +{ + /* all API should be place at tcm section */ + GLB_Set_System_CLK_Div(hdiv, bdiv); + HBN_Set_ROOT_CLK_Sel(rtClk); +} + +/****************************************************************************/ /** + * @brief Efuse get trim list + * + * @param trim_list: Trim list pointer + * + * @return Trim list count + * +*******************************************************************************/ +uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list) +{ + *ptrim_list = &trim_list[0]; + return sizeof(trim_list) / sizeof(trim_list[0]); +} + +/****************************************************************************/ /** + * @brief Efuse read device info + * + * @param deviceInfo: info pointer + * + * @return None + * +*******************************************************************************/ +void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo) +{ + uint32_t *p = (uint32_t *)deviceInfo; + + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1); +} + +void bflb_efuse_get_chipid(uint8_t chipid[8]) +{ + bflb_efuse_read_mac_address_opt(0, chipid, 1); + chipid[6] = 0; + chipid[7] = 0; +} + +/****************************************************************************/ /** + * @brief Whether MAC address slot is empty + * + * @param slot: MAC address slot + * @param reload: whether reload to check + * + * @return 0 for all slots full,1 for others + * +*******************************************************************************/ +uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload) +{ + uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; + uint32_t part1Empty = 0, part2Empty = 0; + + if (slot == 0) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload); + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload); + } else if (slot == 1) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmp1, 1, reload); + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmp2, 1, reload); + } else if (slot == 2) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmp1, 1, reload); + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmp2, 1, reload); + } + + part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32)); + part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22)); + + return (part1Empty && part2Empty); +} + +/****************************************************************************/ /** + * @brief Efuse write optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param program: Whether program + * + * @return 0 or -1 + * +*******************************************************************************/ +int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpval; + uint32_t i = 0, cnt; + + if (slot >= 3) { + return -1; + } + + /* Change to local order */ + for (i = 0; i < 3; i++) { + tmpval = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpval; + } + + /* The low 32 bits */ + tmpval = BL_RDWD_FRM_BYTEP(maclow); + + if (slot == 0) { + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program); + } else if (slot == 1) { + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, program); + } else if (slot == 2) { + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, program); + } + + /* The high 16 bits */ + tmpval = machigh[0] + (machigh[1] << 8); + cnt = 0; + + for (i = 0; i < 6; i++) { + cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]); + } + + tmpval |= ((cnt & 0x3f) << 16); + + if (slot == 0) { + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program); + } else if (slot == 1) { + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, program); + } else if (slot == 2) { + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, program); + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Efuse read optional MAC address + * + * @param slot: MAC address slot + * @param mac[6]: MAC address buffer + * @param reload: Whether reload + * + * @return 0 or -1 + * +*******************************************************************************/ +int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload) +{ + uint8_t *maclow = (uint8_t *)mac; + uint8_t *machigh = (uint8_t *)(mac + 4); + uint32_t tmpval = 0; + uint32_t i = 0; + uint32_t cnt = 0; + + if (slot >= 3) { + return -1; + } + + if (slot == 0) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload); + } else if (slot == 1) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, reload); + } else if (slot == 2) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, reload); + } + + BL_WRWD_TO_BYTEP(maclow, tmpval); + + if (slot == 0) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload); + } else if (slot == 1) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, reload); + } else if (slot == 2) { + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, reload); + } + + machigh[0] = tmpval & 0xff; + machigh[1] = (tmpval >> 8) & 0xff; + + /* Check parity */ + for (i = 0; i < 6; i++) { + cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]); + } + + if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) { + /* Change to network order */ + for (i = 0; i < 3; i++) { + tmpval = mac[i]; + mac[i] = mac[5 - i]; + mac[5 - i] = tmpval; + } + return 0; + } else { + return -1; + } +} + +float bflb_efuse_get_adc_trim(void) +{ + bflb_ef_ctrl_com_trim_t trim; + uint32_t tmp; + + float coe = 1.0; + + bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1); + + if (trim.en) { + if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) { + tmp = trim.value; + + if (tmp & 0x800) { + tmp = ~tmp; + tmp += 1; + tmp = tmp & 0xfff; + coe = (1.0 + ((float)tmp / 2048.0)); + } else { + coe = (1.0 - ((float)tmp / 2048.0)); + } + } + } + + return coe; +} + +uint32_t bflb_efuse_get_adc_tsen_trim(void) +{ + bflb_ef_ctrl_com_trim_t trim; + + bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1); + if (trim.en) { + if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) { + return trim.value; + } + } + + return 2042; +} + +void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes) +{ + uint32_t tmpval = 0; + + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1); + *sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01; + *aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS); +} + +void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len) +{ + if (index > 5) { + return; + } + + bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1); +} + +void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len) +{ + if (index > 5) { + return; + } + + bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1); +} + +void bflb_efuse_lock_aes_key_write(uint8_t index) +{ + uint32_t lock = 0; + + if (index > 5) { + return; + } + /* write lock */ + if (index <= 3) { + lock |= (1 << (index + 19)); + } else { + lock |= (1 << (index + 19)); + lock |= (1 << (index - 4 + 13)); + } + bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1); +} + +void bflb_efuse_lock_aes_key_read(uint8_t index) +{ + uint32_t lock = 0; + + if (index > 5) { + return; + } + /* read lock */ + lock |= (1 << (index + 26)); + + bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1); +} + +void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program) +{ + if (index != 0) { + return; + } + bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program); +} + +void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage) +{ + if (index != 0) { + return; + } + bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1); +} \ No newline at end of file diff --git a/drivers/soc/bl702l/std/src/bl702l_glb.c b/drivers/soc/bl702l/std/src/bl702l_glb.c new file mode 100644 index 000000000..fa1bf7cfd --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_glb.c @@ -0,0 +1,2628 @@ +/** + ****************************************************************************** + * @file bl702l_glb.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_glb.h" +#include "bl702l_hbn.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Private_Macros + * @{ + */ +#define GLB_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } +#define GLB_REG_BCLK_DIS_TRUE (*(volatile uint32_t *)(0x40000FFC) = (0x00000001)) +#define GLB_REG_BCLK_DIS_FALSE (*(volatile uint32_t *)(0x40000FFC) = (0x00000000)) + +/*@} end of group GLB_Private_Macros */ + +/** @defgroup GLB_Private_Types + * @{ + */ + +/*@} end of group GLB_Private_Types */ + +/** @defgroup GLB_Private_Variables + * @{ + */ +static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL }; +/*@} end of group GLB_Private_Variables */ + +/** @defgroup GLB_Global_Variables + * @{ + */ + +/*@} end of group GLB_Global_Variables */ + +/** @defgroup GLB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group GLB_Private_Fun_Declaration */ + +/** @defgroup GLB_Private_Functions + * @{ + */ + +/*@} end of group GLB_Private_Functions */ + +/** @defgroup GLB_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief get root clock selection + * + * @param None + * + * @return root clock selection + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) { + case 0: + return GLB_ROOT_CLK_RC32M; + case 1: + return GLB_ROOT_CLK_XTAL; + case 2: + return GLB_ROOT_CLK_DLL; + case 3: + return GLB_ROOT_CLK_DLL; + default: + return GLB_ROOT_CLK_RC32M; + } +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock divider + * + * @param hclkDiv: HCLK divider + * @param bclkDiv: BCLK divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* recommend: fclk<=128MHz, bclk<=64MHz */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get Bus clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief Get CPU clock divider + * + * @param None + * + * @return Clock Divider + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); +} +#endif + +/****************************************************************************/ /** + * @brief Set System clock + * + * @param xtalType: XTAL frequency type + * @param clkFreq: clock frequency selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq) +{ + uint32_t tmpVal; + HBN_XCLK_CLK_Type xclkSel; + + CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType)); + CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + xclkSel = (HBN_XCLK_CLK_Type)(tmpVal & 0x01); + + /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* Before config XTAL and DLL ,make sure root clk is from RC32M */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + GLB_Set_System_CLK_Div(0, 0); + + if (xtalType == GLB_DLL_XTAL_NONE) { + if (clkFreq == GLB_SYS_CLK_RC32M) { + return SUCCESS; + } else { + return ERROR; + } + } + + if (xtalType != GLB_DLL_XTAL_RC32M) { + /* power on xtal first */ + AON_Power_On_XTAL(); + } + + /* Bl702 make PLL Setting out of RF, so following setting can be removed*/ + //AON_Power_On_MBG(); + //AON_Power_On_LDO15_RF(); + + /* always power up PLL and enable all PLL clock output */ + //PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType); + //BL702L_Delay_US(55); + //PDS_Enable_PLL_All_Clks(); + + /* always power up DLL and enable all DLL clock output */ + GLB_Power_Off_DLL(); + BL702L_Delay_US(5); + GLB_Power_On_DLL(xtalType); + GLB_Enable_DLL_All_Clks(); + + /* reg_pll_en = 1, cannot be zero */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + + /* select pll output clock before select root clock */ + if (clkFreq >= GLB_SYS_CLK_DLL25P6M) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_DLL25P6M); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + } + /* select root clock */ + switch (clkFreq) { + case GLB_SYS_CLK_RC32M: + break; + case GLB_SYS_CLK_XTAL: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL); + break; + case GLB_SYS_CLK_DLL25P6M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + HBN_Set_XCLK_CLK_Sel(xclkSel); + break; + case GLB_SYS_CLK_DLL42P67M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + HBN_Set_XCLK_CLK_Sel(xclkSel); + break; + case GLB_SYS_CLK_DLL64M: + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + HBN_Set_XCLK_CLK_Sel(xclkSel); + break; + case GLB_SYS_CLK_DLL128M: + L1C_IROM_2T_Access_Set(ENABLE); + GLB_Set_System_CLK_Div(0, 1); + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL); + HBN_Set_XCLK_CLK_Sel(xclkSel); + break; + default: + break; + } + + GLB_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief This is demo for user that use RC32M as default bootup clock instead of DLL,when APP is + * started, this function can be called to set DLL to 128M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void) +{ + SF_Ctrl_Cfg_Type sfCtrlCfg = { + .owner = SF_CTRL_OWNER_IAHB, + .clkDelay = 1, + .clkInvert = 1, + .rxClkInvert = 1, + .doDelay = 0, + .diDelay = 0, + .oeDelay = 0, + }; + /* Use RC32M as DLL ref source to set up DLL to 128M */ + GLB_Set_System_CLK(GLB_DLL_XTAL_RC32M, GLB_SYS_CLK_DLL128M); + /* Flash controller also need changes since system (bus) clock changed */ + SF_Ctrl_Enable(&sfCtrlCfg); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set mac154 and zigbee clock + * + * @param enable: Enable or disable mac154 and zigbee clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_M154_ZBEN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_M154_ZBEN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S300); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CGEN_S300); + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set BLE clock + * + * @param enable: Enable or disable BLE clock + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S301); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CGEN_S301); + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set AUDIO clock divider + * + * @param clkDivEn: enable or disable AUDIO clock div + * @param autoDivEn: enable or disable AUDIO auto div + * @param clkSel: AUDIO clock source type + * @param div: divider, 0~15 stand for 1~16 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_AUDIO_CLK(uint8_t clkDivEn, uint8_t autoDivEn, GLB_AUDIO_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_AUDIO_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0xF)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_CLK_SRC_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + if (clkDivEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_CLK_DIV_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_CLK_DIV_EN); + } + if (autoDivEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set KYS clock + * + * @param clkSel: KYS clock source type + * @param div: clock divider, 0~31 stand for 1~32 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_KYS_CLK(GLB_KYS_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_KYS_CLK_SRC_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_KYS_1M_CLK_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_KYS_1M_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DMA clock + * + * @param enable: Enable or disable DMA clock + * @param clk: DMA ID type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); + if (enable) { + tmpVal2 |= (1 << clk); + } else { + tmpVal2 &= (~(1 << clk)); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set IR clock divider + * + * @param enable: enable or disable IR clock + * @param clkSel: IR clock type, only XCLK could be selected + * @param div: divider, 0~63 stand for 1~64 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x3F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set sflash clock + * + * @param enable: Enable or disable sflash clock + * @param clkSel: sflash clock type + * @param div: clock divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x7)); + + /* disable SFLASH clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* enable relevant DLL clock */ + if (clkSel == GLB_SFLASH_CLK_64M) { + GLB_Enable_DLL_Clk(GLB_DLL_CLK_64M); + } else if (clkSel == GLB_SFLASH_CLK_42P67M) { + GLB_Enable_DLL_Clk(GLB_DLL_CLK_42P67M); + } else if (clkSel == GLB_SFLASH_CLK_BCLK) { + GLB_Enable_DLL_Clk(GLB_DLL_CLK_128M); + GLB_Enable_DLL_Clk(GLB_DLL_CLK_64M); + GLB_Enable_DLL_Clk(GLB_DLL_CLK_42P67M); + GLB_Enable_DLL_Clk(GLB_DLL_CLK_25P6M); + } + + /* clock divider and source */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* enable or disable flash clock */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set UART clock + * + * @param enable: Enable or disable UART clock + * @param clkSel: UART clock type + * @param div: clock divider, 0~7 stand for 1~8 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((div <= 0x7)); + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + /* disable UART clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Set div */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + /* Select clock source for uart */ + HBN_Set_UART_CLK_Sel(clkSel); + + /* Set enable or disable */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief gpio timer clock select + * + * @param gpioPin: gpio pin number + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Sel_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal, tmpValEn; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpValEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_EN); + switch (gpioPin & 0x3) { + case 0: /* inout_sig_0 */ + tmpValEn &= ~(1 << 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0); + break; + case 1: /* inout_sig_1 */ + tmpValEn &= ~(1 << 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1); + break; + case 2: /* inout_sig_2 */ + tmpValEn &= ~(1 << 2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2); + break; + case 3: /* inout_sig_3 */ + tmpValEn &= ~(1 << 3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3); + break; + default: + break; + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_EN, tmpValEn); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select chip clock out 0 type + * + * @param clkSel: chip clock out type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_0_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_0_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select chip clock out 1 type + * + * @param clkSel: chip clock out type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_1_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_1_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief enable or disable clock out + * + * @param enable: ENABLE or DISABLE + * @param gpioPin: pin index assert clock output + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Chip_Out_CLK_Enable(uint8_t enable, uint8_t pin) +{ + uint32_t tmpVal = 0; + uint32_t tmpValEn = 0; + uint32_t shift = pin & 3; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpValEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_EN); + if (enable) { + tmpValEn |= 1 << shift; + } else { + tmpValEn &= ~(1 << shift); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_EN, tmpValEn); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set I2C clock + * + * @param enable: Enable or disable I2C clock + * @param div: clock divider, 0~255 stand for 1~256 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_I2C_CLK_SRC_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set SPI clock + * + * @param enable: Enable or disable SPI clock + * @param div: clock divider, 0~31 stand for 1~32 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_SPI_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x1F)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); + } + BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief select PKA clock source + * + * @param clkSel: PKA clock selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_SRC_Type clkSel) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_PKA_CLK_SRC_TYPE(clkSel)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Software system reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL702L_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software CPU reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL702L_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Software power on reset + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) +{ + /***********************************************************************************/ + /* NOTE */ + /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */ + /* OCRAM use bclk as source clock. Pay attention to risks when using this API. */ + /***********************************************************************************/ + uint32_t tmpVal; + + /* Swicth clock to 32M as default */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + GLB_CLK_SET_DUMMY_WAIT; + + /* HCLK is RC32M , so BCLK/HCLK no need divider */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0); + BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); + GLB_REG_BCLK_DIS_TRUE; + GLB_REG_BCLK_DIS_FALSE; + GLB_CLK_SET_DUMMY_WAIT; + + /* Do reset */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); + + /* waiting for reset */ + while (1) { + BL702L_Delay_US(10); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief software reset + * + * @param swrst: reset num + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst) +{ + uint32_t tmpVal = 0; + uint32_t bit = 0; + uint32_t regAddr = 0; + + CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst)); + + if (swrst == GLB_AHB_MCU_SW_PWRON_RST) { + return GLB_SW_POR_Reset(); + } else if (swrst == GLB_AHB_MCU_SW_CPU_RESET) { + return GLB_SW_CPU_Reset(); + } else if (swrst == GLB_AHB_MCU_SW_SYS_RESET) { + return GLB_SW_System_Reset(); + } + + if (swrst < 32) { + bit = swrst; + regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET; + } else if (swrst < 64) { + bit = swrst - 32; + regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET; + } else if (swrst < 96) { + bit = swrst - 64; + regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET; + } + + tmpVal = BL_RD_WORD(regAddr); + tmpVal &= ~(1 << bit); + BL_WR_WORD(regAddr, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_WORD(regAddr); + tmpVal |= (1 << bit); + BL_WR_WORD(regAddr, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_WORD(regAddr); + tmpVal &= ~(1 << bit); + BL_WR_WORD(regAddr, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief dis reset + * + * @param enable: ENABLE or DISABLE + * @param disrst: disrst macro + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Disrst_Set(uint8_t enable, GLB_DISRST_Type disrst) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DISRST_TYPE(disrst)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG3); + if (enable) { + tmpVal |= (1 << disrst); + } else { + tmpVal &= ~(1 << disrst); + } + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG3, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief MAC154_ZIGBEE reset + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_MAC154_ZIGBEE_Reset(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWRST_S300); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S300); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BLE reset + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BLE_Reset(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWRST_S301); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal); + BL_DRV_DUMMY; + tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S301); + BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get first 1 from u64, then clear it + * + * @param val: target value + * @param bit: first 1 in bit + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit) +{ + if (!*val) { + return ERROR; + } + + for (uint8_t i = 0; i < 64; i++) { + if ((*val) & ((uint64_t)1 << i)) { + *bit = i; + (*val) &= ~((uint64_t)1 << i); + break; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief hold IPs clock + * + * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips) +{ + /* api request from cjy */ + + uint32_t tmpValCfg0 = 0; + uint32_t tmpValCfg1 = 0; + uint32_t tmpValCfg2 = 0; + uint32_t bitfield = 0; + + tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + while (ips) { + if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { + switch (bitfield) { + case GLB_AHB_CLOCK_IP_CPU: + tmpValCfg0 &= ~(1 << 0); + break; + case GLB_AHB_CLOCK_IP_SEC: + tmpValCfg0 &= ~(1 << 2); + tmpValCfg1 &= ~(1 << 3); + tmpValCfg1 &= ~(1 << 4); + break; + case GLB_AHB_CLOCK_IP_DMA_0: + tmpValCfg0 &= ~(1 << 3); + tmpValCfg1 &= ~(1 << 12); + break; + case GLB_AHB_CLOCK_IP_CCI: + tmpValCfg0 &= ~(1 << 4); + break; + case GLB_AHB_CLOCK_IP_GPIP: + tmpValCfg1 &= ~(1 << 2); + break; + case GLB_AHB_CLOCK_IP_TZC: + tmpValCfg1 &= ~(1 << 5); + break; + case GLB_AHB_CLOCK_IP_EF_CTRL: + tmpValCfg1 &= ~(1 << 7); + break; + case GLB_AHB_CLOCK_IP_SF_CTRL: + tmpValCfg1 &= ~(1 << 11); + break; + case GLB_AHB_CLOCK_IP_UART0: + tmpValCfg1 &= ~(1 << 16); + break; + case GLB_AHB_CLOCK_IP_SPI: + tmpValCfg1 &= ~(1 << 18); + break; + case GLB_AHB_CLOCK_IP_I2C: + tmpValCfg1 &= ~(1 << 19); + break; + case GLB_AHB_CLOCK_IP_PWM: + tmpValCfg1 &= ~(1 << 20); + break; + case GLB_AHB_CLOCK_IP_TIMER: + tmpValCfg1 &= ~(1 << 21); + break; + case GLB_AHB_CLOCK_IP_IR: + tmpValCfg1 &= ~(1 << 22); + break; + case GLB_AHB_CLOCK_IP_CHECKSUM: + tmpValCfg1 &= ~(1 << 23); + break; + case GLB_AHB_CLOCK_IP_KYS: + tmpValCfg1 &= ~(1 << 25); + break; + case GLB_AHB_CLOCK_IP_AUDIO: + tmpValCfg1 &= ~(1 << 29); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: + tmpValCfg2 &= ~(1 << 4); + break; + case GLB_AHB_CLOCK_IP_ZB_NORMAL: + tmpValCfg2 &= ~(1 << 0); + break; + default: + break; + } + } + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief release IPs clock + * + * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips) +{ + /* api request from cjy */ + + uint32_t tmpValCfg0 = 0; + uint32_t tmpValCfg1 = 0; + uint32_t tmpValCfg2 = 0; + uint32_t bitfield = 0; + + tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); + tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); + while (ips) { + if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { + switch (bitfield) { + case GLB_AHB_CLOCK_IP_CPU: + tmpValCfg0 |= (1 << 0); + break; + case GLB_AHB_CLOCK_IP_SEC: + tmpValCfg0 |= (1 << 2); + tmpValCfg1 |= (1 << 3); + tmpValCfg1 |= (1 << 4); + break; + case GLB_AHB_CLOCK_IP_DMA_0: + tmpValCfg0 |= (1 << 3); + tmpValCfg1 |= (1 << 12); + break; + case GLB_AHB_CLOCK_IP_CCI: + tmpValCfg0 |= (1 << 4); + break; + case GLB_AHB_CLOCK_IP_GPIP: + tmpValCfg1 |= (1 << 2); + break; + case GLB_AHB_CLOCK_IP_TZC: + tmpValCfg1 |= (1 << 5); + break; + case GLB_AHB_CLOCK_IP_EF_CTRL: + tmpValCfg1 |= (1 << 7); + break; + case GLB_AHB_CLOCK_IP_SF_CTRL: + tmpValCfg1 |= (1 << 11); + break; + case GLB_AHB_CLOCK_IP_UART0: + tmpValCfg1 |= (1 << 16); + break; + case GLB_AHB_CLOCK_IP_SPI: + tmpValCfg1 |= (1 << 18); + break; + case GLB_AHB_CLOCK_IP_I2C: + tmpValCfg1 |= (1 << 19); + break; + case GLB_AHB_CLOCK_IP_PWM: + tmpValCfg1 |= (1 << 20); + break; + case GLB_AHB_CLOCK_IP_TIMER: + tmpValCfg1 |= (1 << 21); + break; + case GLB_AHB_CLOCK_IP_IR: + tmpValCfg1 |= (1 << 22); + break; + case GLB_AHB_CLOCK_IP_CHECKSUM: + tmpValCfg1 |= (1 << 23); + break; + case GLB_AHB_CLOCK_IP_KYS: + tmpValCfg1 |= (1 << 25); + break; + case GLB_AHB_CLOCK_IP_AUDIO: + tmpValCfg1 |= (1 << 29); + break; + case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: + tmpValCfg2 |= (1 << 4); + break; + case GLB_AHB_CLOCK_IP_ZB_NORMAL: + tmpValCfg2 |= (1 << 0); + break; + default: + break; + } + } + } + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief RTC mode set + * + * @param rtcMode: RTC_MODE_LOWPOWER or RTC_MODE_NORMAL + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_RTC_Mode(RTC_MODE_Type rtcMode) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_RTC_MODE_TYPE(rtcMode)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_NEW_RTC_TIME_H); + if (rtcMode == RTC_MODE_LOWPOWER) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_RTC_TIMER_LATCH_EN); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_RTC_TIMER_LATCH_EN); + } + BL_WR_REG(GLB_BASE, GLB_NEW_RTC_TIME_H, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX init + * + * @param BmxCfg: BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler); + Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN); + BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get BMX error status + * + * @param errType: BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get BMX error address + * + * @param None + * + * @return NP BMX error address + * +*******************************************************************************/ +uint32_t GLB_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief BMX bus error clear set + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_BMX_BusErrClr_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_CLR); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_CLR); + } + BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX error interrupt callback install + * + * @param intType: BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType)); + + glbBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_ERR_IRQHandler(void) +{ + BMX_ERR_INT_Type intType; + + for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) { + if (glbBmxErrIntCbfArra[intType] != NULL) { + glbBmxErrIntCbfArra[intType](); + } + } + + while (1) { + //MSG("BMX_ERR_IRQHandler\r\n"); + BL702L_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief BMX timeout interrupt callback install + * + * @param intType: BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType)); + + glbBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void BMX_TO_IRQHandler(void) +{ + BMX_TO_INT_Type intType; + + for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) { + if (glbBmxToIntCbfArra[intType] != NULL) { + glbBmxToIntCbfArra[intType](); + } + } + + while (1) { + //MSG("BMX_TO_IRQHandler\r\n"); + BL702L_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief set sram_param value + * + * @param value: value, 18bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SRAM_PARM, value); + BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get sram_parm value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_SRAM_PARM(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SRAM_PARM), GLB_REG_SRAM_PARM); +} + +/****************************************************************************/ /** + * @brief set ocram_param value + * + * @param value: value, 11bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_OCRAM_PARM(uint32_t value) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_OCRAM_PARM, value); + BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get ocram_parm value + * + * @param None + * + * @return value + * +*******************************************************************************/ +uint32_t GLB_Get_OCRAM_PARM(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SRAM_PARM), GLB_REG_OCRAM_PARM); +} + +/****************************************************************************/ /** + * @brief select EM type + * + * @param emType: EM type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_EM_TYPE(emType)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Key Scan Column Drive + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO_O latch mode set + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_O_Latch_Mode_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_GPIO_O_LATCH_MODE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_GPIO_O_LATCH_MODE); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap JTAG gpio pins function + * + * @param swapSel: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief CCI use GPIO 0 1 2 7 + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief CCI use JTAG pin + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief swap SPI0 MOSI with MISO + * + * @param newState: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select SPI_0 act mode + * + * @param mod: SPI work mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable or disable flash gpio scenario + * + * @param ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Scenario(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_FLASH2_SCENARIO); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_FLASH2_SCENARIO); + } + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set embedded flash io parameter + * + * @param reverse: Select embedded flash interface reverse + * @param swapIo3Io0: Select embedded flash swap io0 with io3 + * @param swapIo2Cs: Select embedded flash swap cs with io2 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Embedded_FLash_IO_PARM(uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SFLASH_REVERSE, reverse); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SFLASH_SWAP_IO0_IO3, swapIo3Io0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SFLASH_SWAP_CS_IO2, swapIo2Cs); + + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set MTimer clock + * + * @param enable: enable or disable MTimer clock + * @param clkSel: clock selection + * @param div: divider, 0~0x1F stand for 1~0x20 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel)); + CHECK_PARAM((div <= 0x1F)); + + /* disable MTimer clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div); + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN); + } + BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set ADC clock + * + * @param enable: enable or disable ADC clock + * @param clkSel: ADC clock selection + * @param div: divider, 0~63 stand for 1~64 divider + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_SRC_Type clkSel, uint8_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_ADC_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x3F)); + + /* disable ADC clock first */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); + } + BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set DIG 32K clock + * + * @param enable: enable or disable DIG 32K clock + * @param compensation: enable or disable DIG 32K clock compensation + * @param clkSel: clock selection + * @param div: divider, 2 ~ 0x7FF + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, GLB_DIG_CLK_SRC_Type clkSel, uint16_t div) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_GLB_DIG_CLK_SRC_TYPE(clkSel)); + CHECK_PARAM((div <= 0x7FF)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (compensation) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); + } + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SW wakeup BLE even BLE in infinite sleep set + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_SW_BLE_WAKEUP_REQ_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SW_BLE_WAKEUP_REQ); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SW_BLE_WAKEUP_REQ); + } + BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select UART signal function + * + * @param sig: UART signal + * @param fun: UART function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) +{ + uint32_t sig_pos = 0; + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig)); + CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0); + sig_pos = (sig * 4); + /* Clear original val */ + tmpVal &= (~(0xf << sig_pos)); + /* Set new value */ + tmpVal |= (fun << sig_pos); + BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power off DLL + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_DLL(void) +{ + uint32_t tmpVal = 0; + + /* GLB->dll.BF.ppu_dll = 0; */ + /* GLB->dll.BF.pu_dll = 0; */ + /* GLB->dll.BF.dll_reset = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief power on DLL + * + * @param xtalType: DLL xtal type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType)); + + /* GLB->dll.BF.dll_refclk_sel = XXX; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + switch (xtalType) { + case GLB_DLL_XTAL_NONE: + return ERROR; + case GLB_DLL_XTAL_32M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 0); + break; + case GLB_DLL_XTAL_RC32M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 1); + break; + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + /* GLB->dll.BF.dll_prechg_sel = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_PRECHG_SEL, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + /* GLB->dll.BF.ppu_dll = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + BL702L_Delay_US(2); + + /* GLB->dll.BF.pu_dll = 1; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 1); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + BL702L_Delay_US(2); + + /* GLB->dll.BF.dll_reset = 0; */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 0); + BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); + + /* delay for settling */ + BL702L_Delay_US(5); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief enable all DLL output clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1_RF, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV63, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV21, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV5, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV3, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV2, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1, 1); + BL_WR_REG(GLB_BASE, GLB_DLL2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief enable one of DLL output clock + * + * @param dllClk: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL2); + switch (dllClk) { + case GLB_DLL_CLK_RF: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1_RF, 1); + break; + case GLB_DLL_CLK_2P032M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV63, 1); + break; + case GLB_DLL_CLK_6P095M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV21, 1); + break; + case GLB_DLL_CLK_25P6M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV5, 1); + break; + case GLB_DLL_CLK_42P67M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV3, 1); + break; + case GLB_DLL_CLK_64M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV2, 1); + break; + case GLB_DLL_CLK_128M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1, 1); + break; + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_DLL2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief disable all DLL output clock + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_All_Clks(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1_RF, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV63, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV21, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV5, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV3, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV2, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1, 0); + BL_WR_REG(GLB_BASE, GLB_DLL2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief disable one of DLL output clock + * + * @param dllClk: None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk)); + + tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL2); + switch (dllClk) { + case GLB_DLL_CLK_RF: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1_RF, 0); + break; + case GLB_DLL_CLK_2P032M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV63, 0); + break; + case GLB_DLL_CLK_6P095M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV21, 0); + break; + case GLB_DLL_CLK_25P6M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV5, 0); + break; + case GLB_DLL_CLK_42P67M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV3, 0); + break; + case GLB_DLL_CLK_64M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV2, 0); + break; + case GLB_DLL_CLK_128M: + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_EN_DIV1, 0); + break; + + default: + break; + } + BL_WR_REG(GLB_BASE, GLB_DLL2, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set flash id value + * + * @param idValue: flash id value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue) +{ + BL_WR_REG(GLB_BASE, GLB_RSV0, (idValue | BFLB_FLASH_ID_VALID_FLAG)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get flash id value + * + * @param None + * + * @return flash id + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_RSV0); + if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) { + return (tmpVal & BFLB_FLASH_ID_VALID_MASK); + } + + return 0x00000000; +} + +/****************************************************************************/ /** + * @brief Trim RC32M + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_RC32M(void) +{ + bflb_ef_ctrl_com_trim_t trim; + int32_t tmpVal = 0; + + bflb_ef_ctrl_read_common_trim(NULL, "rc32m", &trim, 1); + if (trim.en) { + if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_RC32M_CTRL0); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_RC32M_EXT_CODE_EN); + BL_WR_REG(GLB_BASE, GLB_RC32M_CTRL0, tmpVal); + arch_delay_us(2); + tmpVal = BL_RD_REG(GLB_BASE, GLB_RC32M_CTRL1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_RC32M_CODE_FR_EXT2, trim.value); + BL_WR_REG(GLB_BASE, GLB_RC32M_CTRL1, tmpVal); + tmpVal = BL_RD_REG(GLB_BASE, GLB_RC32M_CTRL1); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_RC32M_EXT_CODE_SEL); + BL_WR_REG(GLB_BASE, GLB_RC32M_CTRL1, tmpVal); + /* hw_5T + sw_5T */ + arch_delay_us(1); + return SUCCESS; + } + } + + return ERROR; +} + +/****************************************************************************/ /** + * @brief Set xtal_cnt_32k_process(0x4000E04C[29]) + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Set_Xtal_Cnt32k_Process(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_XTAL_DEG_32K); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_XTAL_CNT_32K_SW_TRIG_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_XTAL_CNT_32K_DONE); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_START_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_END_PS); + BL_WR_REG(GLB_BASE, GLB_XTAL_DEG_32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Clear xtal_cnt_32k_done(0x4000E04C[30]) + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Clear_Xtal_Cnt32k_Done(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_XTAL_DEG_32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_XTAL_CNT_32K_SW_TRIG_PS); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CLR_XTAL_CNT_32K_DONE); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_START_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_END_PS); + BL_WR_REG(GLB_BASE, GLB_XTAL_DEG_32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GLB start RC32K deg + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_RC32K_Deg_Start(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_XTAL_DEG_32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_XTAL_CNT_32K_SW_TRIG_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_XTAL_CNT_32K_DONE); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_RC32K_DEG_START_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_END_PS); + BL_WR_REG(GLB_BASE, GLB_XTAL_DEG_32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GLB end RC32K deg + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_RC32K_Deg_End(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_XTAL_DEG_32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_XTAL_CNT_32K_SW_TRIG_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_XTAL_CNT_32K_DONE); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_START_PS); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_RC32K_DEG_END_PS); + BL_WR_REG(GLB_BASE, GLB_XTAL_DEG_32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GLB enable or disable RC32K deg + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_RC32K_Deg_Enable(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_XTAL_DEG_32K); + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_RC32K_DEG_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_RC32K_DEG_EN); + } + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_XTAL_CNT_32K_SW_TRIG_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_XTAL_CNT_32K_DONE); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_START_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_END_PS); + BL_WR_REG(GLB_BASE, GLB_XTAL_DEG_32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GLB set XTAL deg cnt limit value + * + * @param cnt: 0~255 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Xtal_Deg_Cnt_Limit_Set(uint8_t cnt) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_XTAL_DEG_32K); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_XTAL_DEG_CNT_LIMIT, cnt); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_XTAL_CNT_32K_SW_TRIG_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_XTAL_CNT_32K_DONE); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_START_PS); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_RC32K_DEG_END_PS); + BL_WR_REG(GLB_BASE, GLB_XTAL_DEG_32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Enable(void) +{ + uint32_t tmpVal = 0; + + /* Enable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable ir led driver + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Disable(void) +{ + uint32_t tmpVal = 0; + + /* Disable led driver */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable ir led driver gpio output + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_IR_LED_Type led) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_IR_LED_TYPE(led)); + + if (led == GLB_IR_LED0) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 1); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } else if (led == GLB_IR_LED1) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 2); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable ir led driver gpio output + * + * @param gpio: IR gpio selected + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_IR_LED_Type led) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_GLB_IR_LED_TYPE(led)); + + if (led == GLB_IR_LED0) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~1); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } else if (led == GLB_IR_LED1) { + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~2); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set ir led driver ibias + * + * @param ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias) +{ + uint32_t tmpVal = 0; + + /* Set driver ibias */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0x7); + BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal); + + return SUCCESS; +} + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_glb_gpio.c b/drivers/soc/bl702l/std/src/bl702l_glb_gpio.c new file mode 100644 index 000000000..d77adb1ea --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_glb_gpio.c @@ -0,0 +1,719 @@ +/** + ****************************************************************************** + * @file bl702l_glb_gpio.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_glb.h" +#include "bl702l_glb_gpio.h" +#include "bl702l_hbn.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup GLB + * @{ + */ + +/** @defgroup GLB_Private_Macros + * @{ + */ + +#define GLB_GPIO_Get_Reg(pin) (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4) +#define GLB_GPIO_INT0_NUM (32) +#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) + +/*@} end of group GLB_Private_Macros */ + +/** @defgroup GLB_Private_Types + * @{ + */ + +/*@} end of group GLB_Private_Types */ + +/** @defgroup GLB_Private_Variables + * @{ + */ +static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +/*@} end of group GLB_Private_Variables */ + +/** @defgroup GLB_Global_Variables + * @{ + */ + +/*@} end of group GLB_Global_Variables */ + +/** @defgroup GLB_Private_Fun_Declaration + * @{ + */ + +/*@} end of group GLB_Private_Fun_Declaration */ + +/** @defgroup GLB_Private_Functions + * @{ + */ + +/*@} end of group GLB_Private_Functions */ + +/** @defgroup GLB_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief GPIO initialization + * + * @param cfg: GPIO configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg) +{ + uint8_t gpioPin = cfg->gpioPin; + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + /* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */ + /* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */ + /* drive strength(drive) = 2 <=> 11.2mA @ 3.3V */ + /* drive strength(drive) = 3 <=> 12.8mA @ 3.3V */ + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + if (gpioPin % 2 == 0) { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + if (gpioPin == GLB_GPIO_PIN_30) { + *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 25); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun); + } else { + if (cfg->gpioMode != GPIO_MODE_ANALOG) { + /* not analog mode */ + + /* Set input or output */ + if (cfg->gpioMode == GPIO_MODE_OUTPUT) { + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut |= (1 << pos); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + + /* Set pull up or down */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + if (cfg->pullType == GPIO_PULL_UP) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + } else if (cfg->pullType == GPIO_PULL_DOWN) { + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + if (gpioPin == GLB_GPIO_PIN_31) { + *(uint32_t *)(HBN_BASE + HBN_PAD_CTRL_0_OFFSET) &= ~(1 << 26); + } + } else { + /* analog mode */ + + /* clear ie && oe */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + tmpOut &= ~(1 << pos); + + /* clear pu && pd */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD); + } + + /* set drive && smt && func */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun); + } + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief init GPIO function in pin list + * + * @param gpioFun: GPIO pin function + * @param pinList: GPIO pin list + * @param cnt: GPIO pin count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt) +{ + GLB_GPIO_Cfg_Type gpioCfg = { + .gpioPin = GLB_GPIO_PIN_0, + .gpioFun = (uint8_t)gpioFun, + .gpioMode = GPIO_MODE_AF, + .pullType = GPIO_PULL_UP, + .drive = 1, + .smtCtrl = 1 + }; + + if (gpioFun == GPIO_FUN_ANALOG) { + gpioCfg.gpioMode = GPIO_MODE_ANALOG; + } + + for (uint8_t i = 0; i < cnt; i++) { + gpioCfg.gpioPin = pinList[i]; + GLB_GPIO_Init(&gpioCfg); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set GPIO output mode in SWGPIO function + * + * @param gpioPin: GPIO pin + * @param mode: output mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_OUTPUT_Mode_Set(GLB_GPIO_Type gpioPin, GLB_GPIO_OUTPUT_MODE_Type mode) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + if (gpioPin % 2 == 0) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_MODE, mode); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_MODE, mode); + } + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set input function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + uint32_t pinOffset; + + pinOffset = (gpioPin >> 1) << 2; + tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset); + if (gpioPin % 2 == 0) { + /* [0] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE); + } else { + /* [16] is ie */ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE); + } + *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set output function enable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set output function disable + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34); + tmpVal = tmpVal & ~(1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO set High-Z + * + * @param gpioPin: GPIO pin + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin) +{ + uint32_t *pOut; + uint32_t pos; + uint32_t tmpOut; + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* pu=0, pd=0, ie=0 */ + if (gpioPin % 2 == 0) { + tmpVal = (tmpVal & 0xffffff00); + } else { + tmpVal = (tmpVal & 0xff00ffff); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2)); + pos = gpioPin % 32; + tmpOut = *pOut; + + /* Disable output anyway*/ + tmpOut &= (~(1 << pos)); + *pOut = tmpOut; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + /* func_sel=swgpio */ + if (gpioPin % 2 == 0) { + tmpVal = (tmpVal & 0xffff00ff); + tmpVal |= 0x0B00; + } else { + tmpVal = (tmpVal & 0x00ffffff); + tmpVal |= (0x0B00 << 16); + } + + BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal); + + /* Disable output anyway*/ + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GPIO function + * + * @param gpioPin: GPIO type + * + * @return GPIO function + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4); + + if (gpioPin % 2 == 0) { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL); + } else { + return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL); + } +} +#endif + +/****************************************************************************/ /** + * @brief Write GPIO + * + * @param gpioPin: GPIO type + * @param val: GPIO value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val) +{ + uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + uint32_t tmpOut; + + tmpOut = *pOut; + if (val > 0) { + tmpOut |= (1 << pos); + } else { + tmpOut &= (~(1 << pos)); + } + *pOut = tmpOut; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Read GPIO + * + * @param gpioPin: GPIO type + * + * @return GPIO value + * +*******************************************************************************/ +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin) +{ + uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2)); + uint32_t pos = gpioPin % 32; + + if ((*p) & (1 << pos)) { + return 1; + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief turn GPIO output high + * + * @param gpioPin: GPIO type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin) +{ + BL_WR_WORD(GLB_BASE + GLB_GPIO_CFGCTL35_OFFSET, 1 << gpioPin); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief turn GPIO output low + * + * @param gpioPin: GPIO type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin) +{ + BL_WR_WORD(GLB_BASE + GLB_GPIO_CFGCTL36_OFFSET, 1 << gpioPin); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intMask: GPIO interrupt MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1); + if (intMask == MASK) { + tmpVal = tmpVal | (1 << gpioPin); + } else { + tmpVal = tmpVal & ~(1 << gpioPin); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mask + * + * @param gpioPin: GPIO type + * @param intClear: GPIO interrupt clear or unclear + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1); + tmpVal = tmpVal | (1 << gpioPin); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get GLB GPIO interrrupt status + * + * @param gpioPin: GPIO type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin) +{ + uint32_t tmpVal = 0; + + if (gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1); + } + + return (tmpVal & (1 << gpioPin)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief Set GLB GPIO interrupt mode + * + * @param gpioPin: GPIO type + * @param intCtlMod: GPIO interrupt control mode + * @param intTrgMod: GPIO interrupt trigger mode + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg) +{ + uint32_t tmpVal; + uint32_t tmpGpioPin; + + if (intCfg->gpioPin < GLB_GPIO_PIN_8) { + /* GPIO0 ~ GPIO7 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1); + tmpGpioPin = intCfg->gpioPin; + tmpVal = (tmpVal & ~(0xf << (4 * tmpGpioPin))) | (intCfg->trig << (4 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal); + } else if (intCfg->gpioPin < GLB_GPIO_PIN_16) { + /* GPIO8 ~ GPIO15 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2); + tmpGpioPin = intCfg->gpioPin - GLB_GPIO_PIN_8; + tmpVal = (tmpVal & ~(0xf << (4 * tmpGpioPin))) | (intCfg->trig << (4 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal); + } else if (intCfg->gpioPin < GLB_GPIO_PIN_24) { + /* GPIO16 ~ GPIO23 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3); + tmpGpioPin = intCfg->gpioPin - GLB_GPIO_PIN_16; + tmpVal = (tmpVal & ~(0xf << (4 * tmpGpioPin))) | (intCfg->trig << (4 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal); + } else if (intCfg->gpioPin < GLB_GPIO_PIN_MAX) { + /* GPIO24 ~ GPIO32 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4); + tmpGpioPin = intCfg->gpioPin - GLB_GPIO_PIN_24; + tmpVal = (tmpVal & ~(0xf << (4 * tmpGpioPin))) | (intCfg->trig << (4 * tmpGpioPin)); + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4, tmpVal); + } + if (intCfg->gpioPin < 32) { + /* GPIO0 ~ GPIO31 */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1); + if (intCfg->intMask == MASK) { + tmpVal = tmpVal | (1 << intCfg->gpioPin); + } else { + tmpVal = tmpVal & ~(1 << intCfg->gpioPin); + } + BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO INT0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler callback install + * + * @param gpioPin: GPIO pin type + * @param cbFun: callback function + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun) +{ + if (gpioPin < 32) { + glbGpioInt0CbfArra[gpioPin] = cbFun; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief GPIO interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void GPIO_INT0_IRQHandler(void) +{ + GLB_GPIO_Type gpioPin; + uint32_t timeOut = 0; + + for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_31; gpioPin++) { + if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) { + GLB_Clr_GPIO_IntStatus(gpioPin); + + /* timeout check */ + timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; + do { + timeOut--; + } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut); + if (!timeOut) { + //MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); + } + + /* if timeOut==0, GPIO interrupt status not cleared */ + //GLB_GPIO_IntClear(gpioPin, RESET); + + if (glbGpioInt0CbfArra[gpioPin] != NULL) { + /* Call the callback function */ + glbGpioInt0CbfArra[gpioPin](); + } + } + } +} +#endif + +/*@} end of group GLB_Public_Functions */ + +/*@} end of group GLB */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_hbn.c b/drivers/soc/bl702l/std/src/bl702l_hbn.c new file mode 100644 index 000000000..51bf0b449 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_hbn.c @@ -0,0 +1,1738 @@ +/** + ****************************************************************************** + * @file bl702l_hbn.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_hbn.h" +#include "bl702l_glb.h" +#include "bflb_acomp.h" +#include "bflb_xip_sflash.h" +#include "bl702l_ef_cfg.h" +#include + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup HBN + * @{ + */ + +/** @defgroup HBN_Private_Macros + * @{ + */ +#define HBN_CLK_SET_DUMMY_WAIT \ + { \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + __NOP(); \ + } + +/*@} end of group HBN_Private_Macros */ + +/** @defgroup HBN_Private_Types + * @{ + */ + +/*@} end of group HBN_Private_Types */ + +/** @defgroup HBN_Private_Variables + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_INT_MAX] = { NULL }; +static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_INT_MAX] = { NULL }; +#endif + +/*@} end of group HBN_Private_Variables */ + +/** @defgroup HBN_Global_Variables + * @{ + */ + +/*@} end of group HBN_Global_Variables */ + +/** @defgroup HBN_Private_Fun_Declaration + * @{ + */ + +/*@} end of group HBN_Private_Fun_Declaration */ + +/** @defgroup HBN_Private_Functions + * @{ + */ + +/*@} end of group HBN_Private_Functions */ + +/** @defgroup HBN_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Enter HBN + * + * @param cfg: HBN APP Config + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) +{ + uint32_t valLow = 0, valHigh = 0; + uint64_t val; + + /* work clock select */ + if (cfg->useXtal32k) { + HBN_32K_Sel(HBN_32K_XTAL); + } else { + HBN_32K_Sel(HBN_32K_RC); + HBN_Power_Off_Xtal_32K(); + } + + /* turn off RC32K during HBN */ + if ((cfg->hbnLevel) >= HBN_LEVEL_2) { + HBN_Power_Off_RC32K(); + } else { + HBN_Power_On_RC32K(); + } + + /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */ + HBN_Hw_Pu_Pd_Cfg(cfg->hw_pu_pd_en); + + /* HBN RTC config and enable */ + if (cfg->sleepTime != 0) { + HBN_Get_RTC_Timer_Val(&valLow, &valHigh); + val = valLow + ((uint64_t)valHigh << 32); + val += cfg->sleepTime; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } + + HBN_Power_Down_Flash(cfg->flashCfg); + + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + + /* power off xtal */ + AON_Power_Off_XTAL(); + + HBN_Enable(cfg->ldoLevel, cfg->hbnLevel); +} + +/** + * @brief Set Wakeup HBN or PDS by GPIOX + * + * @param gpio_wakeup_src PIN Wakeup PDS or HBN + * @param gpio_trig_type HBN GPIO interrupt trigger type + */ +void ATTR_TCM_SECTION HBN_GPIO_Wakeup_Set(uint16_t gpio_wakeup_src, HBN_GPIO_INT_Trigger_Type gpio_trig_type) +{ + HBN_Pin_WakeUp_Mask(~(gpio_wakeup_src)); + + if (gpio_wakeup_src != 0) { + HBN_Aon_Pad_IeSmt_Cfg((uint8_t)(gpio_wakeup_src & 0x7f)); + HBN_Comm_Pad_Wakeup_En_Cfg((uint8_t)((gpio_wakeup_src & 0x380) >> 7)); + HBN_GPIO_INT_Enable(gpio_trig_type); + } else { + HBN_Aon_Pad_IeSmt_Cfg(0); + HBN_Comm_Pad_Wakeup_En_Cfg(0); + } +} + +/****************************************************************************/ /** + * @brief power down and switch clock + * + * @param flashCfg: None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg) +{ + spi_flash_cfg_type bhFlashCfg; + + if (flashCfg == NULL) { + /* fix this some time */ + /* SFlash_Cache_Flush(); */ + bflb_xip_sflash_read_via_cache_need_lock(BL702L_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(spi_flash_cfg_type), 1, 1); + /* fix this some time */ + /* SFlash_Cache_Flush(); */ + + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + bflb_sflash_reset_continue_read(&bhFlashCfg); + } else { + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + bflb_sflash_reset_continue_read(flashCfg); + } + + bflb_sflash_powerdown(); +} + +/****************************************************************************/ /** + * @brief Enable HBN mode + * + * @param aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to + * 0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01. + * @param ldoLevel: LDO volatge level + * @param hbnLevel: HBN work level + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION HBN_Enable(HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel)); + + /* HBN mode LDO level */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + /* Select RC32M */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Set HBN flag */ + BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + + /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ + switch (hbnLevel) { + case HBN_LEVEL_0: + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_1: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_2: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + case HBN_LEVEL_3: + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC); + break; + + default: + break; + } + + /* Set power on option:0 for por reset twice for robust 1 for reset only once*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + *(volatile uint8_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET + HBN_OUT0_IRQn) = 0; + *(volatile uint8_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET + HBN_OUT1_IRQn) = 0; + + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); + + /* Enable HBN mode */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + while (1) { + BL702L_Delay_MS(1000); + } +} +/****************************************************************************/ /** + * @brief Reset HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Reset HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief reset HBN by software + * + * @param npXtalType: NP clock type + * @param bclkDiv: NP clock div + * @param apXtalType: AP clock type + * @param fclkDiv: AP clock div + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv) +{ + uint32_t tmp[12]; + + tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL); + tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L); + tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H); + tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG); + tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH); + tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL); + tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0); + tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1); + tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2); + /* DO HBN reset */ + HBN_Reset(); + /* HBN need 3 32k cyclce to recovery */ + BL702L_Delay_US(100); + /* Recover HBN value */ + BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]); + BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]); + BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]); + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]); + BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]); + BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]); + BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]); + BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]); + BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]); + BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable HBN mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Disable HBN mode */ + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get HBN bor out state + * + * @param None + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_BOR_OUT_State(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_MISC), HBN_R_BOD_OUT) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set HBN bor config + * + * @param enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset + * @param threshold: bor threshold + * @param mode: bor work mode with por + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold)); + CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + + if (enable) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 1); + } else { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 0); + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, threshold); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_SEL, mode); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief VDD11_AON voltage out select at PDS or HBN status + * + * @param ldoLevel: LDO11 volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_PDS_Set_Ldo11_Vout(HBN_LDO11_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO11_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11aon voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11soc voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set ldo11 all voltage out + * + * @param ldoLevel: LDO volatge level + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN select 32K + * + * @param clkType: HBN 32k clock type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType)); + + HBN_Trim_RC32K(); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select uart clock source + * + * @param clkSel: uart clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + if (clkSel == HBN_UART_CLK_XCLK) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_UART_CLK_SEL2); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_UART_CLK_SEL2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel); + } + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select xclk clock source + * + * @param xClk: xclk clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (xClk) { + case HBN_XCLK_CLK_RC32M: + tmpVal2 &= (~(1 << 0)); + break; + + case HBN_XCLK_CLK_XTAL: + tmpVal2 |= (1 << 0); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Select root clk source + * + * @param rootClk: root clock type selection + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL); + + switch (rootClk) { + case HBN_ROOT_CLK_RC32M: + tmpVal2 = 0x0; + break; + + case HBN_ROOT_CLK_XTAL: + tmpVal2 = 0x1; + break; + + case HBN_ROOT_CLK_DLL: + tmpVal2 |= (1 << 1); + break; + + default: + break; + } + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + HBN_CLK_SET_DUMMY_WAIT; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief set HBN_RAM sleep mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_slp(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set HBN_RAM retension mode + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_HRAM_Ret(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET); + BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + /* Delay >1s */ + arch_delay_us(1100); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off XTAL 32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); + BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power on RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + /* Delay >800us */ + arch_delay_us(880); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Power off RC3K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Trim RC32K + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void) +{ + Efuse_Common_Trim_Type trim; + int32_t tmpVal = 0; + + EF_Ctrl_Read_Common_Trim("rc32k", &trim); + + if (trim.en) { + if (trim.parity == EF_Ctrl_Get_Trim_Parity(trim.value, trim.len)) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CAP_SEL, trim.value); + BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal); + arch_delay_us(2); + return SUCCESS; + } + } + + return ERROR; +} +#endif + +/****************************************************************************/ /** + * @brief Get HBN status flag + * + * @param None + * + * @return HBN status flag value + * +*******************************************************************************/ +uint32_t HBN_Get_Status_Flag(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV0); +} + +/****************************************************************************/ /** + * @brief Set HBN status flag + * + * @param flag: Status Flag + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag) +{ + BL_WR_REG(HBN_BASE, HBN_RSV0, flag); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get HBN wakeup address + * + * @param None + * + * @return HBN wakeup address + * +*******************************************************************************/ +uint32_t HBN_Get_Wakeup_Addr(void) +{ + return BL_RD_REG(HBN_BASE, HBN_RSV1); +} + +/****************************************************************************/ /** + * @brief Set HBN wakeup address + * + * @param addr: HBN wakeup address + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr) +{ + BL_WR_REG(HBN_BASE, HBN_RSV1, addr); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get user boot config + * + * @param None + * + * @return user boot config + * +*******************************************************************************/ +uint8_t HBN_Get_User_Boot_Config(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2); + if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) { + return BL_GET_REG_BITS_VAL(tmpVal, HBN_USER_BOOT_SEL); + } + + return 0x00; +} + +/****************************************************************************/ /** + * @brief Set user boot config + * + * @param ubCfg: user boot config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_User_Boot_Config(uint8_t ubCfg) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_USER_BOOT_SEL, ubCfg); + BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer counter + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_RTC_Counter(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set RTC control bit0 */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN set RTC timer configuration + * + * @param delay: RTC interrupt delay 32 clocks + * @param compValLow: RTC interrupt commpare value low 32 bits + * @param compValHigh: RTC interrupt commpare value high 32 bits + * @param compMode: RTC interrupt commpare + * mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay)); + + BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow); + BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Set interrupt delay option */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay); + /* Set RTC compare mode */ + tmpVal |= (compMode << 1); + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get RTC async timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_NEW_RTC_TIME_H); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_RTC_TIMER_LATCH_EN); + if (tmpVal == 0) { + /* Tigger RTC val read */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); + BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); + + /* Read RTC val */ + *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); + *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); + } else { + /* Read RTC val */ + *valLow = BL_RD_REG(GLB_BASE, GLB_NEW_RTC_TIME_L); + *valHigh = (BL_RD_REG(GLB_BASE, GLB_NEW_RTC_TIME_H) & 0xff); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get RTC timer count value + * + * @param valLow: RTC count value pointer for low 32 bits + * @param valHigh: RTC count value pointer for high 8 bits + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh) +{ + uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1; + uint64_t val, val1; + + do { + HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh); + val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow); + HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1); + val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1); + } while (val1 < val); + + *valLow = tmpValLow1; + *valHigh = tmpValHigh1; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_RTC_INT(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */ + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable GPIO interrupt + * + * @param gpioIntTrigType: HBN GPIO interrupt trigger type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable GPIO interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_GPIO_INT_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN get interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT); + + if (tmpVal & (1 << irqType)) { + return SET; + } else { + return RESET; + } +} + +/****************************************************************************/ /** + * @brief HBN get pin wakeup mode value + * + * @param None + * + * @return HBN pin wakeup mode value + * +*******************************************************************************/ +uint8_t HBN_Get_Pin_Wakeup_Mode(void) +{ + return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE); +} + +/****************************************************************************/ /** + * @brief HBN clear interrupt status + * + * @param irqType: HBN interrupt type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_HBN_INT_TYPE(irqType)); + + /* set clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal |= (1 << irqType); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + /* unset clear bit */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR); + tmpVal &= (~(1 << irqType)); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN hardware pullup or pulldown configuration + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + } + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN Config Common pad Wakeup enable + * + * @param padCfg: GPIO Wakeup Enable for HBN + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Comm_Pad_Wakeup_En_Cfg(uint8_t padCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_GPIO_WAKEUP_EN_AON, padCfg); + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN Config AON pad input and SMT + * + * @param padCfg: AON pad config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_GPIO_IE_SMT, padCfg); + BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN Config PDS pad keep select + * + * @param keepSel: PDS pad keep select + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +__WEAK +BL_Err_Type HBN_Enable_PDS_Pad_Keep(uint32_t keepSel) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_AON_GPIO_ISO_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_CR_GPIO_KEEP_EN,keepSel); + BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal); + + return SUCCESS; +} +/****************************************************************************/ /** + * @brief HBN wakeup pin mask configuration + * + * @param maskVal: mask value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint16_t maskVal) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN aon pad cfg configuration + * + * @param aonPadHwCtrlEn: hw control aon pad enable + * @param aonGpio: aon pad number + * @param aonPadCfg: aon pad configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg) +{ + uint32_t tmpVal0; + uint32_t tmpVal1; + uint32_t enAonCtrlGpio; + uint32_t aonPadIeSmt; + uint32_t aonPadPu; + uint32_t aonPadPd; + uint32_t aonPadOe; + + CHECK_PARAM(IS_HBN_AON_PAD_TYPE(aonGpio)); + + if (NULL == aonPadCfg) { + return ERROR; + } + + /* hbn_pad_ctrl_0 */ + tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0); + enAonCtrlGpio = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO); + if (aonPadCfg->ctrlEn) { + enAonCtrlGpio |= (1 << aonGpio); + } else { + enAonCtrlGpio &= ~(1 << aonGpio); + } + tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO, enAonCtrlGpio); + aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_GPIO_IE_SMT); + if (aonPadCfg->ie) { + aonPadIeSmt |= (1 << aonGpio); + } else { + aonPadIeSmt &= ~(1 << aonGpio); + } + tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_GPIO_IE_SMT, aonPadIeSmt); + BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0); + + /* hbn_pad_ctrl_1 */ + tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1); + aonPadPu = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_GPIO_PU); + if (aonPadCfg->pullUp) { + aonPadPu |= (1 << aonGpio); + } else { + aonPadPu &= ~(1 << aonGpio); + } + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_GPIO_PU, aonPadPu); + aonPadPd = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_GPIO_PD); + if (aonPadCfg->pullDown) { + aonPadPd |= (1 << aonGpio); + } else { + aonPadPd &= ~(1 << aonGpio); + } + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_GPIO_PD, aonPadPd); + aonPadOe = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_GPIO_OE); + if (aonPadCfg->oe) { + aonPadOe |= (1 << aonGpio); + } else { + aonPadOe &= ~(1 << aonGpio); + } + tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_GPIO_OE, aonPadOe); + BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1); + + return SUCCESS; +} + + +/****************************************************************************/ /** + * @brief HBN enable ACOMP interrupt + * + * @param acompId: HBN Acomp ID + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompId)); + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + if (acompId == AON_ACOMP0_ID) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 | edge; + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } else if (acompId == AON_ACOMP1_ID) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 | edge; + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable ACOMP interrupt + * + * @param acompId: HBN Acomp ID + * @param edge: HBN acomp interrupt edge type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge) +{ + uint32_t tmpVal; + uint32_t tmpVal2; + + CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompId)); + CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); + + if (acompId == (uint8_t)AON_ACOMP0_ID) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); + tmpVal2 = tmpVal2 & (~edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } else if (acompId == (uint8_t)AON_ACOMP1_ID) { + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); + tmpVal2 = tmpVal2 & (~edge); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN enable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Enable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOD_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN disable BOR interrupt + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Disable_BOR_IRQ(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOD_EN); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get HBN reset event status + * + * @param event: HBN reset event type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RESET_EVENT); + + return (tmpVal & (1 << event)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief clear HBN reset event status + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Clear_Reset_Event(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT); + BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN out0 install interrupt callback + * + * @param intType: HBN out0 interrupt type + * @param cbFun: HBN out0 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType)); + + hbnInt0CbfArra[intType] = cbFun; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN out1 install interrupt callback + * + * @param intType: HBN out1 interrupt type + * @param cbFun: HBN out1 interrupt callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun) +{ + /* Check the parameters */ + CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType)); + + hbnInt1CbfArra[intType] = cbFun; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief HBN GPIO debug pull config + * + * @param pupdEn: Enable or disable GPIO pull down and pull up + * @param dlyEn: Enable or disable GPIO wakeup delay function + * @param dlySec: GPIO wakeup delay sec 1 to 7 + * @param gpioIrq: HBN GPIO num + * @param gpioMask: HBN GPIO MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask) +{ + uint32_t tmpVal; + + CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7))); + CHECK_PARAM((gpioIrq >= HBN_INT_GPIO9) && (gpioIrq <= HBN_INT_GPIO13)); + + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_DLY_EN, dlyEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_DLY_SEL, dlySec); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn); + + if (gpioMask != UNMASK) { + tmpVal = tmpVal | (1 << (gpioIrq + 8)); + } else { + tmpVal = tmpVal & ~(1 << (gpioIrq + 8)); + } + + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set BOR config + * + * @param cfg: Enable or disable + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg) +{ + uint32_t tmpVal = 0; + + if (cfg->enableBorInt) { + HBN_Enable_BOR_IRQ(); + } else { + HBN_Disable_BOR_IRQ(); + } + + tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, cfg->borThreshold); + + if (cfg->enablePorInBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOD_SEL); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOD_SEL); + } + + if (cfg->enableBor) { + tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOD); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOD); + } + + BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief HBN OUT0 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT0_IRQHandler(void) +{ + if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) { + HBN_Clear_IRQ(HBN_INT_GPIO9); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO9] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO9](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) { + HBN_Clear_IRQ(HBN_INT_GPIO10); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO10] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO10](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) { + HBN_Clear_IRQ(HBN_INT_GPIO11); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO11] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO11](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) { + HBN_Clear_IRQ(HBN_INT_GPIO12); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO12] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO12](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) { + HBN_Clear_IRQ(HBN_INT_GPIO13); + + if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO13] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_GPIO13](); + } + } + + if (SET == HBN_Get_INT_State(HBN_INT_RTC)) { + HBN_Clear_IRQ(HBN_INT_RTC); + HBN_Clear_RTC_INT(); + + if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) { + hbnInt0CbfArra[HBN_OUT0_INT_RTC](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief HBN OUT1 interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void HBN_OUT1_IRQHandler(void) +{ + /* BOD */ + if (SET == HBN_Get_INT_State(HBN_INT_BOD)) { + HBN_Clear_IRQ(HBN_INT_BOD); + + if (hbnInt1CbfArra[HBN_OUT1_INT_BOD] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_BOD](); + } + } + + /* ACOMP0 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { + HBN_Clear_IRQ(HBN_INT_ACOMP0); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0](); + } + } + + /* ACOMP1 */ + if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { + HBN_Clear_IRQ(HBN_INT_ACOMP1); + + if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) { + hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1](); + } + } +} +#endif + +/****************************************************************************/ /** + * @brief HBN out0 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type HBN_Out0_IRQHandler_Install(void) +{ + Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler); + return SUCCESS; +} +#endif +/****************************************************************************/ /** + * @brief HBN out1 IRQHandler install + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type HBN_Out1_IRQHandler_Install(void) +{ + Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler); + return SUCCESS; +} +#endif +/*@} end of group HBN_Public_Functions */ + +/*@} end of group HBN */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_kys.c b/drivers/soc/bl702l/std/src/bl702l_kys.c new file mode 100644 index 000000000..cf22ae9b7 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_kys.c @@ -0,0 +1,456 @@ +/** + ****************************************************************************** + * @file bl702l_kys.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_kys.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup KYS + * @{ + */ + +/** @defgroup KYS_Private_Macros + * @{ + */ + +/*@} end of group KYS_Private_Macros */ + +/** @defgroup KYS_Private_Types + * @{ + */ + +/*@} end of group KYS_Private_Types */ + +/** @defgroup KYS_Private_Variables + * @{ + */ +static intCallback_Type *KYSIntCbfArra[KYS_INT_ALL] = { NULL }; + +/*@} end of group KYS_Private_Variables */ + +/** @defgroup KYS_Global_Variables + * @{ + */ + +/*@} end of group KYS_Global_Variables */ + +/** @defgroup KYS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group KYS_Private_Fun_Declaration */ + +/** @defgroup KYS_Private_Functions + * @{ + */ + +/*@} end of group KYS_Private_Functions */ + +/** @defgroup KYS_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief KYS initialization function + * + * @param kysCfg: KYS configuration structure pointer + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + /* Set col and row */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_NUM, kysCfg->col - 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM, kysCfg->row - 1); + + /* Enable or disable fifo mode for keycode */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_FIFO_MODE, kysCfg->fifo_mode); + + /* Set idle duration between column scans */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_RC_EXT, kysCfg->idle_duration); + + /* Enable or disable ghost key event detection */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_GHOST_EN, kysCfg->ghost_en); + + /* Enable or disable deglitch function */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_EN, kysCfg->deglitch_en); + + /* Set deglitch count */ + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_DEG_CNT, kysCfg->deglitch_cnt); + + /* Write back */ + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, tmpVal); + + // tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL2); + + // /* Set skip col and row */ + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_COL_START, kysCfg->col_start); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, KYS_ROW_START, kysCfg->row_start); + + // BL_WR_REG(KYS_BASE, KYS_KS_CTRL2, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + // Interrupt_Handler_Register(KYS_IRQn, KYS_IRQHandler); +#endif + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable KYS + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Enable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_SET_REG_BIT(tmpVal, KYS_KS_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable KYS + * + * @param None + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); + BL_WR_REG(KYS_BASE, KYS_KS_CTRL, BL_CLR_REG_BIT(tmpVal, KYS_KS_EN)); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief KYS mask or unmask interrupt + * + * @param intMask: KYS interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_IntMask(KYS_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_KYS_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_INT_EN); + + switch (intType) { + case KYS_INT_KS_DONE: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (BL_CLR_REG_BIT(tmpVal, KYS_KS_DONE_INT_EN))); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (BL_SET_REG_BIT(tmpVal, KYS_KS_DONE_INT_EN))); + } + break; + + case KYS_INT_KEYFIFO_FULL: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (tmpVal & (~(0x1 << KYS_KEYFIFO_FULL_POS)))); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (BL_SET_REG_BITS_VAL(tmpVal, KYS_KEYFIFO_INT_EN, 0x1))); + } + break; + + case KYS_INT_KEYFIFO_HALF: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (tmpVal & (~(0x1 << KYS_KEYFIFO_HALF_POS)))); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (BL_SET_REG_BITS_VAL(tmpVal, KYS_KEYFIFO_INT_EN, 0x2))); + } + break; + + case KYS_INT_KEYFIFO_QUARTER: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (tmpVal & (~(0x1 << KYS_KEYFIFO_QUARTER_POS)))); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (BL_SET_REG_BITS_VAL(tmpVal, KYS_KEYFIFO_INT_EN, 0x4))); + } + break; + + case KYS_INT_KEYFIFO_NONEMPTY: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (tmpVal & (~(0x1 << KYS_KEYFIFO_NONEMPTY_POS)))); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (BL_SET_REG_BITS_VAL(tmpVal, KYS_KEYFIFO_INT_EN, 0x8))); + } + break; + + case KYS_INT_GHOST_DET: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, BL_CLR_REG_BIT(tmpVal, KYS_GHOST_INT_EN)); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, BL_SET_REG_BIT(tmpVal, KYS_GHOST_INT_EN)); + } + break; + + case KYS_INT_ALL: + if (MASK == intMask) { + /* MASK(Disable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (tmpVal & (~((0x1 << KYS_KS_DONE_INT_EN_POS) | (0x7 << KYS_KEYFIFO_INT_EN_POS) | (0x1 << KYS_GHOST_INT_EN_POS))))); + } else { + /* UNMASK(Enable) this interrupt */ + BL_WR_REG(KYS_BASE, KYS_KS_INT_EN, (tmpVal | ((0x1 << KYS_KS_DONE_INT_EN_POS) | (0x7 << KYS_KEYFIFO_INT_EN_POS) | (0x1 << KYS_GHOST_INT_EN_POS)))); + } + break; + default: + break; + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief KYS clear interrupt + * + * @param intType + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_IntClear(KYS_INT_CLR_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_KYS_INT_CLR_TYPE(intType)); + + /* Clear certain or all interrupt */ + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_INT_STS); + + if (KYS_INT_CLR_ALL == intType) { + tmpVal |= 0x1180 << KYS_KS_DONE_CLR_POS; + } else { + tmpVal |= 1 << (intType); + } + + BL_WR_REG(KYS_BASE, KYS_KEYCODE_CLR, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Install KYS interrupt callback function + * + * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type KYS_Int_Callback_Install(KYS_INT_Type intType, intCallback_Type *cbFun) +{ + KYSIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief KYS get interrupt status + * + * @param None + * + * @return Status of interrupt + * +*******************************************************************************/ +BL_Sts_Type KYS_GetIntStatus(KYS_INT_Type intType) +{ + uint32_t tmpVal; + + /* Check the parameters */ + CHECK_PARAM(IS_KYS_INT_TYPE(intType)); + + /* Get certain or all interrupt status */ + tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_INT_STS); + + if (KYS_INT_ALL == intType) { + if ((tmpVal & 0x1f80) != 0) { + return SET; + } else { + return RESET; + } + } else { + if ((tmpVal & (1U << (intType + 7U))) != 0) { + return SET; + } else { + return RESET; + } + } +} + +void KYS_Get_FIFO_Idx(uint8_t *fifo_head, uint8_t *fifo_tail) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(KYS_BASE, KYS_KEYFIFO_IDX); + *fifo_head = (uint8_t)(tmpVal & 0x7); + *fifo_tail = (uint8_t)((tmpVal & 0x700) >> 8); +} + +uint8_t KYS_ReadKeyfifo(void) +{ + return ((uint8_t)(BL_RD_REG(KYS_BASE, KYS_KEYFIFO_VALUE))); +} + +/****************************************************************************/ /** + * @brief KYS get keycode value + * + * @param keycode: KYS keycode type + * @param col: Col of key + * @param row: Row of key + * + * @return Keycode value + * +*******************************************************************************/ +// uint8_t KYS_GetKeycode(KYS_Keycode_Type keycode, uint8_t *col, uint8_t *row) +// { +// uint32_t tmpVal; +// uint8_t keyValue; + +// /* Get keycode value */ +// keyValue = BL_RD_REG(KYS_BASE, KYS_KEYCODE_VALUE) >> (8 * keycode) & 0xff; + +// /* Get total row number of keyboard */ +// tmpVal = BL_RD_REG(KYS_BASE, KYS_KS_CTRL); +// tmpVal = BL_GET_REG_BITS_VAL(tmpVal, KYS_ROW_NUM); + +// /* Calculate col and row of the key */ +// *col = keyValue / (tmpVal + 1); +// *row = keyValue % (tmpVal + 1); + +// return keyValue; +// } + +/****************************************************************************/ /** + * @brief KYS interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +// extern void dv_bflb_platform_printf(); +#ifndef BFLB_USE_HAL_DRIVER +void KYS_IRQHandler(void) +{ + // dv_bflb_platform_printf("kys int sts:%lx\r\n", BL_RD_REG(KYS_BASE, KYS_KS_INT_STS)); + + if ((KYS_GetIntStatus(KYS_INT_KS_DONE) == SET) && (0x80 & BL_RD_REG(KYS_BASE, KYS_KS_INT_EN))) { + KYS_IntClear(KYS_INT_KS_DONE_CLR); + + if (KYSIntCbfArra[KYS_INT_KS_DONE] != NULL) { + KYSIntCbfArra[KYS_INT_KS_DONE](); + } + } + + if ((KYS_GetIntStatus(KYS_INT_KEYFIFO_FULL) == SET) && (0x100 & BL_RD_REG(KYS_BASE, KYS_KS_INT_EN))) { + // KYS_IntClear(KYS_INT_KEYFIFO_CLR); + + if (KYSIntCbfArra[KYS_INT_KEYFIFO_FULL] != NULL) { + KYSIntCbfArra[KYS_INT_KEYFIFO_FULL](); + } + } + + if ((KYS_GetIntStatus(KYS_INT_KEYFIFO_HALF) == SET) && (0x200 & BL_RD_REG(KYS_BASE, KYS_KS_INT_EN))) { + // KYS_IntClear(KYS_INT_KEYFIFO_CLR); + + if (KYSIntCbfArra[KYS_INT_KEYFIFO_HALF] != NULL) { + KYSIntCbfArra[KYS_INT_KEYFIFO_HALF](); + } + } + + if ((KYS_GetIntStatus(KYS_INT_KEYFIFO_QUARTER) == SET) && (0x400 & BL_RD_REG(KYS_BASE, KYS_KS_INT_EN))) { + // KYS_IntClear(KYS_INT_KEYFIFO_CLR); + + if (KYSIntCbfArra[KYS_INT_KEYFIFO_QUARTER] != NULL) { + KYSIntCbfArra[KYS_INT_KEYFIFO_QUARTER](); + } + } + + if ((KYS_GetIntStatus(KYS_INT_KEYFIFO_NONEMPTY) == SET) && (0x800 & BL_RD_REG(KYS_BASE, KYS_KS_INT_EN))) { + // KYS_IntClear(KYS_INT_KEYFIFO_CLR); + + if (KYSIntCbfArra[KYS_INT_KEYFIFO_NONEMPTY] != NULL) { + KYSIntCbfArra[KYS_INT_KEYFIFO_NONEMPTY](); + } + } + + if ((KYS_GetIntStatus(KYS_INT_GHOST_DET) == SET) && (0x1000 & BL_RD_REG(KYS_BASE, KYS_KS_INT_EN))) { + KYS_IntClear(KYS_INT_GHOST_CLR); + + if (KYSIntCbfArra[KYS_INT_GHOST_DET] != NULL) { + KYSIntCbfArra[KYS_INT_GHOST_DET](); + } + } +} + +#endif + +/*@} end of group KYS_Public_Functions */ + +/*@} end of group KYS */ + +/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_l1c.c b/drivers/soc/bl702l/std/src/bl702l_l1c.c new file mode 100644 index 000000000..964fc458b --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_l1c.c @@ -0,0 +1,646 @@ +/** + ****************************************************************************** + * @file bl702l_l1c.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_l1c.h" +#include "bl702l_common.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup L1C + * @{ + */ + +/** @defgroup L1C_Private_Macros + * @{ + */ + +/*@} end of group L1C_Private_Macros */ + +/** @defgroup L1C_Private_Types + * @{ + */ + +/*@} end of group L1C_Private_Types */ + +/** @defgroup L1C_Private_Variables + * @{ + */ +static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL }; +static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL }; + +/*@} end of group L1C_Private_Variables */ + +/** @defgroup L1C_Global_Variables + * @{ + */ + +/*@} end of group L1C_Global_Variables */ + +/** @defgroup L1C_Private_Fun_Declaration + * @{ + */ + +/*@} end of group L1C_Private_Fun_Declaration */ + +/** @defgroup L1C_Private_Functions + * @{ + */ + +/*@} end of group L1C_Private_Functions */ + +/** @defgroup L1C_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief L1C cache write set + * + * @param wtEn: L1C write through enable + * @param wbEn: L1C write back enable + * @param waEn: L1C write allocate enable + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (wtEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN); + } + + if (wbEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN); + } + + if (waEn) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN); + } + + if (wtEn && waEn) { + tmpVal = BL_SET_REG_BIT(tmpVal,L1C_FORCE_BURST_0); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal,L1C_FORCE_BURST_0); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief Cache enable set + * + * @param wayDisable: cache way disable config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable) +{ + uint32_t tmpVal; + uint32_t cnt = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + /*Set Tag RAM to zero */ + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Polling for invalid done */ + do { + BL702L_Delay_US(1); + cnt++; + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100); + + /* data flush */ + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Polling for flush done */ + do { + BL702L_Delay_US(1); + cnt++; + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100); + + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, wayDisable); + + /* If way disable is 0x0f, cacheable can't be set */ + if (wayDisable != 0x0f) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Flush cache api + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(void) +{ + uint32_t tmpVal; + + /* Disable early respone */ + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + L1C_Cache_Enable_Set((tmpVal >> L1C_WAY_DIS_POS) & 0xf); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Get cache hit count + * + * @param hitCountLow: hit count low 32 bits pointer + * @param hitCountHigh: hit count high 32 bits pointer + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +{ + *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB); + *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB); +} +#endif + +/****************************************************************************/ /** + * @brief Get cache miss count + * + * @param None + * + * @return Cache miss count + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +uint32_t ATTR_TCM_SECTION L1C_Cache_Miss_Count_Get(void) +{ + return BL_RD_REG(L1C_BASE, L1C_MISS_CNT); +} +#endif + +/****************************************************************************/ /** + * @brief Disable read from flash or psram with cache + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION L1C_Cache_Read_Disable(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief wrap set + * + * @param wrap: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap) +{ + uint32_t tmpVal = 0; + uint8_t cacheEn = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); + + if (cacheEn != 0) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (wrap == ENABLE) { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS); + } else { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (cacheEn != 0) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + } + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief cache way disable set + * + * @param disableVal: cache way disable value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + if (disableVal != 0x0f) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Set for ROM 2T access if CPU freq >120MHz + * + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + + if (enable) { + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS); + } else { + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS); + } + + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief L1C BMX init + * + * @param l1cBmxCfg: L1C BMX config + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler); + Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler); +#endif + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX address monitor enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX address monitor disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS); + BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX bus error response enable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX bus error response disable + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN); + BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Get L1C BMX error status + * + * @param errType: L1C BMX error status type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType)); + + tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN); + + if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) { + return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET; + } else { + return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET; + } +} + +/****************************************************************************/ /** + * @brief Get L1C BMX error address + * + * @param None + * + * @return NP L1C BMX error address + * +*******************************************************************************/ +uint32_t L1C_BMX_Get_Err_Addr(void) +{ + return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR); +} + +/****************************************************************************/ /** + * @brief L1C BMX error interrupt callback install + * + * @param intType: L1C BMX error interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType)); + + l1cBmxErrIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX ERR interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_ERR_IRQHandler(void) +{ + L1C_BMX_ERR_INT_Type intType; + + for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) { + if (l1cBmxErrIntCbfArra[intType] != NULL) { + l1cBmxErrIntCbfArra[intType](); + } + } + + while (1) { + //MSG("L1C_BMX_ERR_IRQHandler\r\n"); + BL702L_Delay_MS(1000); + } +} +#endif + +/****************************************************************************/ /** + * @brief L1C BMX timeout interrupt callback install + * + * @param intType: L1C BMX timeout interrupt type + * @param cbFun: callback + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun) +{ + CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType)); + + l1cBmxToIntCbfArra[intType] = cbFun; + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief L1C BMX Time Out interrupt IRQ handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void L1C_BMX_TO_IRQHandler(void) +{ + L1C_BMX_TO_INT_Type intType; + + for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) { + if (l1cBmxToIntCbfArra[intType] != NULL) { + l1cBmxToIntCbfArra[intType](); + } + } + + while (1) { + //MSG("L1C_BMX_TO_IRQHandler\r\n"); + BL702L_Delay_MS(1000); + } +} +#endif + +/*@} end of group L1C_Public_Functions */ + +/*@} end of group L1C */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_pds.c b/drivers/soc/bl702l/std/src/bl702l_pds.c new file mode 100644 index 000000000..2c8c8bf49 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_pds.c @@ -0,0 +1,1215 @@ +/** + ****************************************************************************** + * @file bl702l_pds.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l.h" +#include "bl702l_pds.h" +#include "bl702l_hbn.h" +#include "bl702l_ef_cfg.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup PDS + * @{ + */ + +/** @defgroup PDS_Private_Macros + * @{ + */ + +/*@} end of group PDS_Private_Macros */ + +/** @defgroup PDS_Private_Types + * @{ + */ + +/*@} end of group PDS_Private_Types */ + +/** @defgroup PDS_Private_Variables + * @{ + */ +#ifndef BFLB_USE_HAL_DRIVER +static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX] = { NULL }; +#endif + +/*@} end of group PDS_Private_Variables */ + +/** @defgroup PDS_Global_Variables + * @{ + */ + +/*@} end of group PDS_Global_Variables */ + +/** @defgroup PDS_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PDS_Private_Fun_Declaration */ + +/** @defgroup PDS_Private_Functions + * @{ + */ + +/*@} end of group PDS_Private_Functions */ + +/** @defgroup PDS_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief set gpio pad pull type in pds + * + * @param pin: gpio type + * @param cfg: pull up en & pull down en & ie en & oe en + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_Type pin, PDS_GPIO_Cfg_Type *cfg) +{ + uint32_t tmpVal; + + CHECK_PARAM(IS_PDS_GPIO_TYPE(pin)); + + /* pu/pd/ie config */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PU_SET); + if (cfg->pu_en) { + tmpVal |= (1 << pin); + } else { + tmpVal &= ~(1 << pin); + } + BL_WR_REG(PDS_BASE, PDS_GPIO_PU_SET, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET); + if (cfg->pd_en) { + tmpVal |= (1 << pin); + } else { + tmpVal &= ~(1 << pin); + } + BL_WR_REG(PDS_BASE, PDS_GPIO_PD_SET, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_IE_SET); + if (cfg->ie_en) { + tmpVal |= (1 << pin); + } else { + tmpVal &= ~(1 << pin); + } + BL_WR_REG(PDS_BASE, PDS_GPIO_IE_SET, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_OE_SET); + if (cfg->oe_en) { + tmpVal |= (1 << pin); + } else { + tmpVal &= ~(1 << pin); + } + BL_WR_REG(PDS_BASE, PDS_GPIO_OE_SET, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set gpio pad value in pds + * + * @param pad: gpio type + * @param val: GPIO value + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_GPIO_Write(PDS_GPIO_GROUP_SET_Type grp, uint32_t val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + + if (val > 0) { + tmpVal |= (1 << grp); + } else { + tmpVal &= ~(1 << grp); + } + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set gpio pad int mask type in pds + * + * @param pad: gpio type + * @param intMask: MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMask(PDS_GPIO_GROUP_SET_Type grp, BL_Mask_Type intMask) +{ + uint32_t tmpVal; + uint32_t tmpValMask; + + CHECK_PARAM(IS_PDS_GPIO_GROUP_SET_TYPE(grp)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpValMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_SET_INT_MASK); + if (intMask) { + tmpValMask |= (1 << grp); + } else { + tmpValMask &= ~(1 << grp); + } + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_SET_INT_MASK, tmpValMask); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set gpio pad trig type in pds + * + * @param set: set type + * @param trig: trig type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_GROUP_SET_Type grp, PDS_GPIO_INT_TRIG_Type trig) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_PDS_GPIO_GROUP_SET_TYPE(grp)); + CHECK_PARAM(IS_PDS_GPIO_INT_TRIG_TYPE(trig)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT_SET); + tmpVal &= ~(0xF << (grp << 2)); + tmpVal |= (trig << (grp << 2)); + BL_WR_REG(PDS_BASE, PDS_GPIO_INT_SET, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set gpio pad int clear in pds + * + * @param set: set type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_GROUP_SET_Type grp) +{ + uint32_t tmpVal = 0; + uint32_t offset = 0; + + CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(grp)); + + offset = grp + PDS_CR_PDS_GPIO0_SET_INT_CLR_POS; + + /* pds_gpio_setx_int_clr = 0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpVal &= ~(1 << offset); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + /* pds_gpio_setx_int_clr = 1 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpVal |= (1 << offset); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + /* pds_gpio_setx_int_clr = 0 */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpVal &= ~(1 << offset); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief set PDS gpio interrupt clear + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_All_GPIO_IntClear(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpVal &= ~(0xFF << PDS_CR_PDS_GPIO0_SET_INT_CLR_POS); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpVal |= (0xFF << PDS_CR_PDS_GPIO0_SET_INT_CLR_POS); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN); + tmpVal &= ~(0xFF << PDS_CR_PDS_GPIO0_SET_INT_CLR_POS); + BL_WR_REG(PDS_BASE, PDS_CFG_PDS_KEY_SCAN, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get gpio pad int status + * + * @param pad: gpio type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Sts_Type ATTR_TCM_SECTION PDS_Get_GPIO_Pad_IntStatus(PDS_GPIO_Type pin) +{ + CHECK_PARAM(IS_PDS_GPIO_TYPE(pin)); + + return (BL_RD_REG(PDS_BASE, PDS_GPIO_STAT) & (1 << pin)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief set flash pad pull none + * + * @param pinCfg: flash pin type + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg) +{ + PDS_GPIO_Cfg_Type pds_io_cfg = { + .pd_en = 0, + .pu_en = 0, + .ie_en = 0, + .oe_en = 0, + }; + + if (pinCfg == SF_CTRL_SEL_EXTERNAL_FLASH) { + PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_PIN_23, &pds_io_cfg); + PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_PIN_24, &pds_io_cfg); + PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_PIN_25, &pds_io_cfg); + PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_PIN_26, &pds_io_cfg); + PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_PIN_27, &pds_io_cfg); + PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_PIN_28, &pds_io_cfg); + } else { + return INVALID; + } + + return SUCCESS; +} +/****************************************************************************/ /** + * @brief set flash pad pull none + * + * @param pinCfg: flash pin type + * + * @return SUCCESS or ERROR + * + * @note ext_flash need call this function after pds mode +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg) +{ + uint32_t tmpVal; + + if (pinCfg == SF_CTRL_SEL_EXTERNAL_FLASH) { + /* pd config */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET); + /* GPIO23~28 [23]~[28] = 0 */ + tmpVal &= ~(0x1F800000); + BL_WR_REG(PDS_BASE, PDS_GPIO_PD_SET, tmpVal); + + /* pu config */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PU_SET); + /* GPIO23~28 [23]~[28] = 0 */ + tmpVal &= ~(0x1F800000); + BL_WR_REG(PDS_BASE, PDS_GPIO_PU_SET, tmpVal); + + /* ie config */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_IE_SET); + /* GPIO23~28 [23]~[28] = 0 */ + tmpVal &= ~(0x1F800000); + BL_WR_REG(PDS_BASE, PDS_GPIO_IE_SET, tmpVal); + + /* oe config */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_OE_SET); + /* GPIO23~28 [23]~[28] = 0 */ + tmpVal &= ~(0x1F800000); + BL_WR_REG(PDS_BASE, PDS_GPIO_OE_SET, tmpVal); + } else { + return INVALID; + } + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Disable PDS GPIO Keep + * + * @return SUCCESS + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Disable_GPIO_Keep(void) +{ + uint32_t tmpVal = 0; + + /* PDS_IO keep disable */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_GPIO_ISO_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_GPIO_KEEP_EN); + /* don't entry PDS */ + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_START_PS); + BL_WR_REG(PDS_BASE, PDS_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enabel PDS GPIO Keep + * + * @param keepSel: + * @return SUCCESS + * +*******************************************************************************/ +__WEAK +BL_Err_Type ATTR_TCM_SECTION PDS_Enable_PDS_Pad_Keep(uint32_t keepSel) +{ + uint32_t tmpVal = 0; + + /* PDS_IO keep disable */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_GPIO_ISO_MODE); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_SW_GPIO_ISO_MODE); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_KEEP_EN,keepSel); + /* don't entry PDS */ + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_START_PS); + BL_WR_REG(PDS_BASE, PDS_CTL, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief Enable power down sleep + * + * @param cfg: power down sleep configuration 1 + * @param cfg4: power down sleep configuration 2 + * @param pdsSleepCnt: power down sleep count cycle + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt) +{ + uint32_t tmpVal = 0; + uint32_t valLow = 0, valHigh = 0; + uint64_t val; + + /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */ + /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */ + if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) { + return ERROR; + } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) { + HBN_Get_RTC_Timer_Val(&valLow, &valHigh); + val = valLow + ((uint64_t)valHigh << 32); + val += pdsSleepCnt - PDS_WARMUP_LATENCY_CNT; + HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39); + HBN_Enable_RTC_Counter(); + } else { + /* PDS sleep time 0 ,means mask pds_timer wakeup */ + } + + /* PDS_CTL4 config */ + BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4); + + /* PDS_CTL config */ + if (cfg->pdsStart) { + /* clear pds int */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0))); + BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0))); + } else { + BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg); + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep force configure + * + * @param cfg2: power down sleep force configuration 1 + * @param cfg3: power down sleep force configuration 2 + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3) +{ + /* PDS_CTL2 config */ + BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2); + + /* PDS_CTL3 config */ + BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep ram configure + * + * @param ramCfg: power down sleep force ram configuration + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg) +{ + if (NULL == ramCfg) { + return ERROR; + } + + /* PDS_RAM1 config */ + BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep force configure + * + * @param defaultLvCfg: power down sleep default level configuration + * @param pdsSleepCnt: power down sleep time count + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt) +{ + PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3)); + PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief power down sleep wakeup event enable + * + * @param intType: PDS Wakeup Source type + * @param enable: ENABLE or DISABLE + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_Type intType, BL_Fun_Type enable) +{ + uint32_t offset = 0; + uint32_t tmpVal = 0; + + if (intType > PDS_WAKEUP_SRC_WDG_TIMEOUT) { + return ERROR; + } + + offset = intType + PDS_CR_PDS_WAKEUP_SRC_EN_POS; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + + if (enable) { + tmpVal = tmpVal | (1 << offset); + } else { + tmpVal = tmpVal & ~(1 << offset); + } + + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep Wakeup Source type + * + * @param intType: PDS int type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_Wakeup_Src(PDS_WAKEUP_SRC_Type intType) +{ + uint32_t offset = 0; + + if (intType > PDS_WAKEUP_SRC_WDG_TIMEOUT) { + return RESET; + } + + offset = intType + PDS_RO_PDS_WAKEUP_EVENT_POS; + + return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << offset)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief power down sleep int mask + * + * @param intType: PDS int type + * @param intMask: MASK or UNMASK + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask) +{ + uint32_t tmpVal = 0; + + CHECK_PARAM(IS_PDS_INT_TYPE(intType)); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + + if (intMask != UNMASK) { + tmpVal = tmpVal | (1 << (intType + PDS_CR_PDS_WAKE_INT_MASK_POS)); + } else { + tmpVal = tmpVal & ~(1 << (intType + PDS_CR_PDS_WAKE_INT_MASK_POS)); + } + + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep int status + * + * @param intType: PDS int type + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType) +{ + CHECK_PARAM(IS_PDS_INT_TYPE(intType)); + + return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET; +} + +/****************************************************************************/ /** + * @brief clear power down sleep int status + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION PDS_IntClear(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep RF status + * + * @param None + * + * @return PDS RF status + * +*******************************************************************************/ +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void) +{ + return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE); +} + +/****************************************************************************/ /** + * @brief get power down sleep status + * + * @param None + * + * @return PDS status + * +*******************************************************************************/ +PDS_STS_Type PDS_Get_PdsStstus(void) +{ + return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE); +} + +/****************************************************************************/ /** + * @brief power down sleep clear reset event + * + * @param None + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +BL_Err_Type PDS_Clear_Reset_Event(void) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get power down sleep reset event + * + * @param event: power down sleep reset event + * + * @return SET or RESET + * +*******************************************************************************/ +BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT); + + return (tmpVal & (1 << event)) ? SET : RESET; +} + +#if 0 +/****************************************************************************/ /** + * @brief PDS Auto mode wake up counter config + * + * @param sleepDuration: sleep time, total pds = sleep_duration + max_warmup_cnt (32K clock cycles), + * recommend maxWarmCnt*N+2 + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Auto_Time_Config(uint32_t sleepDuration) +{ + /* PDS_TIME1 */ + BL_WR_REG(PDS_BASE, PDS_TIME1, sleepDuration); +} +#endif +#endif +/****************************************************************************/ /** + * @brief PDS Auto mode config and enable + * + * @param powerCfg: PDS Auto mode power domain config + * @param normalCfg: PDS Auto mode power normal config + * @param enable: PDS Auto mode Enable or Disable + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable) +{ + uint32_t pdsCtl = 0; + + CHECK_PARAM(IS_PDS_LDO_VOLTAGE_TYPE(normalCfg->vddcoreVol)); + + /* power config */ + pdsCtl |= (powerCfg->mbgPower << 31) | + (powerCfg->ldo18rfPower << 30) | + (powerCfg->sfregPower << 29) | + (powerCfg->pllPower << 28) | + (powerCfg->cpu0Power << 19) | + (powerCfg->rc32mPower << 17) | + (powerCfg->xtalPower << 14) | + (powerCfg->allPower << 13) | + (powerCfg->isoPower << 11) | + (powerCfg->bzPower << 10) | + (powerCfg->sramDisStanby << 9) | + (powerCfg->cgPower << 8) | + (powerCfg->cpu1Power << 7) | + (powerCfg->usbPower << 3); + // pdsCtl = BL_SET_REG_BITS_VAL(pdsCtl, PDS_CR_PDS_LDO_VOL, normalCfg->vddcoreVol); + pdsCtl |= (normalCfg->vddcoreVolEn << 18) | + (normalCfg->cpu0NotNeedWFI << 21) | + (normalCfg->cpu1NotNeedWFI << 20) | + (normalCfg->busReset << 16) | + (normalCfg->disIrqWakeUp << 15) | + (normalCfg->powerOffXtalForever << 2) | + (normalCfg->sleepForever << 1); + BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl); + + pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL); + + if (enable) { + pdsCtl |= (1 << 0); + } else { + pdsCtl &= ~(1 << 0); + } + + BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl); +} +#endif + +/****************************************************************************/ /** + * @brief PDS force turn off XXX domain + * + * @param domain: PDS domain + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain) +{ + uint32_t tmpVal = 0; + + /* memory sleep */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_MEM_STBY_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* gate clock */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_GATE_CLK_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* pds reset */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal |= 1 << (domain + PDS_FORCE_PDS_RST_OFFSET); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* isolation on */ + // tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + // tmpVal |= 1 << (domain + PDS_FORCE_ISO_EN_OFFSET); + // BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* power off */ + // tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + // tmpVal |= 1 << (domain + PDS_FORCE_PWR_OFF_OFFSET); + // BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); +} +#endif + +/****************************************************************************/ /** + * @brief PDS force turn on XXX domain + * + * @param domain: PDS domain + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_ROM_DRIVER +__WEAK +void ATTR_TCM_SECTION PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain) +{ + uint32_t tmpVal = 0; + + /* power on */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_PWR_OFF_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* isolation off */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_ISO_EN_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* pds de_reset */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_PDS_RST_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* memory active */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_MEM_STBY_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); + + /* clock on */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2); + tmpVal &= ~(1 << (domain + PDS_FORCE_GATE_CLK_OFFSET)); + BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal); +} +#endif + +/** + * @brief + * + * @param col_size + * @param row_size + * + * @return BL_Err_Type + */ +BL_Err_Type PDS_Set_KYD_Matrix_Size(uint8_t col_size, uint8_t row_size) +{ + uint32_t tmpVal = 0; + + /* set col size */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_KYD_COL_MATRIX_SIZE, col_size); + BL_WR_REG(PDS_BASE, PDS_KYD_CTL, tmpVal); + + /* set row size */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_KYD_ROW_MATRIX_SIZE, row_size); + BL_WR_REG(PDS_BASE, PDS_KYD_CTL, tmpVal); + + return SUCCESS; +} +/** + * @brief + * + * @param val + * @return BL_Err_Type + */ +BL_Err_Type PDS_Set_KYD_Col_Value(uint8_t val) +{ + uint32_t tmpVal = 0; + + /* set col output value */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_KYD_COL_O_VAL, val); + BL_WR_REG(PDS_BASE, PDS_KYD_CTL, tmpVal); + + return SUCCESS; +} + +/** + * @brief + * + * @param en + * @return BL_Err_Type + */ +BL_Err_Type PDS_Set_KYD_Row_Pull(uint8_t en) +{ + uint32_t tmpVal = 0; + + /* disable/enable pullup or pulldown */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_KYD_ROW_I_PULL_EN, en); + BL_WR_REG(PDS_BASE, PDS_KYD_CTL, tmpVal); + + return SUCCESS; +} + +/** + * @brief + * + * @param en + * @return BL_Err_Type + */ +BL_Err_Type PDS_Set_KYD_Wakeup_En(uint8_t en) +{ + uint32_t tmpVal = 0; + + /* disable/enable cr_pds_kyd_en */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_KYD_EN, en); + BL_WR_REG(PDS_BASE, PDS_KYD_CTL, tmpVal); + + PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_KYD_WAKEUP, en); + + return SUCCESS; +} + +/** + * @brief PDS Clear KYD Wakeup Flag + * + * @return BL_Err_Type + */ +__WEAK +BL_Err_Type PDS_Clear_KYD_Wakeup(void) +{ + uint32_t tmpVal = 0; + + /* disable/enable cr_pds_kyd_en */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_PDS_KYD_WAKEUP); + BL_WR_REG(PDS_BASE, PDS_KYD_CTL, tmpVal); + + return SUCCESS; +} + +/** + * @brief set gpio x binding to keyscan row input lines + * + * @param row_x + * @param sel_io + * @return BL_Err_Type + */ +BL_Err_Type PDS_Set_KYS_ROW_IN_GPIO(PDS_KEY_ROW_Type row_x, PDS_KYS_GPIO_Type sel_io) +{ + CHECK_PARAM(IS_PDS_KYS_ROW_TYPE(row_x)); + CHECK_PARAM(IS_PDS_KYS_GPIO_TYPE(sel_io)); + + uint32_t tmp_val = 0; + /* select gpio x binding to keyscan row input lines. */ + switch (row_x) { + case PDS_KEY_ROW_0: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_0_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_ROW_1: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_1_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_ROW_2: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_2_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_ROW_3: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_3_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_ROW_4: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_4_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1, tmp_val); + break; + case PDS_KEY_ROW_5: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_5_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1, tmp_val); + break; + case PDS_KEY_ROW_6: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_6_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1, tmp_val); + break; + case PDS_KEY_ROW_7: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_ROW_I_7_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_ROW_I_GPIO_SEL1, tmp_val); + break; + + default: + break; + } + return SUCCESS; +} + +/** + * @brief select gpio x binding to keyscan col output lines + * + * @param col_x + * @param sel_io + * @return BL_Err_Type + */ +BL_Err_Type PDS_Set_KYS_COL_OUT_GPIO(PDS_KEY_COL_Type col_x, PDS_KYS_GPIO_Type sel_io) +{ + CHECK_PARAM(IS_PDS_KYS_COL_TYPE(col_x)); + CHECK_PARAM(IS_PDS_KYS_GPIO_TYPE(sel_io)); + + uint32_t tmp_val = 0; + /* select gpio x binding to keyscan col output lines. */ + + switch (col_x) { + case PDS_KEY_COL_0: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_0_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_COL_1: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_1_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_COL_2: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_2_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_COL_3: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_3_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL0, tmp_val); + break; + case PDS_KEY_COL_4: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_4_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1, tmp_val); + break; + case PDS_KEY_COL_5: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_5_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1, tmp_val); + break; + case PDS_KEY_COL_6: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_6_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1, tmp_val); + break; + case PDS_KEY_COL_7: + tmp_val = BL_RD_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1); + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CFG_KEY_COL_O_7_GPIO_SEL, sel_io); + BL_WR_REG(PDS_BASE, PDS_KYS_COL_O_GPIO_SEL1, tmp_val); + break; + + default: + break; + } + return SUCCESS; +} + +/** + * @brief PDS Get KYS Wakeup by col output and gpio x + * + * @param row_index + * @param row_gpio + * @return BL_Err_Type + */ +__WEAK +BL_Err_Type PDS_Get_KYS_Wakeup_ROW_INDEX_GPIO(PDS_KEY_ROW_Type* row_index,PDS_KYS_GPIO_Type* row_gpio) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + *row_index = BL_GET_REG_BITS_VAL(tmpVal, PDS_RO_PDS_KYD_WAKEUP_ROW_INDEX); + *row_gpio = BL_GET_REG_BITS_VAL(tmpVal, PDS_RO_PDS_KYD_WAKEUP_ROW_GPIO); + + return SUCCESS; +} + +/** + * @brief PDS Get KYS Wakeup by row input lines and gpio x + * + * @param col_index + * @param col_gpio + * @return BL_Err_Type + */ +__WEAK +BL_Err_Type PDS_Get_KYS_Wakeup_COL_INDEX_GPIO(PDS_KEY_COL_Type* col_index,PDS_KYS_GPIO_Type* col_gpio) +{ + uint32_t tmpVal = 0; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_CTL); + *col_index = BL_GET_REG_BITS_VAL(tmpVal, PDS_RO_PDS_KYD_WAKEUP_COL_INDEX); + *col_gpio = BL_GET_REG_BITS_VAL(tmpVal, PDS_RO_PDS_KYD_WAKEUP_COL_GPIO); + + return SUCCESS; +} + +/** + * @brief PDS Set KYS White_Key + * + * @param white_key_i + * @param row_index + * @param col_index + * @param type + * @return BL_Err_Type + */ +__WEAK +BL_Err_Type PDS_Set_KYS_White_Key(uint8_t white_key_i ,PDS_KEY_ROW_Type row_index,PDS_KEY_COL_Type col_index,PDS_KYD_WHITE_KEY_MODE_Type type) +{ + if( white_key_i > 3 ) { + return ERROR; + } + + uint32_t tmpVal = 0; + uint8_t bits_offset = 0; + bits_offset = 8 * white_key_i; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_KYD_WHITE_SET); + + tmpVal &= ~(0xF << bits_offset ); + tmpVal |= (row_index << bits_offset ); + tmpVal |= (col_index << (3 + bits_offset)); + tmpVal |= (type << (6 + bits_offset)); + + BL_WR_REG(PDS_BASE, PDS_KYD_WHITE_SET, tmpVal); + + return SUCCESS; +} +/****************************************************************************/ /** + * @brief Install PDS interrupt callback function + * + * @param intType: PDS int type + * @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) + * + * @return SUCCESS or ERROR + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun) +{ +#ifndef BFLB_USE_HAL_DRIVER + Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler); +#endif + pdsIntCbfArra[intType] = cbFun; + + return SUCCESS; +} +#endif + +/****************************************************************************/ /** + * @brief Power down sleep wake up interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +#ifndef BFLB_USE_HAL_DRIVER +void PDS_WAKEUP_IRQHandler(void) +{ + for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) { + if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType] != NULL)) { + pdsIntCbfArra[intType](); + } + } + + PDS_IntClear(); +} +#endif + +/*@} end of group PDS_Public_Functions */ + +/*@} end of group PDS */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/src/bl702l_pm.c b/drivers/soc/bl702l/std/src/bl702l_pm.c new file mode 100644 index 000000000..b8acee3b8 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_pm.c @@ -0,0 +1,511 @@ +#include "bl702l_pm.h" +#include "bl702l_glb.h" +#include "bl702l_pds.h" +#include "bl702l_hbn.h" +#include "bl702l_clock.h" +#include "bflb_acomp.h" +#include "bflb_flash.h" + +#ifndef PM_PDS_FLASH_POWER_OFF +#define PM_PDS_FLASH_POWER_OFF 1 +#endif + +#ifndef PM_PDS_DLL_POWER_OFF +#define PM_PDS_DLL_POWER_OFF 1 +#endif + +#ifndef PM_PDS_PLL_POWER_OFF +#define PM_PDS_PLL_POWER_OFF 1 +#endif + +#ifndef PM_PDS_RF_POWER_OFF +#define PM_PDS_RF_POWER_OFF 1 +#endif + +#ifndef PM_PDS_LDO_LEVEL_DEFAULT +#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V +#endif + +#ifndef PM_PDS_IO_KEEP_VAL +#define PM_PDS_IO_KEEP_VAL 0 +#endif + +#ifndef PM_HBN_LDO_LEVEL_DEFAULT +#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V +#endif + +#ifndef PM_OCRAM_RET_VAL +#define PM_OCRAM_RET_VAL 0x1C1F1F +#endif + + +static PDS_DEFAULT_LV_CFG_Type pdsCfgLevel31 = { + .pdsCtl = { + .pdsStart = 1, + .sleepForever = 0, + .xtalForceOff = 0, + .waitRC32mRdy = 0, + .avdd14Off = 1, + .bgSysOff = 1, + .glbRstProtect = 0, + .puFlash = 0, + .clkOff = 1, + .memStby = 1, + .swPuFlash = 1, + .isolation = 1, + .waitXtalRdy = 0, + .pdsPwrOff = 1, + .xtalOff = 1, + .socEnbForceOn = 1, + .pdsRstSocEn = 1, + .pdsRC32mOn = 0, + .pdsLdoVselEn = 1, + .xtalCntRC32kEn = 0, + .cpu0WfiMask = 0, + .ldo11Off = 1, + .pdsCtlRfSel = 1, + .xtalDegEn = 0, + .bleWakeupReqEn = 0, + .swGpioIsoMod = 0, + .pdsClkOff = 0, + .pdsGpioKeep = 0, + .pdsGpioIsoMod = 0, + }, + .pdsCtl2 = { + .forceCpuPdsRst = 0, + .forceBzPdsRst = 0, + .forceCpuGateClk = 0, + .forceBzGateClk = 0, + }, + .pdsCtl3 = { + .forceMiscPwrOff = 0, + .forceMiscPdsRst = 0, + .forceMiscGateClk = 0, + .MiscIsoEn = 1, + }, + .pdsCtl4 = { + .cpuRst = 1, + .cpuGateClk = 1, + .BzRst = 1, + .BzGateClk = 1, + .MiscPwrOff = 1, + .MiscRst = 1, + .MiscGateClk = 1, + } +}; + +/****************************************************************************/ /** +* @brief pm power on flash +* +* @param cfg: PDS app config +* +* @return None +* +*******************************************************************************/ +void ATTR_TCM_SECTION pm_power_on_flash(uint32_t *cfg, uint8_t cont) +{ + /* Init flash gpio */ + bflb_sf_cfg_init_flash_gpio(0, 1); + + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + + /* Restore flash */ + bflb_sflash_restore_from_powerdown((spi_flash_cfg_type *)cfg, cont, 0); +} + +/****************************************************************************/ /** + * @brief pm power on flash pad gpio + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION pm_power_on_flash_pad(void) +{ + /* Turn on Flash pad, GPIO23 - GPIO28 */ + bflb_sf_cfg_init_internal_flash_gpio(); +} + +/****************************************************************************/ /** + * @brief pm update flash_ctrl setting + * + * @param fastClock: fast clock + * + * @return None + * +*******************************************************************************/ +static ATTR_TCM_SECTION void PDS_Update_Flash_Ctrl_Setting(uint8_t fastClock) +{ + if (fastClock) { + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_64M, 0); + } else { + GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_XCLK, 0); + } + + bflb_sf_ctrl_set_clock_delay(fastClock); +} + +/****************************************************************************/ /** + * @brief pm pds wakeup src enable + * + * @param WakeupType + * + * @return BL_Err_Type + * +*******************************************************************************/ +BL_Err_Type pm_pds_wakeup_src_en(uint32_t WakeupType) +{ + return PDS_Wakeup_Src_En((PDS_WAKEUP_SRC_Type)WakeupType,ENABLE); +} + +/****************************************************************************/ /** + * @brief pm pds get wakeup src + * + * @param WakeupType + * + * @return BL_Sts_Type + * +*******************************************************************************/ +BL_Sts_Type pm_pds_get_wakeup_src(uint32_t WakeupType) +{ + return PDS_Get_Wakeup_Src(WakeupType); +} + +/****************************************************************************/ /** + * @brief pm pds mask all wakeup src + * + * @param none + * + * @return None + * +*******************************************************************************/ +void pm_pds_mask_all_wakeup_src(void) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_WAKEUP_SRC_EN); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_RF_DONE_INT_MASK); + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); +} + +/****************************************************************************/ /** + * @brief pm pds enable + * + * @param cfg: + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION pm_pds_enable(uint32_t *cfg) +{ + uint32_t tmpVal = 0; + PM_PDS_CFG_Type *p = (PM_PDS_CFG_Type *)cfg; + PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; + uintptr_t irq_flag; + + HBN_32K_Sel(HBN_32K_RC); + HBN_Set_Ldo11_All_Vout(p->ldoLevel); + + /* To make it simple and safe*/ + irq_flag = bflb_irq_save(); + + // PDS_WAKEUP_IRQHandler_Install(); + /* CLear HBN RTC INT Status */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); + tmpVal &= ~0xE; + BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); + BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal &= ~(1 << 8); //unmask pds wakeup + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + if (p->sleepTime) { + /* enable hbn(rtc\acomp\aonio) wakeup for pds */ + PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_HBN_IRQ_OUT,ENABLE); + } + + PDS_Set_All_GPIO_IntClear(); + PDS_IntClear(); + + /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI) */ + CPU_Interrupt_Enable(PDS_WAKEUP_IRQn); + + switch (p->pdsLevel) { + case PM_PDS_LEVEL_31: + pPdsCfg = &pdsCfgLevel31; + break; + default: + return; + } + + if (p->powerDownFlash) { + HBN_Power_Down_Flash((spi_flash_cfg_type *)p->flashCfg); + /* turn_off_ext_flash_pin, GPIO23 - GPIO28 */ + // for (uint32_t pin = 23; pin <= 28; pin++) { + // GLB_GPIO_Set_HZ(pin); + // } + + /* SF io select from efuse value */ +#if 0 //TODO + SF_Ctrl_Pin_Select sf_pin_select = 0; + /* get sw uasge 0 */ + EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&tmpVal); + /* get flash type */ + sf_pin_select = (tmpVal >> 14) & 0x3f; +#endif + } + + if (p->turnoffDLL) { + GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); + AON_Power_Off_XTAL(); + GLB_Power_Off_DLL(); + PDS_Update_Flash_Ctrl_Setting(0); + } + + if (p->pdsLdoEn) { + pPdsCfg->pdsCtl.pdsLdoVselEn = 1; + /* PDS mode LDO level, if cr_pds_ldo_vsel_en =1 */ + HBN_Set_Ldo11_Aon_Vout(p->ldoLevel); + } + + if (p->ocramRetetion) { + uint32_t pds_ram = PM_OCRAM_RET_VAL; + PDS_RAM_CFG_Type *ramCfg = (PDS_RAM_CFG_Type *)&pds_ram; + PDS_RAM_Config(ramCfg); + } + + if (!(p->turnOffRF)) { + pPdsCfg->pdsCtl.pdsCtlRfSel = 0; + } + + if( p->ioKeepSel ) { + pPdsCfg->pdsCtl.swGpioIsoMod = 1; + pPdsCfg->pdsCtl.pdsGpioKeep = p->ioKeepSel; + pPdsCfg->pdsCtl.pdsGpioIsoMod = 1; + } + + + /* config ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup ldo11soc_rdy_aon */ + AON_Set_LDO11_SOC_Sstart_Delay(0x2); + + PDS_Default_Level_Config(pPdsCfg, p->sleepTime); + + __WFI(); /* if(.wfiMask==0){CPU won't power down until PDS module had seen __wfi} */ + + bflb_irq_restore(irq_flag); + + if (p->turnoffDLL) { + HBN_Set_XCLK_CLK_Sel(1); + GLB_Set_System_CLK(GLB_DLL_XTAL_32M, GLB_SYS_CLK_DLL128M); + PDS_Update_Flash_Ctrl_Setting(1); + } + + if (p->powerDownFlash) { + pm_power_on_flash(p->flashCfg, p->flashContRead); + } +} + +void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time) +{ + PM_PDS_CFG_Type cfg = { + .pdsLevel = pds_level, /*!< PDS level */ + .turnOffRF = PM_PDS_RF_POWER_OFF, /*!< Wheather turn off RF */ + .powerDownFlash = PM_PDS_FLASH_POWER_OFF, /*!< Whether power down flash */ + .ocramRetetion = 1, /*!< Whether OCRAM Retention */ + .turnoffDLL = PM_PDS_DLL_POWER_OFF, /*!< Whether trun off PLL */ + .pdsLdoEn = 1, /*!< Whether enable PDS control LDO */ + .flashContRead = 0, /*!< Whether enable flash continue read */ + .ioKeepSel = PM_PDS_IO_KEEP_VAL, /*!< PDS io keep select */ + .sleepTime = sleep_time, /*!< PDS sleep time */ + .flashCfg = NULL, /*!< Flash config pointer, used when power down flash */ + .ldoLevel = PM_PDS_LDO_LEVEL_DEFAULT, /*!< LDO level */ + .preCbFun = NULL, /*!< Pre callback function */ + .postCbFun = NULL, /*!< Post callback function */ + }; + + uint32_t flash_cfg_len; + bflb_flash_get_cfg((uint8_t **)&cfg.flashCfg, &flash_cfg_len); + + pm_pds_enable((uint32_t *)&cfg); +} + +void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint32_t sleep_time) +{ + HBN_APP_CFG_Type cfg = { + .useXtal32k = 0, /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */ + .sleepTime = sleep_time, /*!< HBN sleep time */ + .hw_pu_pd_en = 1, /*!< Always disable HBN pin pull up/down to reduce PDS/HBN current */ + .flashCfg = NULL, /*!< Flash config pointer, used when power down flash */ + .hbnLevel = hbn_level, /*!< HBN level */ + .ldoLevel = PM_HBN_LDO_LEVEL_DEFAULT, /*!< LDO level */ + }; + + uint32_t flash_cfg_len; + bflb_flash_get_cfg((uint8_t **)&cfg.flashCfg, &flash_cfg_len); + + HBN_Mode_Enter(&cfg); +} + +void pm_pds_io_wakeup_en(uint32_t pin,int trigMode, int pu, int pd) +{ + PDS_GPIO_Cfg_Type cfg={ + .pu_en = pu, + .pd_en = pd, + .ie_en = 1, + .oe_en = 0, + }; + + uint32_t tmpVal; + + PDS_GPIO_GROUP_SET_Type grp = (PDS_GPIO_GROUP_SET_Type)(pin/4); + + PDS_Set_GPIO_Pad_IntMask(grp,MASK); + + /* ENABL all pin's ie of GROUP */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_IE_SET); + tmpVal |= ((uint32_t)0xF << grp); + BL_WR_REG(PDS_BASE, PDS_GPIO_IE_SET, tmpVal); + + PDS_Set_GPIO_Pad_Cfg((PDS_GPIO_Type)pin,&cfg); + + PDS_Set_GPIO_Pad_IntMode(grp,(PDS_GPIO_INT_TRIG_Type)trigMode); + PDS_Set_GPIO_Pad_IntClr(grp); + + PDS_Set_GPIO_Pad_IntMask(grp,UNMASK); + + PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_PDS_IO_INT,ENABLE); +} + +void pm_hbn_io_wakeup_en(uint32_t pin,int trigMode, int pu, int pd) +{ + uint32_t mask = 0; + uint32_t mask_bit = 0; + + HBN_AON_PAD_CFG_Type aonPadCfg={ + .ctrlEn = 1, + .ie = 1, + .pullUp = pu, + .pullDown = pd, + .oe = 0, + }; + + if( (pin>=9) && (pin<=13) ) { /* AONIO 9~13*/ + HBN_Aon_Pad_Cfg(1,(HBN_AON_PAD_Type)(pin-9),&aonPadCfg); + mask_bit = pin - 9; + } else if( (pin>=30) && (pin<=31) ) { /* AONIO 30~31*/ + HBN_Aon_Pad_Cfg(1,(HBN_AON_PAD_Type)(pin-25),&aonPadCfg); + mask_bit = pin - 25; + } else { + } + + mask = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + mask = BL_GET_REG_BITS_VAL(mask,HBN_PIN_WAKEUP_MASK); + mask = mask & ~(1 << mask_bit); + + /* set trigMode */ + HBN_GPIO_Wakeup_Set((~mask),(HBN_GPIO_INT_Trigger_Type)trigMode); + + /* UnMask Hbn_Irq Wakeup PDS*/ + PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_HBN_IRQ_OUT,ENABLE); + +} + +BL_Err_Type pm_set_io_keep(uint32_t pin,uint32_t value) +{ + if( (pin>=4) && (pin<=6) ) { /* 702l don't have gpio4~6 */ + return ERROR; + } + + PDS_GPIO_Cfg_Type pdsPadcfg={ + .pu_en = 0, + .pd_en = 0, + .ie_en = 1, + .oe_en = 0, + }; + + HBN_AON_PAD_CFG_Type aonPadCfg={ + .ctrlEn = 1, + .ie = 1, + .pullUp = 0, + .pullDown = 0, + .oe = 0, + }; + + if( value ) { + pdsPadcfg.pu_en = 1; + aonPadCfg.pullUp = 1; + } else { + pdsPadcfg.pd_en = 1; + aonPadCfg.pullDown = 1; + } + + if( (pin>=9) && (pin<=13) ) { /* AONIO 9~13*/ + HBN_Aon_Pad_Cfg(1,(HBN_AON_PAD_Type)(pin-9),&aonPadCfg); + } else if( (pin>=30) && (pin<=31) ) { /* AONIO 30~31*/ + HBN_Aon_Pad_Cfg(1,(HBN_AON_PAD_Type)(pin-25),&aonPadCfg); + } else { /* PDSIO */ + PDS_Set_GPIO_Pad_Cfg((PDS_GPIO_Type)pin,&pdsPadcfg); + + } + + return SUCCESS; +} + +uint32_t pm_acomp_wakeup_en(uint8_t acompNo, uint8_t pin, uint8_t pos_edge_en, uint8_t neg_edge_en) +{ + uint32_t chId=0; + struct bflb_acomp_config_s acompCfg = { + .mux_en = ENABLE, + .pos_chan_sel = AON_ACOMP_CHAN_ADC0, + .neg_chan_sel = AON_ACOMP_CHAN_VIO_X_SCALING_FACTOR_1, + .vio_sel = 33, //1.65v + .scaling_factor = AON_ACOMP_SCALING_FACTOR_1, + .bias_prog = AON_ACOMP_BIAS_POWER_MODE1, + .hysteresis_pos_volt = AON_ACOMP_HYSTERESIS_VOLT_NONE, + .hysteresis_neg_volt = AON_ACOMP_HYSTERESIS_VOLT_NONE, + }; + + if( SUCCESS != bflb_acomp_gpio_2_chanid((uint32_t)pin,&chId) ) { + return -1; + } else { + acompCfg.pos_chan_sel = chId; + } + + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + /* Config Gpio as Analog */ + bflb_gpio_init(gpio, pin, GPIO_ANALOG | GPIO_PULL_NONE | GPIO_DRV_0); + + /* Config Comp0/1 */ + bflb_acomp_init(acompNo, &acompCfg); + bflb_acomp_enable(acompNo); + + HBN_Clear_IRQ(HBN_INT_ACOMP0 + acompNo * 2); + + /* enable/disable POSEDGE */ + if (pos_edge_en) { + HBN_Enable_AComp_IRQ(acompNo, HBN_ACOMP_INT_EDGE_POSEDGE); + } else { + HBN_Disable_AComp_IRQ(acompNo, HBN_ACOMP_INT_EDGE_POSEDGE); + } + + /* enable/disable NEGEDGE */ + if (neg_edge_en) { + HBN_Enable_AComp_IRQ(acompNo, HBN_ACOMP_INT_EDGE_NEGEDGE); + } else { + HBN_Disable_AComp_IRQ(acompNo, HBN_ACOMP_INT_EDGE_NEGEDGE); + } + + /* UnMask Hbn_Irq Wakeup PDS*/ + PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_HBN_IRQ_OUT,ENABLE); + + return 0; +} \ No newline at end of file diff --git a/drivers/soc/bl702l/std/src/bl702l_romapi.c b/drivers/soc/bl702l/std/src/bl702l_romapi.c new file mode 100644 index 000000000..0708e58cb --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_romapi.c @@ -0,0 +1,2342 @@ +#include "bl702l_romdriver.h" + + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_On_MBG(void){ + return RomDriver_AON_Power_On_MBG(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_Off_MBG(void){ + return RomDriver_AON_Power_Off_MBG(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_On_XTAL(void){ + return RomDriver_AON_Power_On_XTAL(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut){ + return RomDriver_AON_Set_Xtal_CapCode(capIn,capOut); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t AON_Get_Xtal_CapCode(void){ + return RomDriver_AON_Get_Xtal_CapCode(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Set_Xtal_CapCode_Extra(uint8_t extra){ + return RomDriver_AON_Set_Xtal_CapCode_Extra(extra); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_Off_XTAL(void){ + return RomDriver_AON_Power_Off_XTAL(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_On_BG(void){ + return RomDriver_AON_Power_On_BG(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_Off_BG(void){ + return RomDriver_AON_Power_Off_BG(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_On_LDO11_SOC(void){ + return RomDriver_AON_Power_On_LDO11_SOC(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_Off_LDO11_SOC(void){ + return RomDriver_AON_Power_Off_LDO11_SOC(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_On_SFReg(void){ + return RomDriver_AON_Power_On_SFReg(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Power_Off_SFReg(void){ + return RomDriver_AON_Power_Off_SFReg(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay){ + return RomDriver_AON_Set_LDO11_SOC_Sstart_Delay(delay); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Set_DCDC14_Top_0(uint8_t voutSel, uint8_t vpfm){ + return RomDriver_AON_Set_DCDC14_Top_0(voutSel,vpfm); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Trim_Ldo11socVoutTrim(void){ + return RomDriver_AON_Trim_Ldo11socVoutTrim(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Trim_Ldo14VoutTrim(void){ + return RomDriver_AON_Trim_Ldo14VoutTrim(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type AON_Trim_Dcdc14VoutTrim(void){ + return RomDriver_AON_Trim_Dcdc14VoutTrim(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type){ + return RomDriver_Clock_System_Clock_Get(type); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type){ + return RomDriver_Clock_Peripheral_Clock_Get(type); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t SystemCoreClockGet(void){ + return RomDriver_SystemCoreClockGet(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t CPU_Get_MTimer_Clock(void){ + return RomDriver_CPU_Get_MTimer_Clock(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint64_t CPU_Get_MTimer_Counter(void){ + return RomDriver_CPU_Get_MTimer_Counter(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint64_t CPU_Get_CPU_Cycle(void){ + return RomDriver_CPU_Get_CPU_Cycle(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint64_t CPU_Get_MTimer_US(void){ + return RomDriver_CPU_Get_MTimer_US(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint64_t CPU_Get_MTimer_MS(void){ + return RomDriver_CPU_Get_MTimer_MS(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type CPU_MTimer_Delay_US(uint32_t cnt){ + return RomDriver_CPU_MTimer_Delay_US(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type CPU_MTimer_Delay_MS(uint32_t cnt){ + return RomDriver_CPU_MTimer_Delay_MS(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void BL702L_Delay_US(uint32_t cnt){ + return RomDriver_BL702L_Delay_US(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void BL702L_Delay_MS(uint32_t cnt){ + return RomDriver_BL702L_Delay_MS(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len){ + return RomDriver_EF_Ctrl_Get_Trim_Parity(val,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Common_Trim(char *name, Efuse_Common_Trim_Type *trim){ + return RomDriver_EF_Ctrl_Read_Common_Trim(name,trim); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_Common_Trim(char *name, uint8_t trim_en, uint32_t trim_value){ + return RomDriver_EF_Ctrl_Write_Common_Trim(name,trim_en,trim_value); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload){ + return RomDriver_EF_Ctrl_Is_MAC_Address_Slot_Empty(slot,reload); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program){ + return RomDriver_EF_Ctrl_Write_MAC_Address_Opt(slot,mac,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload){ + return RomDriver_EF_Ctrl_Read_MAC_Address_Opt(slot,mac,reload); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Sw_AHB_Clk_0(void){ + return RomDriver_EF_Ctrl_Sw_AHB_Clk_0(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Program_Efuse_0(void){ + return RomDriver_EF_Ctrl_Program_Efuse_0(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Load_Efuse_R0(void){ + return RomDriver_EF_Ctrl_Load_Efuse_R0(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type EF_Ctrl_Busy(void){ + return RomDriver_EF_Ctrl_Busy(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type EF_Ctrl_AutoLoad_Done(void){ + return RomDriver_EF_Ctrl_AutoLoad_Done(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program){ + return RomDriver_EF_Ctrl_Write_Dbg_Pwd(passWdLow,passWdHigh,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh){ + return RomDriver_EF_Ctrl_Read_Dbg_Pwd(passWdLow,passWdHigh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program){ + return RomDriver_EF_Ctrl_Readlock_Dbg_Pwd(program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program){ + return RomDriver_EF_Ctrl_Writelock_Dbg_Pwd(program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program){ + return RomDriver_EF_Ctrl_Write_Secure_Cfg(cfg,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg){ + return RomDriver_EF_Ctrl_Read_Secure_Cfg(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_Secure_Boot(uint8_t sign[1], uint8_t aes[1], uint8_t program){ + return RomDriver_EF_Ctrl_Write_Secure_Boot(sign,aes,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Secure_Boot(uint8_t sign[1], uint8_t aes[1]){ + return RomDriver_EF_Ctrl_Read_Secure_Boot(sign,aes); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program){ + return RomDriver_EF_Ctrl_Write_Sw_Usage(index,usage,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage){ + return RomDriver_EF_Ctrl_Read_Sw_Usage(index,usage); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program){ + return RomDriver_EF_Ctrl_Writelock_Sw_Usage(index,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_MAC_Address(uint8_t mac[8], uint8_t program){ + return RomDriver_EF_Ctrl_Write_MAC_Address(mac,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val){ + return RomDriver_EF_Ctrl_Get_Byte_Zero_Cnt(val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len){ + return RomDriver_EF_Ctrl_Is_All_Bits_Zero(val,start,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]){ + return RomDriver_EF_Ctrl_Read_MAC_Address(mac); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Writelock_MAC_Address(uint8_t program){ + return RomDriver_EF_Ctrl_Writelock_MAC_Address(program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]){ + return RomDriver_EF_Ctrl_Read_Chip_ID(chipID); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo){ + return RomDriver_EF_Ctrl_Read_Device_Info(deviceInfo); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload){ + return RomDriver_EF_Ctrl_Is_CapCode_Empty(slot,reload); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program){ + return RomDriver_EF_Ctrl_Write_CapCode_Opt(slot,code,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload){ + return RomDriver_EF_Ctrl_Read_CapCode_Opt(slot,code,reload); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload){ + return RomDriver_EF_Ctrl_Is_PowerOffset_Slot_Empty(slot,reload); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program){ + return RomDriver_EF_Ctrl_Write_PowerOffset_Opt(slot,pwrOffset,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload){ + return RomDriver_EF_Ctrl_Read_PowerOffset_Opt(slot,pwrOffset,reload); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program){ + return RomDriver_EF_Ctrl_Write_AES_Key(index,keyData,len,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len){ + return RomDriver_EF_Ctrl_Read_AES_Key(index,keyData,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program){ + return RomDriver_EF_Ctrl_Writelock_AES_Key(index,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program){ + return RomDriver_EF_Ctrl_Readlock_AES_Key(index,program); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){ + return RomDriver_EF_Ctrl_Program_Direct_R0(index,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){ + return RomDriver_EF_Ctrl_Read_Direct_R0(index,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Clear(uint32_t index, uint32_t len){ + return RomDriver_EF_Ctrl_Clear(index,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Crc_Enable(void){ + return RomDriver_EF_Ctrl_Crc_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void){ + return RomDriver_EF_Ctrl_Crc_Is_Busy(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue){ + return RomDriver_EF_Ctrl_Crc_Set_Golden(goldenValue); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type EF_Ctrl_Crc_Result(void){ + return RomDriver_EF_Ctrl_Crc_Result(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void){ + return RomDriver_GLB_Get_Root_CLK_Sel(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv){ + return RomDriver_GLB_Set_System_CLK_Div(hclkDiv,bclkDiv); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t GLB_Get_BCLK_Div(void){ + return RomDriver_GLB_Get_BCLK_Div(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t GLB_Get_HCLK_Div(void){ + return RomDriver_GLB_Get_HCLK_Div(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq){ + return RomDriver_GLB_Set_System_CLK(xtalType,clkFreq); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type System_Core_Clock_Update_From_RC32M(void){ + return RomDriver_System_Core_Clock_Update_From_RC32M(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable){ + return RomDriver_GLB_Set_MAC154_ZIGBEE_CLK(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable){ + return RomDriver_GLB_Set_BLE_CLK(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_AUDIO_CLK(uint8_t clkDivEn, uint8_t autoDivEn, GLB_AUDIO_CLK_SRC_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_AUDIO_CLK(clkDivEn,autoDivEn,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_KYS_CLK(GLB_KYS_CLK_SRC_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_KYS_CLK(clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk){ + return RomDriver_GLB_Set_DMA_CLK(enable,clk); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_IR_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_SF_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_UART_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Sel_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_Sel_TMR_GPIO_Clock(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_0_Type clkSel){ + return RomDriver_GLB_Set_Chip_Out_0_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_1_Type clkSel){ + return RomDriver_GLB_Set_Chip_Out_1_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Chip_Out_0_CLK_Enable(uint8_t enable){ + return RomDriver_GLB_Set_Chip_Out_0_CLK_Enable(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Chip_Out_1_CLK_Enable(uint8_t enable){ + return RomDriver_GLB_Set_Chip_Out_1_CLK_Enable(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_SRC_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_I2C_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_SRC_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_SPI_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_SRC_Type clkSel){ + return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_SW_System_Reset(void){ + return RomDriver_GLB_SW_System_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_SW_CPU_Reset(void){ + return RomDriver_GLB_SW_CPU_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_SW_POR_Reset(void){ + return RomDriver_GLB_SW_POR_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst){ + return RomDriver_GLB_AHB_MCU_Software_Reset(swrst); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Disrst_Set(uint8_t enable, GLB_DISRST_Type disrst){ + return RomDriver_GLB_Disrst_Set(enable,disrst); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_MAC154_ZIGBEE_Reset(void){ + return RomDriver_GLB_MAC154_ZIGBEE_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BLE_Reset(void){ + return RomDriver_GLB_BLE_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips){ + return RomDriver_GLB_PER_Clock_Gate(ips); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips){ + return RomDriver_GLB_PER_Clock_UnGate(ips); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_RTC_Mode(RTC_MODE_Type rtcMode){ + return RomDriver_GLB_Set_RTC_Mode(rtcMode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg){ + return RomDriver_GLB_BMX_Init(BmxCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void){ + return RomDriver_GLB_BMX_Addr_Monitor_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void){ + return RomDriver_GLB_BMX_Addr_Monitor_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BMX_BusErrResponse_Enable(void){ + return RomDriver_GLB_BMX_BusErrResponse_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BMX_BusErrResponse_Disable(void){ + return RomDriver_GLB_BMX_BusErrResponse_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType){ + return RomDriver_GLB_BMX_Get_Status(errType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t GLB_BMX_Get_Err_Addr(void){ + return RomDriver_GLB_BMX_Get_Err_Addr(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_BMX_BusErrClr_Set(uint8_t enable){ + return RomDriver_GLB_BMX_BusErrClr_Set(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value){ + return RomDriver_GLB_Set_SRAM_PARM(value); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t GLB_Get_SRAM_PARM(void){ + return RomDriver_GLB_Get_SRAM_PARM(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_OCRAM_PARM(uint32_t value){ + return RomDriver_GLB_Set_OCRAM_PARM(value); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t GLB_Get_OCRAM_PARM(void){ + return RomDriver_GLB_Get_OCRAM_PARM(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType){ + return RomDriver_GLB_Set_EM_Sel(emType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable){ + return RomDriver_GLB_Set_Kys_Drv_Col(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_O_Latch_Mode_Set(uint8_t enable){ + return RomDriver_GLB_GPIO_O_Latch_Mode_Set(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel){ + return RomDriver_GLB_JTAG_Sig_Swap_Set(swapSel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable){ + return RomDriver_GLB_CCI_Use_IO_0_1_2_7(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable){ + return RomDriver_GLB_CCI_Use_Jtag_Pin(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState){ + return RomDriver_GLB_Swap_SPI_0_MOSI_With_MISO(newState); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod){ + return RomDriver_GLB_Set_SPI_0_ACT_MOD_Sel(mod); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Flash_Scenario(uint8_t enable){ + return RomDriver_GLB_Set_Flash_Scenario(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Embedded_FLash_IO_PARM(uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs){ + return RomDriver_GLB_Set_Embedded_FLash_IO_PARM(reverse,swapIo3Io0,swapIo2Cs); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_MTimer_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_SRC_Type clkSel, uint8_t div){ + return RomDriver_GLB_Set_ADC_CLK(enable,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, GLB_DIG_CLK_SRC_Type clkSel, uint16_t div){ + return RomDriver_GLB_Set_DIG_32K_CLK(enable,compensation,clkSel,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_SW_BLE_WAKEUP_REQ_Set(uint8_t enable){ + return RomDriver_GLB_SW_BLE_WAKEUP_REQ_Set(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun){ + return RomDriver_GLB_UART_Fun_Sel(sig,fun); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Power_Off_DLL(void){ + return RomDriver_GLB_Power_Off_DLL(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType){ + return RomDriver_GLB_Power_On_DLL(xtalType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Enable_DLL_All_Clks(void){ + return RomDriver_GLB_Enable_DLL_All_Clks(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk){ + return RomDriver_GLB_Enable_DLL_Clk(dllClk); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Disable_DLL_All_Clks(void){ + return RomDriver_GLB_Disable_DLL_All_Clks(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk){ + return RomDriver_GLB_Disable_DLL_Clk(dllClk); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue){ + return RomDriver_GLB_Set_Flash_Id_Value(idValue); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t GLB_Get_Flash_Id_Value(void){ + return RomDriver_GLB_Get_Flash_Id_Value(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Trim_RC32M(void){ + return RomDriver_GLB_Trim_RC32M(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Set_Xtal_Cnt32k_Process(void){ + return RomDriver_GLB_Set_Xtal_Cnt32k_Process(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Clear_Xtal_Cnt32k_Done(void){ + return RomDriver_GLB_Clear_Xtal_Cnt32k_Done(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_RC32K_Deg_Start(void){ + return RomDriver_GLB_RC32K_Deg_Start(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_RC32K_Deg_End(void){ + return RomDriver_GLB_RC32K_Deg_End(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_RC32K_Deg_Enable(uint8_t enable){ + return RomDriver_GLB_RC32K_Deg_Enable(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Xtal_Deg_Cnt_Limit_Set(uint8_t cnt){ + return RomDriver_GLB_Xtal_Deg_Cnt_Limit_Set(cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_IR_LED_Driver_Enable(void){ + return RomDriver_GLB_IR_LED_Driver_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_IR_LED_Driver_Disable(void){ + return RomDriver_GLB_IR_LED_Driver_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_IR_LED_Type led){ + return RomDriver_GLB_IR_LED_Driver_Output_Enable(led); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_IR_LED_Type led){ + return RomDriver_GLB_IR_LED_Driver_Output_Disable(led); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias){ + return RomDriver_GLB_IR_LED_Driver_Ibias(ibias); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg){ + return RomDriver_GLB_GPIO_Init(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt){ + return RomDriver_GLB_GPIO_Func_Init(gpioFun,pinList,cnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_OUTPUT_Mode_Set(GLB_GPIO_Type gpioPin, GLB_GPIO_OUTPUT_MODE_Type mode){ + return RomDriver_GLB_GPIO_OUTPUT_Mode_Set(gpioPin,mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_INPUT_Enable(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_INPUT_Disable(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Set_HZ(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Get_Fun(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val){ + return RomDriver_GLB_GPIO_Write(gpioPin,val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Read(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Set(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_GPIO_Clr(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask){ + return RomDriver_GLB_GPIO_IntMask(gpioPin,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_Clr_GPIO_IntStatus(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin){ + return RomDriver_GLB_Get_GPIO_IntStatus(gpioPin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg){ + return RomDriver_GLB_GPIO_Int_Init(intCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg){ + return RomDriver_HBN_Mode_Enter(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void HBN_GPIO_Wakeup_Set(uint16_t gpio_wakeup_src, HBN_GPIO_INT_Trigger_Type gpio_trig_type){ + return RomDriver_HBN_GPIO_Wakeup_Set(gpio_wakeup_src,gpio_trig_type); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void HBN_Power_Down_Flash(spi_flash_cfg_type *flash_cfg){ + return RomDriver_HBN_Power_Down_Flash(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void HBN_Enable(HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel){ + return RomDriver_HBN_Enable(ldoLevel,hbnLevel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Reset(void){ + return RomDriver_HBN_Reset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv){ + return RomDriver_HBN_App_Reset(npXtalType,bclkDiv,apXtalType,fclkDiv); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Disable(void){ + return RomDriver_HBN_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type HBN_Get_BOR_OUT_State(void){ + return RomDriver_HBN_Get_BOR_OUT_State(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode){ + return RomDriver_HBN_Set_BOR_Config(enable,threshold,mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel){ + return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel){ + return RomDriver_HBN_Set_Ldo11_Soc_Vout(ldoLevel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel){ + return RomDriver_HBN_Set_Ldo11_All_Vout(ldoLevel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType){ + return RomDriver_HBN_32K_Sel(clkType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel){ + return RomDriver_HBN_Set_UART_CLK_Sel(clkSel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk){ + return RomDriver_HBN_Set_XCLK_CLK_Sel(xClk); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk){ + return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_HRAM_slp(void){ + return RomDriver_HBN_Set_HRAM_slp(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_HRAM_Ret(void){ + return RomDriver_HBN_Set_HRAM_Ret(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Power_On_Xtal_32K(void){ + return RomDriver_HBN_Power_On_Xtal_32K(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Power_Off_Xtal_32K(void){ + return RomDriver_HBN_Power_Off_Xtal_32K(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Power_On_RC32K(void){ + return RomDriver_HBN_Power_On_RC32K(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Power_Off_RC32K(void){ + return RomDriver_HBN_Power_Off_RC32K(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Trim_RC32K(void){ + return RomDriver_HBN_Trim_RC32K(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t HBN_Get_Status_Flag(void){ + return RomDriver_HBN_Get_Status_Flag(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_Status_Flag(uint32_t flag){ + return RomDriver_HBN_Set_Status_Flag(flag); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t HBN_Get_Wakeup_Addr(void){ + return RomDriver_HBN_Get_Wakeup_Addr(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr){ + return RomDriver_HBN_Set_Wakeup_Addr(addr); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t HBN_Get_User_Boot_Config(void){ + return RomDriver_HBN_Get_User_Boot_Config(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_User_Boot_Config(uint8_t ubCfg){ + return RomDriver_HBN_Set_User_Boot_Config(ubCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Clear_RTC_Counter(void){ + return RomDriver_HBN_Clear_RTC_Counter(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Enable_RTC_Counter(void){ + return RomDriver_HBN_Enable_RTC_Counter(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode){ + return RomDriver_HBN_Set_RTC_Timer(delay,compValLow,compValHigh,compMode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh){ + return RomDriver_HBN_Get_RTC_Timer_Val(valLow,valHigh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Clear_RTC_INT(void){ + return RomDriver_HBN_Clear_RTC_INT(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType){ + return RomDriver_HBN_GPIO_INT_Enable(gpioIntTrigType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_GPIO_INT_Disable(void){ + return RomDriver_HBN_GPIO_INT_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType){ + return RomDriver_HBN_Get_INT_State(irqType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t HBN_Get_Pin_Wakeup_Mode(void){ + return RomDriver_HBN_Get_Pin_Wakeup_Mode(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType){ + return RomDriver_HBN_Clear_IRQ(irqType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable){ + return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Comm_Pad_Wakeup_En_Cfg(uint8_t padCfg){ + return RomDriver_HBN_Comm_Pad_Wakeup_En_Cfg(padCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg){ + return RomDriver_HBN_Aon_Pad_IeSmt_Cfg(padCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Pin_WakeUp_Mask(uint16_t maskVal){ + return RomDriver_HBN_Pin_WakeUp_Mask(maskVal); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge){ + return RomDriver_HBN_Enable_AComp0_IRQ(edge); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge){ + return RomDriver_HBN_Disable_AComp0_IRQ(edge); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge){ + return RomDriver_HBN_Enable_AComp1_IRQ(edge); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge){ + return RomDriver_HBN_Disable_AComp1_IRQ(edge); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Enable_BOR_IRQ(void){ + return RomDriver_HBN_Enable_BOR_IRQ(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Disable_BOR_IRQ(void){ + return RomDriver_HBN_Disable_BOR_IRQ(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event){ + return RomDriver_HBN_Get_Reset_Event(event); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Clear_Reset_Event(void){ + return RomDriver_HBN_Clear_Reset_Event(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask){ + return RomDriver_HBN_GPIO_Dbg_Pull_Cfg(pupdEn,dlyEn,dlySec,gpioIrq,gpioMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg){ + return RomDriver_HBN_Set_BOR_Cfg(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en){ + return RomDriver_L1C_Cache_Write_Set(wt_en,wb_en,wa_en); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_Cache_Enable_Set(uint8_t way_disable){ + return RomDriver_L1C_Cache_Enable_Set(way_disable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_Cache_Flush(void){ + return RomDriver_L1C_Cache_Flush(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh){ + return RomDriver_L1C_Cache_Hit_Count_Get(hitCountLow,hitCountHigh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t L1C_Cache_Miss_Count_Get(void){ + return RomDriver_L1C_Cache_Miss_Count_Get(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void L1C_Cache_Read_Disable(void){ + return RomDriver_L1C_Cache_Read_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap){ + return RomDriver_L1C_Set_Wrap(wrap); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal){ + return RomDriver_L1C_Set_Way_Disable(disableVal); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable){ + return RomDriver_L1C_IROM_2T_Access_Set(enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg){ + return RomDriver_L1C_BMX_Init(l1cBmxCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void){ + return RomDriver_L1C_BMX_Addr_Monitor_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void){ + return RomDriver_L1C_BMX_Addr_Monitor_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_BMX_BusErrResponse_Enable(void){ + return RomDriver_L1C_BMX_BusErrResponse_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type L1C_BMX_BusErrResponse_Disable(void){ + return RomDriver_L1C_BMX_BusErrResponse_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType){ + return RomDriver_L1C_BMX_Get_Status(errType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t L1C_BMX_Get_Err_Addr(void){ + return RomDriver_L1C_BMX_Get_Err_Addr(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_GPIO_Pad_Cfg(PDS_GPIO_Type pin, PDS_GPIO_Cfg_Type *cfg){ + return RomDriver_PDS_Set_GPIO_Pad_Cfg(pin,cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_GPIO_Write(PDS_GPIO_GROUP_SET_Type grp, uint32_t val){ + return RomDriver_PDS_GPIO_Write(grp,val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_GPIO_Pad_IntMask(PDS_GPIO_GROUP_SET_Type grp, BL_Mask_Type intMask){ + return RomDriver_PDS_Set_GPIO_Pad_IntMask(grp,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_GROUP_SET_Type grp, PDS_GPIO_INT_TRIG_Type trig){ + return RomDriver_PDS_Set_GPIO_Pad_IntMode(grp,trig); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_GROUP_SET_Type grp){ + return RomDriver_PDS_Set_GPIO_Pad_IntClr(grp); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_All_GPIO_IntClear(void){ + return RomDriver_PDS_Set_All_GPIO_IntClear(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(PDS_GPIO_Type pin){ + return RomDriver_PDS_Get_GPIO_Pad_IntStatus(pin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Disable_GPIO_Keep(void){ + return RomDriver_PDS_Disable_GPIO_Keep(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt){ + return RomDriver_PDS_Enable(cfg,cfg4,pdsSleepCnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3){ + return RomDriver_PDS_Force_Config(cfg2,cfg3); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg){ + return RomDriver_PDS_RAM_Config(ramCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt){ + return RomDriver_PDS_Default_Level_Config(defaultLvCfg,pdsSleepCnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Wakeup_Src_En(PDS_WAKEUP_SRC_Type intType, BL_Fun_Type enable){ + return RomDriver_PDS_Wakeup_Src_En(intType,enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type PDS_Get_Wakeup_Src(PDS_WAKEUP_SRC_Type intType){ + return RomDriver_PDS_Get_Wakeup_Src(intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask){ + return RomDriver_PDS_IntMask(intType,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType){ + return RomDriver_PDS_Get_IntStatus(intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_IntClear(void){ + return RomDriver_PDS_IntClear(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +PDS_RF_STS_Type PDS_Get_PdsRfStstus(void){ + return RomDriver_PDS_Get_PdsRfStstus(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +PDS_STS_Type PDS_Get_PdsStstus(void){ + return RomDriver_PDS_Get_PdsStstus(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Clear_Reset_Event(void){ + return RomDriver_PDS_Clear_Reset_Event(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event){ + return RomDriver_PDS_Get_Reset_Event(event); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable){ + return RomDriver_PDS_Auto_Enable(powerCfg,normalCfg,enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain){ + return RomDriver_PDS_Manual_Force_Turn_Off(domain); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain){ + return RomDriver_PDS_Manual_Force_Turn_On(domain); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_KYD_Matrix_Size(uint8_t col_size, uint8_t row_size){ + return RomDriver_PDS_Set_KYD_Matrix_Size(col_size,row_size); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_KYD_Col_Value(uint8_t val){ + return RomDriver_PDS_Set_KYD_Col_Value(val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_KYD_Row_Pull(uint8_t en){ + return RomDriver_PDS_Set_KYD_Row_Pull(en); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type PDS_Set_KYD_Wakeup_En(uint8_t en){ + return RomDriver_PDS_Set_KYD_Wakeup_En(en); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_cfg_init_internal_flash_gpio(void){ + return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin){ + return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin){ + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank){ + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id,p_flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default){ + return RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg,restore_default); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank){ + uint8_t auto_scan = 0; + uint8_t flash_pin = 0; + auto_scan = ((flash_pin_cfg >> 7) & 1); + flash_pin = (flash_pin_cfg & 0x7F); + return RomDriver_SF_Cfg_Flash_Identify(call_from_flash,auto_scan,flash_pin,restore_default,p_flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg){ + return RomDriver_SF_Ctrl_Enable(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg){ + return RomDriver_SF_Ctrl_Psram_Init(sf_ctrl_psram_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t bflb_sf_ctrl_get_clock_delay(void){ + return RomDriver_SF_Ctrl_Get_Clock_Delay(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_set_clock_delay(uint8_t delay){ + return RomDriver_SF_Ctrl_Set_Clock_Delay(delay); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel){ + return RomDriver_SF_Ctrl_Cmds_Set(cmds_cfg,sel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode){ + return RomDriver_SF_Ctrl_Burst_Toggle_Set(burst_toggle_en,mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_select_pad(uint8_t sel){ + return RomDriver_SF_Ctrl_Select_Pad(sel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_select_bank(uint8_t sel){ + return RomDriver_SF_Ctrl_Select_Bank(sel); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_set_owner(uint8_t owner){ + return RomDriver_SF_Ctrl_Set_Owner(owner); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_disable(void){ + return RomDriver_SF_Ctrl_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_enable_be(void){ + return RomDriver_SF_Ctrl_AES_Enable_BE(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_enable_le(void){ + return RomDriver_SF_Ctrl_AES_Enable_LE(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t start_addr, uint32_t end_addr, uint8_t locked){ + return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,start_addr,end_addr,locked); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type){ + return RomDriver_SF_Ctrl_AES_Set_Key(region,key,key_type); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type){ + return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,key_type); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset){ + return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addr_offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset){ + return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addr_offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_enable(void){ + return RomDriver_SF_Ctrl_AES_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_aes_disable(void){ + return RomDriver_SF_Ctrl_AES_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t bflb_sf_ctrl_is_aes_enable(void){ + return RomDriver_SF_Ctrl_Is_AES_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank){ + return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank){ + return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg){ + return RomDriver_SF_Ctrl_SendCmd(cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_flash_read_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){ + return RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg,cmd_valid); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_psram_write_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){ + return RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg,cmd_valid); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sf_ctrl_psram_read_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){ + return RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg,cmd_valid); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t bflb_sf_ctrl_get_busy_state(void){ + return RomDriver_SF_Ctrl_GetBusyState(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg){ + return RomDriver_SFlash_Init(p_sf_ctrl_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_set_spi_mode(uint8_t mode){ + return RomDriver_SFlash_SetSPIMode(mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Read_Reg(flash_cfg,reg_index,reg_value,reg_len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Write_Reg(flash_cfg,reg_index,reg_value,reg_len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg,read_reg_cmd,reg_value,reg_len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg,write_reg_cmd,reg_value,reg_len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg){ + return RomDriver_SFlash_Clear_Status_Register(p_flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Busy(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Write_Enable(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Qspi_Enable(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Chip_Erase(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sec_num){ + return RomDriver_SFlash_Sector_Erase(flash_cfg,sec_num); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num){ + return RomDriver_SFlash_Blk32_Erase(flash_cfg,blk_num); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num){ + return RomDriver_SFlash_Blk64_Erase(flash_cfg,blk_num); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t startaddr, uint32_t endaddr){ + return RomDriver_SFlash_Erase(flash_cfg,startaddr,endaddr); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len){ + return RomDriver_SFlash_Program(flash_cfg,io_mode,addr,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len){ + return RomDriver_SFlash_GetUniqueId(data,id_len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data){ + return RomDriver_SFlash_GetJedecId(flash_cfg,data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr){ + return RomDriver_SFlash_GetDeviceId(data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_powerdown(void){ + return RomDriver_SFlash_Powerdown(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_releae_powerdown(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Releae_Powerdown(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flash_cont_read, uint8_t bank){ + return RomDriver_SFlash_Restore_From_Powerdown(p_flash_cfg,flash_cont_read); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_SetBurstWrap(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_DisableBurstWrap(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Software_Reset(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Reset_Continue_Read(flash_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_set_idbus_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank){ + return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg,io_mode,cont_read,addr,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank){ + return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg,io_mode,cont_read); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_cache_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t way_disable){ + return RomDriver_SFlash_Cache_Read_Enable(flash_cfg,io_mode,cont_read,way_disable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_sflash_cache_read_disable(void){ + return RomDriver_SFlash_Cache_Read_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len){ + return RomDriver_SFlash_Read(flash_cfg,io_mode,cont_read,addr,data,len); +} +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate){ + return RomDriver_UART_SetBaudRate(uartId,baudRate); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg){ + return RomDriver_UART_Init(uartId,uartCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_DeInit(UART_ID_Type uartId){ + return RomDriver_UART_DeInit(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg){ + return RomDriver_UART_FifoConfig(uartId,fifoCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct){ + return RomDriver_UART_Enable(uartId,direct); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct){ + return RomDriver_UART_Disable(uartId,direct); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length){ + return RomDriver_UART_SetTxDataLength(uartId,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length){ + return RomDriver_UART_SetRxDataLength(uartId,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time){ + return RomDriver_UART_SetRxTimeoutValue(uartId,time); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count){ + return RomDriver_UART_SetRxByteCount(uartId,count); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt){ + return RomDriver_UART_SetDeglitchCount(uartId,deglitchCnt); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){ + return RomDriver_UART_ApplyAbrResult(uartId,autoBaudDet); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId){ + return RomDriver_UART_SetRtsValue(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId){ + return RomDriver_UART_ClrRtsValue(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetTxValue(UART_ID_Type uartId){ + return RomDriver_UART_SetTxValue(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId){ + return RomDriver_UART_ClrTxValue(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun){ + return RomDriver_UART_TxFreeRun(uartId,txFreeRun); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud){ + return RomDriver_UART_AutoBaudDetection(uartId,autoBaud); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError){ + return RomDriver_UART_SetAllowableError0X55(uartId,allowableError); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width){ + return RomDriver_UART_GetBitWidth0X55(uartId,width); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity){ + return RomDriver_UART_SetRS485(uartId,enable,polarity); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId){ + return RomDriver_UART_TxFifoClear(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId){ + return RomDriver_UART_RxFifoClear(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask){ + return RomDriver_UART_IntMask(uartId,intType,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType){ + return RomDriver_UART_IntClear(uartId,intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len){ + return RomDriver_UART_SendData(uartId,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len){ + return RomDriver_UART_SendDataBlock(uartId,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen){ + return RomDriver_UART_ReceiveData(uartId,data,maxLen); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){ + return RomDriver_UART_GetAutoBaudCount(uartId,autoBaudDet); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint16_t UART_GetRxByteCount(UART_ID_Type uartId){ + return RomDriver_UART_GetRxByteCount(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t UART_GetTxFifoCount(UART_ID_Type uartId){ + return RomDriver_UART_GetTxFifoCount(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t UART_GetRxFifoCount(UART_ID_Type uartId){ + return RomDriver_UART_GetRxFifoCount(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType){ + return RomDriver_UART_GetIntStatus(uartId,intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId){ + return RomDriver_UART_GetTxBusBusyStatus(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId){ + return RomDriver_UART_GetRxBusBusyStatus(uartId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow){ + return RomDriver_UART_GetOverflowStatus(uartId,overflow); +} +#endif +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_xip_sflash_opt_enter(uint8_t *aes_enable){ + return RomDriver_XIP_SFlash_Opt_Enter(aes_enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_xip_sflash_opt_exit(uint8_t aes_enable){ + return RomDriver_XIP_SFlash_Opt_Exit(aes_enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_State_Save(p_flash_cfg,offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_State_Restore(p_flash_cfg,offset); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Erase_Need_Lock(p_flash_cfg,startaddr,startaddr+len-1); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Write_Need_Lock(p_flash_cfg,addr,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Read_Need_Lock(p_flash_cfg,addr,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(p_flash_cfg,data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(p_flash_cfg,data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t id_len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(p_flash_cfg,data,id_len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Clear_Status_Register_Need_Lock(p_flash_cfg); +} +#if 0 +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg){ + return RomDriver_IR_TxInit(irTxCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg){ + return RomDriver_IR_TxPulseWidthConfig(irTxPulseWidthCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_FifoConfig(IR_FifoCfg_Type *fifoCfg){ + return RomDriver_IR_FifoConfig(fifoCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_DeInit(void){ + return RomDriver_IR_DeInit(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_Enable(IR_Direction_Type direct){ + return RomDriver_IR_Enable(direct); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_Disable(IR_Direction_Type direct){ + return RomDriver_IR_Disable(direct); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM){ + return RomDriver_IR_TxSWM(txSWM); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_TxFifoClear(void){ + return RomDriver_IR_TxFifoClear(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_SendData(uint32_t *data, uint8_t length){ + return RomDriver_IR_SendData(data,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length){ + return RomDriver_IR_SWMSendData(data,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_SendCommand(uint32_t *data, uint8_t length){ + return RomDriver_IR_SendCommand(data,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length){ + return RomDriver_IR_SWMSendCommand(data,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command){ + return RomDriver_IR_SendNEC(address,command); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask){ + return RomDriver_IR_IntMask(intType,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType){ + return RomDriver_IR_ClrIntStatus(intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType){ + return RomDriver_IR_GetIntStatus(intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type IR_GetFifoStatus(IR_FifoStatus_Type fifoSts){ + return RomDriver_IR_GetFifoStatus(fifoSts); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t IR_GetTxFifoCount(void){ + return RomDriver_IR_GetTxFifoCount(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_LEDInit(uint8_t clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L){ + return RomDriver_IR_LEDInit(clk,div,unit,code0H,code0L,code1H,code1L); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type IR_LEDSend(uint32_t data){ + return RomDriver_IR_LEDSend(data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type KYS_Init(KYS_CFG_Type *kysCfg){ + return RomDriver_KYS_Init(kysCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type KYS_Enable(void){ + return RomDriver_KYS_Enable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type KYS_Disable(void){ + return RomDriver_KYS_Disable(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type KYS_IntMask(KYS_INT_Type intType, BL_Mask_Type intMask){ + return RomDriver_KYS_IntMask(intType,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type KYS_IntClear(KYS_INT_CLR_Type intType){ + return RomDriver_KYS_IntClear(intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type KYS_GetIntStatus(KYS_INT_Type intType){ + return RomDriver_KYS_GetIntStatus(intType); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void KYS_Get_FIFO_Idx(uint8_t *fifo_head, uint8_t *fifo_tail){ + return RomDriver_KYS_Get_FIFO_Idx(fifo_head,fifo_tail); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint8_t KYS_ReadKeyfifo(void){ + return RomDriver_KYS_ReadKeyfifo(); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg, struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg){ + return RomDriver_Psram_Init(psram_cfg,cmds_cfg,sf_ctrl_psram_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value){ + return RomDriver_Psram_ReadReg(psram_cfg,reg_value); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value){ + return RomDriver_Psram_WriteReg(psram_cfg,reg_value); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg){ + return RomDriver_Psram_SetDriveStrength(psram_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg){ + return RomDriver_Psram_SetBurstWrap(psram_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data){ + return RomDriver_Psram_ReadId(psram_cfg,data); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg){ + return RomDriver_Psram_EnterQuadMode(psram_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg){ + return RomDriver_Psram_ExitQuadMode(psram_cfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode){ + return RomDriver_Psram_ToggleBurstLength(psram_cfg,ctrl_mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode){ + return RomDriver_Psram_SoftwareReset(psram_cfg,ctrl_mode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len){ + return RomDriver_Psram_Set_IDbus_Cfg(psram_cfg,io_mode,addr,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, BL_Fun_Type wt_en, BL_Fun_Type wb_en, BL_Fun_Type wa_en){ + return RomDriver_Psram_Cache_Write_Set(psram_cfg,io_mode,wt_en,wb_en,wa_en); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len){ + return RomDriver_Psram_Write(psram_cfg,io_mode,addr,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len){ + return RomDriver_Psram_Read(psram_cfg,io_mode,addr,data,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo){ + return RomDriver_TIMER_GetCompValue(timerId,timerCh,cmpNo); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val){ + return RomDriver_TIMER_SetCompValue(timerId,timerCh,cmpNo,val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable){ + return RomDriver_TIMER_CompValueEffectImmediately(timerId,timerCh,enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh){ + return RomDriver_TIMER_GetCounterValue(timerId,timerCh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh){ + return RomDriver_TIMER_ResetCounterValue(timerId,timerCh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo){ + return RomDriver_TIMER_GetMatchStatus(timerId,timerCh,cmpNo); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh){ + return RomDriver_TIMER_GetPreloadValue(timerId,timerCh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val){ + return RomDriver_TIMER_SetPreloadValue(timerId,timerCh,val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc){ + return RomDriver_TIMER_SetPreloadTrigSrc(timerId,timerCh,plSrc); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode){ + return RomDriver_TIMER_SetCountMode(timerId,timerCh,countMode); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo){ + return RomDriver_TIMER_ClearIntStatus(timerId,timerCh,cmpNo); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg){ + return RomDriver_TIMER_Init(timerId,timerCfg); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId){ + return RomDriver_TIMER_DeInit(timerId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh){ + return RomDriver_TIMER_Enable(timerId,timerCh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh){ + return RomDriver_TIMER_Disable(timerId,timerCh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask){ + return RomDriver_TIMER_IntMask(timerId,timerCh,intType,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity){ + return RomDriver_TIMER_GPIOSetPolarity(timerId,timerCh,polarity); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable){ + return RomDriver_TIMER_CH0_SetMeasurePulseWidth(timerId,enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId){ + return RomDriver_TIMER_CH0_GetMeasurePulseWidth(timerId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh){ + return RomDriver_TIMER_ForceClockDivision(timerId,timerCh); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div){ + return RomDriver_WDT_Set_Clock(wdtId,clkSrc,div); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId){ + return RomDriver_WDT_GetMatchValue(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val){ + return RomDriver_WDT_SetCompValue(wdtId,val); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable){ + return RomDriver_WDT_CompValueEffectImmediately(wdtId,enable); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId){ + return RomDriver_WDT_GetCounterValue(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_ResetCounterValue(WDT_ID_Type wdtId){ + return RomDriver_WDT_ResetCounterValue(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId){ + return RomDriver_WDT_GetResetStatus(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_ClearResetStatus(WDT_ID_Type wdtId){ + return RomDriver_WDT_ClearResetStatus(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_Enable(WDT_ID_Type wdtId){ + return RomDriver_WDT_Enable(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_Disable(WDT_ID_Type wdtId){ + return RomDriver_WDT_Disable(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_ForceClockDivision(WDT_ID_Type wdtId){ + return RomDriver_WDT_ForceClockDivision(wdtId); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask){ + return RomDriver_WDT_IntMask(wdtId,intType,intMask); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity){ + return RomDriver_WDT_GPIOSetPolarity(wdtId,polarity); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void * arch_memcpy(void *dst, const void *src, uint32_t n){ + return RomDriver_arch_memcpy(dst,src,n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t * arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n){ + return RomDriver_arch_memcpy4(dst,src,n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void * arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n){ + return RomDriver_arch_memcpy_fast(pdst,psrc,n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void * arch_memset(void *s, uint8_t c, uint32_t n){ + return RomDriver_arch_memset(s,c,n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t * arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n){ + return RomDriver_arch_memset4(dst,val,n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +int arch_memcmp(const void *s1, const void *s2, uint32_t n){ + return RomDriver_arch_memcmp(s1,s2,n); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length){ + return RomDriver_memcopy_to_fifo(fifo_addr,data,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length){ + return RomDriver_fifocopy_to_mem(fifo_addr,data,length); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len){ + return RomDriver_BFLB_Soft_CRC32_Ex(initial,dataIn,len); +} + +__ALWAYS_INLINE ATTR_TCM_SECTION +uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len){ + return RomDriver_BFLB_Soft_CRC32(dataIn,len); +} +#endif \ No newline at end of file diff --git a/drivers/soc/bl702l/std/src/bl702l_romapi_patch.c b/drivers/soc/bl702l/std/src/bl702l_romapi_patch.c new file mode 100644 index 000000000..86b533455 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_romapi_patch.c @@ -0,0 +1,246 @@ +/** + ****************************************************************************** + * @file bl702l_romapi_patch.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2021 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_romapi_patch.h" +#include "bl702l_romdriver.h" + + +typedef struct +{ + uint32_t jedec_id; + char *name; + const spi_flash_cfg_type *cfg; +} Flash_Info_t; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_16JV = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xef, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3d, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 3000, + .time_e_32k = 5000, + .time_e_64k = 5000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION Flash_Info_t flash_infos[] = { + { + .jedec_id = 0x14650b, + //.name="XTX_25W08F_08_1833", + .cfg = &flash_cfg_Winb_16JV, + }, +}; + +//FLASH +/****************************************************************************/ /** + * @brief Get flash config according to flash ID patch + * + * @param flash_id: Flash ID + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) +{ + uint32_t i; + uint8_t buf[sizeof(spi_flash_cfg_type) + 8]; + uint32_t crc, *p_crc; + uint32_t xip_offset; + char flash_cfg_magic[] = "FCFG"; + + if (flash_id == 0) { + xip_offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); + bflb_xip_sflash_read_via_cache_need_lock(8 + BL702L_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank); + bflb_sf_ctrl_set_flash_image_offset(xip_offset, group, bank); + + if (arch_memcmp(buf, flash_cfg_magic, 4) == 0) { + crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + p_crc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type)); + + if (*p_crc == crc) { + arch_memcpy_fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + return 0; + } + } + } else { + if (RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg) == 0) { + return 0; + } + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == flash_id) { + arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); + return 0; + } + } + } + + return -1; +} + +/****************************************************************************/ /** + * @brief Identify one flash patch + * + * @param call_from_flash: code run at flash or ram + * @param flash_pin_cfg: Bit 7: autoscan, Bit6-0: flash GPIO config + * @param restore_default: Wether restore default flash GPIO config + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return Flash ID + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, + uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) +{ + uint32_t jedec_id = 0; + uint32_t i = 0; + uint32_t ret = 0; + + ret = bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank); + if (call_from_flash) { + bflb_sflash_set_xip_cfg(p_flash_cfg, p_flash_cfg->io_mode & 0xf, 1, 0, 32, bank); + } + if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) { + return ret; + } + + jedec_id = (ret & 0xffffff); + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == jedec_id) { + arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); + break; + } + } + if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) { + return jedec_id; + } else { + return (jedec_id | BFLB_FLASH_ID_VALID_FLAG); + } +} + diff --git a/drivers/soc/bl702l/std/src/bl702l_romdriver.c b/drivers/soc/bl702l/std/src/bl702l_romdriver.c new file mode 100644 index 000000000..6c748401a --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_romdriver.c @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file bl702l_romdriver.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2021 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl702l_romdriver.h" +#include + +/** @addtogroup BL702L_Periph_Driver + * @{ + */ + +/** @defgroup ROMDRIVER + * @brief ROMDRIVER common functions + * @{ + */ + +/** @defgroup ROMDRIVER_Private_Type + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Type*/ + +/** @defgroup ROMDRIVER_Private_Defines + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Defines */ + +/** @defgroup ROMDRIVER_Private_Variables + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Variables */ + +/** @defgroup ROMDRIVER_Global_Variables + * @{ + */ + + +uint32_t const romDriverTable[]={ + 0x07020001, + 0x00000000, + 0x00000000, + 0x00000000, + + + [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG, + [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG, + [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL, + [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode, + [ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode, + [ROM_API_INDEX_AON_Set_Xtal_CapCode_Extra] = (uint32_t)AON_Set_Xtal_CapCode_Extra, + [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL, + [ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG, + [ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG, + [ROM_API_INDEX_AON_Power_On_LDO11_SOC] = (uint32_t)AON_Power_On_LDO11_SOC, + [ROM_API_INDEX_AON_Power_Off_LDO11_SOC] = (uint32_t)AON_Power_Off_LDO11_SOC, + [ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg, + [ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg, + [ROM_API_INDEX_AON_Set_LDO11_SOC_Sstart_Delay] = (uint32_t)AON_Set_LDO11_SOC_Sstart_Delay, + [ROM_API_INDEX_AON_Set_DCDC14_Top_0] = (uint32_t)AON_Set_DCDC14_Top_0, + [ROM_API_INDEX_AON_Trim_Ldo11socVoutTrim] = (uint32_t)AON_Trim_Ldo11socVoutTrim, + [ROM_API_INDEX_AON_Trim_Ldo14VoutTrim] = (uint32_t)AON_Trim_Ldo14VoutTrim, + [ROM_API_INDEX_AON_Trim_Dcdc14VoutTrim] = (uint32_t)AON_Trim_Dcdc14VoutTrim, + + [ROM_API_INDEX_Clock_System_Clock_Get] = (uint32_t)Clock_System_Clock_Get, + [ROM_API_INDEX_Clock_Peripheral_Clock_Get] = (uint32_t)Clock_Peripheral_Clock_Get, + + [ROM_API_INDEX_SystemCoreClockGet] = (uint32_t)SystemCoreClockGet, + + [ROM_API_INDEX_CPU_Get_MTimer_Clock] = (uint32_t)CPU_Get_MTimer_Clock, + [ROM_API_INDEX_CPU_Get_MTimer_Counter] = (uint32_t)CPU_Get_MTimer_Counter, + [ROM_API_INDEX_CPU_Get_CPU_Cycle] = (uint32_t)CPU_Get_CPU_Cycle, + [ROM_API_INDEX_CPU_Get_MTimer_US] = (uint32_t)CPU_Get_MTimer_US, + [ROM_API_INDEX_CPU_Get_MTimer_MS] = (uint32_t)CPU_Get_MTimer_MS, + [ROM_API_INDEX_CPU_MTimer_Delay_US] = (uint32_t)CPU_MTimer_Delay_US, + [ROM_API_INDEX_CPU_MTimer_Delay_MS] = (uint32_t)CPU_MTimer_Delay_MS, + + [ROM_API_INDEX_BL702L_Delay_US] = (uint32_t)BL702L_Delay_US, + [ROM_API_INDEX_BL702L_Delay_MS] = (uint32_t)BL702L_Delay_MS, + + [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity, + [ROM_API_INDEX_EF_Ctrl_Read_Common_Trim] = (uint32_t)EF_Ctrl_Read_Common_Trim, + [ROM_API_INDEX_EF_Ctrl_Write_Common_Trim] = (uint32_t)EF_Ctrl_Write_Common_Trim, + [ROM_API_INDEX_EF_Ctrl_Is_MAC_Address_Slot_Empty] = (uint32_t)EF_Ctrl_Is_MAC_Address_Slot_Empty, + [ROM_API_INDEX_EF_Ctrl_Write_MAC_Address_Opt] = (uint32_t)EF_Ctrl_Write_MAC_Address_Opt, + [ROM_API_INDEX_EF_Ctrl_Read_MAC_Address_Opt] = (uint32_t)EF_Ctrl_Read_MAC_Address_Opt, + [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0, + [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0, + [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0, + [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy, + [ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done, + [ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd] = (uint32_t)EF_Ctrl_Write_Dbg_Pwd, + [ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd] = (uint32_t)EF_Ctrl_Read_Dbg_Pwd, + [ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd] = (uint32_t)EF_Ctrl_Readlock_Dbg_Pwd, + [ROM_API_INDEX_EF_Ctrl_Writelock_Dbg_Pwd] = (uint32_t)EF_Ctrl_Writelock_Dbg_Pwd, + [ROM_API_INDEX_EF_Ctrl_Write_Secure_Cfg] = (uint32_t)EF_Ctrl_Write_Secure_Cfg, + [ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg] = (uint32_t)EF_Ctrl_Read_Secure_Cfg, + [ROM_API_INDEX_EF_Ctrl_Write_Secure_Boot] = (uint32_t)EF_Ctrl_Write_Secure_Boot, + [ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot] = (uint32_t)EF_Ctrl_Read_Secure_Boot, + [ROM_API_INDEX_EF_Ctrl_Write_Sw_Usage] = (uint32_t)EF_Ctrl_Write_Sw_Usage, + [ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage] = (uint32_t)EF_Ctrl_Read_Sw_Usage, + [ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage] = (uint32_t)EF_Ctrl_Writelock_Sw_Usage, + [ROM_API_INDEX_EF_Ctrl_Write_MAC_Address] = (uint32_t)EF_Ctrl_Write_MAC_Address, + [ROM_API_INDEX_EF_Ctrl_Get_Byte_Zero_Cnt] = (uint32_t)EF_Ctrl_Get_Byte_Zero_Cnt, + [ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero] = (uint32_t)EF_Ctrl_Is_All_Bits_Zero, + [ROM_API_INDEX_EF_Ctrl_Read_MAC_Address] = (uint32_t)EF_Ctrl_Read_MAC_Address, + [ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address] = (uint32_t)EF_Ctrl_Writelock_MAC_Address, + [ROM_API_INDEX_EF_Ctrl_Read_Chip_ID] = (uint32_t)EF_Ctrl_Read_Chip_ID, + [ROM_API_INDEX_EF_Ctrl_Read_Device_Info] = (uint32_t)EF_Ctrl_Read_Device_Info, + [ROM_API_INDEX_EF_Ctrl_Is_CapCode_Empty] = (uint32_t)EF_Ctrl_Is_CapCode_Empty, + [ROM_API_INDEX_EF_Ctrl_Write_CapCode_Opt] = (uint32_t)EF_Ctrl_Write_CapCode_Opt, + [ROM_API_INDEX_EF_Ctrl_Read_CapCode_Opt] = (uint32_t)EF_Ctrl_Read_CapCode_Opt, + [ROM_API_INDEX_EF_Ctrl_Is_PowerOffset_Slot_Empty] = (uint32_t)EF_Ctrl_Is_PowerOffset_Slot_Empty, + [ROM_API_INDEX_EF_Ctrl_Write_PowerOffset_Opt] = (uint32_t)EF_Ctrl_Write_PowerOffset_Opt, + [ROM_API_INDEX_EF_Ctrl_Read_PowerOffset_Opt] = (uint32_t)EF_Ctrl_Read_PowerOffset_Opt, + [ROM_API_INDEX_EF_Ctrl_Write_AES_Key] = (uint32_t)EF_Ctrl_Write_AES_Key, + [ROM_API_INDEX_EF_Ctrl_Read_AES_Key] = (uint32_t)EF_Ctrl_Read_AES_Key, + [ROM_API_INDEX_EF_Ctrl_Writelock_AES_Key] = (uint32_t)EF_Ctrl_Writelock_AES_Key, + [ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key] = (uint32_t)EF_Ctrl_Readlock_AES_Key, + [ROM_API_INDEX_EF_Ctrl_Program_Direct_R0] = (uint32_t)EF_Ctrl_Program_Direct_R0, + [ROM_API_INDEX_EF_Ctrl_Read_Direct_R0] = (uint32_t)EF_Ctrl_Read_Direct_R0, + [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear, + [ROM_API_INDEX_EF_Ctrl_Crc_Enable] = (uint32_t)EF_Ctrl_Crc_Enable, + [ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy] = (uint32_t)EF_Ctrl_Crc_Is_Busy, + [ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden] = (uint32_t)EF_Ctrl_Crc_Set_Golden, + [ROM_API_INDEX_EF_Ctrl_Crc_Result] = (uint32_t)EF_Ctrl_Crc_Result, + + [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel, + [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div, + [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div, + [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div, + [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK, + + [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M, + + [ROM_API_INDEX_GLB_Set_MAC154_ZIGBEE_CLK] = (uint32_t)GLB_Set_MAC154_ZIGBEE_CLK, + [ROM_API_INDEX_GLB_Set_BLE_CLK] = (uint32_t)GLB_Set_BLE_CLK, + [ROM_API_INDEX_GLB_Set_AUDIO_CLK] = (uint32_t)GLB_Set_AUDIO_CLK, + [ROM_API_INDEX_GLB_Set_KYS_CLK] = (uint32_t)GLB_Set_KYS_CLK, + [ROM_API_INDEX_GLB_Set_DMA_CLK] = (uint32_t)GLB_Set_DMA_CLK, + [ROM_API_INDEX_GLB_Set_IR_CLK] = (uint32_t)GLB_Set_IR_CLK, + [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK, + [ROM_API_INDEX_GLB_Set_UART_CLK] = (uint32_t)GLB_Set_UART_CLK, + [ROM_API_INDEX_GLB_Sel_TMR_GPIO_Clock] = (uint32_t)GLB_Sel_TMR_GPIO_Clock, + [ROM_API_INDEX_GLB_Set_Chip_Out_0_CLK_Sel] = (uint32_t)GLB_Set_Chip_Out_0_CLK_Sel, + [ROM_API_INDEX_GLB_Set_Chip_Out_1_CLK_Sel] = (uint32_t)GLB_Set_Chip_Out_1_CLK_Sel, + [ROM_API_INDEX_GLB_Set_Chip_Out_0_CLK_Enable] = (uint32_t)GLB_Set_Chip_Out_0_CLK_Enable, + [ROM_API_INDEX_GLB_Set_Chip_Out_1_CLK_Enable] = (uint32_t)GLB_Set_Chip_Out_1_CLK_Enable, + [ROM_API_INDEX_GLB_Set_I2C_CLK] = (uint32_t)GLB_Set_I2C_CLK, + [ROM_API_INDEX_GLB_Set_SPI_CLK] = (uint32_t)GLB_Set_SPI_CLK, + [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel, + [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset, + [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset, + [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset, + [ROM_API_INDEX_GLB_AHB_MCU_Software_Reset] = (uint32_t)GLB_AHB_MCU_Software_Reset, + [ROM_API_INDEX_GLB_Disrst_Set] = (uint32_t)GLB_Disrst_Set, + [ROM_API_INDEX_GLB_MAC154_ZIGBEE_Reset] = (uint32_t)GLB_MAC154_ZIGBEE_Reset, + [ROM_API_INDEX_GLB_BLE_Reset] = (uint32_t)GLB_BLE_Reset, + [ROM_API_INDEX_GLB_PER_Clock_Gate] = (uint32_t)GLB_PER_Clock_Gate, + [ROM_API_INDEX_GLB_PER_Clock_UnGate] = (uint32_t)GLB_PER_Clock_UnGate, + [ROM_API_INDEX_GLB_Set_RTC_Mode] = (uint32_t)GLB_Set_RTC_Mode, + [ROM_API_INDEX_GLB_BMX_Init] = (uint32_t)GLB_BMX_Init, + [ROM_API_INDEX_GLB_BMX_Addr_Monitor_Enable] = (uint32_t)GLB_BMX_Addr_Monitor_Enable, + [ROM_API_INDEX_GLB_BMX_Addr_Monitor_Disable] = (uint32_t)GLB_BMX_Addr_Monitor_Disable, + [ROM_API_INDEX_GLB_BMX_BusErrResponse_Enable] = (uint32_t)GLB_BMX_BusErrResponse_Enable, + [ROM_API_INDEX_GLB_BMX_BusErrResponse_Disable] = (uint32_t)GLB_BMX_BusErrResponse_Disable, + [ROM_API_INDEX_GLB_BMX_Get_Status] = (uint32_t)GLB_BMX_Get_Status, + [ROM_API_INDEX_GLB_BMX_Get_Err_Addr] = (uint32_t)GLB_BMX_Get_Err_Addr, + [ROM_API_INDEX_GLB_BMX_BusErrClr_Set] = (uint32_t)GLB_BMX_BusErrClr_Set, + [ROM_API_INDEX_GLB_Set_SRAM_PARM] = (uint32_t)GLB_Set_SRAM_PARM, + [ROM_API_INDEX_GLB_Get_SRAM_PARM] = (uint32_t)GLB_Get_SRAM_PARM, + [ROM_API_INDEX_GLB_Set_OCRAM_PARM] = (uint32_t)GLB_Set_OCRAM_PARM, + [ROM_API_INDEX_GLB_Get_OCRAM_PARM] = (uint32_t)GLB_Get_OCRAM_PARM, + [ROM_API_INDEX_GLB_Set_EM_Sel] = (uint32_t)GLB_Set_EM_Sel, + [ROM_API_INDEX_GLB_Set_Kys_Drv_Col] = (uint32_t)GLB_Set_Kys_Drv_Col, + [ROM_API_INDEX_GLB_GPIO_O_Latch_Mode_Set] = (uint32_t)GLB_GPIO_O_Latch_Mode_Set, + [ROM_API_INDEX_GLB_JTAG_Sig_Swap_Set] = (uint32_t)GLB_JTAG_Sig_Swap_Set, + [ROM_API_INDEX_GLB_CCI_Use_IO_0_1_2_7] = (uint32_t)GLB_CCI_Use_IO_0_1_2_7, + [ROM_API_INDEX_GLB_CCI_Use_Jtag_Pin] = (uint32_t)GLB_CCI_Use_Jtag_Pin, + [ROM_API_INDEX_GLB_Swap_SPI_0_MOSI_With_MISO] = (uint32_t)GLB_Swap_SPI_0_MOSI_With_MISO, + [ROM_API_INDEX_GLB_Set_SPI_0_ACT_MOD_Sel] = (uint32_t)GLB_Set_SPI_0_ACT_MOD_Sel, + [ROM_API_INDEX_GLB_Set_Flash_Scenario] = (uint32_t)GLB_Set_Flash_Scenario, + [ROM_API_INDEX_GLB_Set_Embedded_FLash_IO_PARM] = (uint32_t)GLB_Set_Embedded_FLash_IO_PARM, + [ROM_API_INDEX_GLB_Set_MTimer_CLK] = (uint32_t)GLB_Set_MTimer_CLK, + [ROM_API_INDEX_GLB_Set_ADC_CLK] = (uint32_t)GLB_Set_ADC_CLK, + [ROM_API_INDEX_GLB_Set_DIG_32K_CLK] = (uint32_t)GLB_Set_DIG_32K_CLK, + [ROM_API_INDEX_GLB_SW_BLE_WAKEUP_REQ_Set] = (uint32_t)GLB_SW_BLE_WAKEUP_REQ_Set, + [ROM_API_INDEX_GLB_UART_Fun_Sel] = (uint32_t)GLB_UART_Fun_Sel, + [ROM_API_INDEX_GLB_Power_Off_DLL] = (uint32_t)GLB_Power_Off_DLL, + [ROM_API_INDEX_GLB_Power_On_DLL] = (uint32_t)GLB_Power_On_DLL, + [ROM_API_INDEX_GLB_Enable_DLL_All_Clks] = (uint32_t)GLB_Enable_DLL_All_Clks, + [ROM_API_INDEX_GLB_Enable_DLL_Clk] = (uint32_t)GLB_Enable_DLL_Clk, + [ROM_API_INDEX_GLB_Disable_DLL_All_Clks] = (uint32_t)GLB_Disable_DLL_All_Clks, + [ROM_API_INDEX_GLB_Disable_DLL_Clk] = (uint32_t)GLB_Disable_DLL_Clk, + [ROM_API_INDEX_GLB_Set_Flash_Id_Value] = (uint32_t)GLB_Set_Flash_Id_Value, + [ROM_API_INDEX_GLB_Get_Flash_Id_Value] = (uint32_t)GLB_Get_Flash_Id_Value, + [ROM_API_INDEX_GLB_Trim_RC32M] = (uint32_t)GLB_Trim_RC32M, + [ROM_API_INDEX_GLB_Set_Xtal_Cnt32k_Process] = (uint32_t)GLB_Set_Xtal_Cnt32k_Process, + [ROM_API_INDEX_GLB_Clear_Xtal_Cnt32k_Done] = (uint32_t)GLB_Clear_Xtal_Cnt32k_Done, + [ROM_API_INDEX_GLB_RC32K_Deg_Start] = (uint32_t)GLB_RC32K_Deg_Start, + [ROM_API_INDEX_GLB_RC32K_Deg_End] = (uint32_t)GLB_RC32K_Deg_End, + [ROM_API_INDEX_GLB_RC32K_Deg_Enable] = (uint32_t)GLB_RC32K_Deg_Enable, + [ROM_API_INDEX_GLB_Xtal_Deg_Cnt_Limit_Set] = (uint32_t)GLB_Xtal_Deg_Cnt_Limit_Set, + [ROM_API_INDEX_GLB_IR_LED_Driver_Enable] = (uint32_t)GLB_IR_LED_Driver_Enable, + [ROM_API_INDEX_GLB_IR_LED_Driver_Disable] = (uint32_t)GLB_IR_LED_Driver_Disable, + [ROM_API_INDEX_GLB_IR_LED_Driver_Output_Enable] = (uint32_t)GLB_IR_LED_Driver_Output_Enable, + [ROM_API_INDEX_GLB_IR_LED_Driver_Output_Disable] = (uint32_t)GLB_IR_LED_Driver_Output_Disable, + [ROM_API_INDEX_GLB_IR_LED_Driver_Ibias] = (uint32_t)GLB_IR_LED_Driver_Ibias, + [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init, + [ROM_API_INDEX_GLB_GPIO_Func_Init] = (uint32_t)GLB_GPIO_Func_Init, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Mode_Set] = (uint32_t)GLB_GPIO_OUTPUT_Mode_Set, + [ROM_API_INDEX_GLB_GPIO_INPUT_Enable] = (uint32_t)GLB_GPIO_INPUT_Enable, + [ROM_API_INDEX_GLB_GPIO_INPUT_Disable] = (uint32_t)GLB_GPIO_INPUT_Disable, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable, + [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ, + [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun, + [ROM_API_INDEX_GLB_GPIO_Write] = (uint32_t)GLB_GPIO_Write, + [ROM_API_INDEX_GLB_GPIO_Read] = (uint32_t)GLB_GPIO_Read, + [ROM_API_INDEX_GLB_GPIO_Set] = (uint32_t)GLB_GPIO_Set, + [ROM_API_INDEX_GLB_GPIO_Clr] = (uint32_t)GLB_GPIO_Clr, + [ROM_API_INDEX_GLB_GPIO_IntMask] = (uint32_t)GLB_GPIO_IntMask, + [ROM_API_INDEX_GLB_Clr_GPIO_IntStatus] = (uint32_t)GLB_Clr_GPIO_IntStatus, + [ROM_API_INDEX_GLB_Get_GPIO_IntStatus] = (uint32_t)GLB_Get_GPIO_IntStatus, + [ROM_API_INDEX_GLB_GPIO_Int_Init] = (uint32_t)GLB_GPIO_Int_Init, + + [ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter, + [ROM_API_INDEX_HBN_GPIO_Wakeup_Set] = (uint32_t)HBN_GPIO_Wakeup_Set, + [ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash, + [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable, + [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset, + [ROM_API_INDEX_HBN_App_Reset] = (uint32_t)HBN_App_Reset, + [ROM_API_INDEX_HBN_Disable] = (uint32_t)HBN_Disable, + [ROM_API_INDEX_HBN_Get_BOR_OUT_State] = (uint32_t)HBN_Get_BOR_OUT_State, + [ROM_API_INDEX_HBN_Set_BOR_Config] = (uint32_t)HBN_Set_BOR_Config, + [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout] = (uint32_t)HBN_Set_Ldo11_Soc_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_All_Vout] = (uint32_t)HBN_Set_Ldo11_All_Vout, + [ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel, + [ROM_API_INDEX_HBN_Set_UART_CLK_Sel] = (uint32_t)HBN_Set_UART_CLK_Sel, + [ROM_API_INDEX_HBN_Set_XCLK_CLK_Sel] = (uint32_t)HBN_Set_XCLK_CLK_Sel, + [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel, + [ROM_API_INDEX_HBN_Set_HRAM_slp] = (uint32_t)HBN_Set_HRAM_slp, + [ROM_API_INDEX_HBN_Set_HRAM_Ret] = (uint32_t)HBN_Set_HRAM_Ret, + [ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K, + [ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K, + [ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K, + [ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K, + [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K, + [ROM_API_INDEX_HBN_Get_Status_Flag] = (uint32_t)HBN_Get_Status_Flag, + [ROM_API_INDEX_HBN_Set_Status_Flag] = (uint32_t)HBN_Set_Status_Flag, + [ROM_API_INDEX_HBN_Get_Wakeup_Addr] = (uint32_t)HBN_Get_Wakeup_Addr, + [ROM_API_INDEX_HBN_Set_Wakeup_Addr] = (uint32_t)HBN_Set_Wakeup_Addr, + [ROM_API_INDEX_HBN_Get_User_Boot_Config] = (uint32_t)HBN_Get_User_Boot_Config, + [ROM_API_INDEX_HBN_Set_User_Boot_Config] = (uint32_t)HBN_Set_User_Boot_Config, + [ROM_API_INDEX_HBN_Clear_RTC_Counter] = (uint32_t)HBN_Clear_RTC_Counter, + [ROM_API_INDEX_HBN_Enable_RTC_Counter] = (uint32_t)HBN_Enable_RTC_Counter, + [ROM_API_INDEX_HBN_Set_RTC_Timer] = (uint32_t)HBN_Set_RTC_Timer, + [ROM_API_INDEX_HBN_Get_RTC_Timer_Val] = (uint32_t)HBN_Get_RTC_Timer_Val, + [ROM_API_INDEX_HBN_Clear_RTC_INT] = (uint32_t)HBN_Clear_RTC_INT, + [ROM_API_INDEX_HBN_GPIO_INT_Enable] = (uint32_t)HBN_GPIO_INT_Enable, + [ROM_API_INDEX_HBN_GPIO_INT_Disable] = (uint32_t)HBN_GPIO_INT_Disable, + [ROM_API_INDEX_HBN_Get_INT_State] = (uint32_t)HBN_Get_INT_State, + [ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode] = (uint32_t)HBN_Get_Pin_Wakeup_Mode, + [ROM_API_INDEX_HBN_Clear_IRQ] = (uint32_t)HBN_Clear_IRQ, + [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg, + [ROM_API_INDEX_HBN_Comm_Pad_Wakeup_En_Cfg] = (uint32_t)HBN_Comm_Pad_Wakeup_En_Cfg, + [ROM_API_INDEX_HBN_Aon_Pad_IeSmt_Cfg] = (uint32_t)HBN_Aon_Pad_IeSmt_Cfg, + [ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask, + [ROM_API_INDEX_HBN_Enable_AComp0_IRQ] = (uint32_t)HBN_Enable_AComp0_IRQ, + [ROM_API_INDEX_HBN_Disable_AComp0_IRQ] = (uint32_t)HBN_Disable_AComp0_IRQ, + [ROM_API_INDEX_HBN_Enable_AComp1_IRQ] = (uint32_t)HBN_Enable_AComp1_IRQ, + [ROM_API_INDEX_HBN_Disable_AComp1_IRQ] = (uint32_t)HBN_Disable_AComp1_IRQ, + [ROM_API_INDEX_HBN_Enable_BOR_IRQ] = (uint32_t)HBN_Enable_BOR_IRQ, + [ROM_API_INDEX_HBN_Disable_BOR_IRQ] = (uint32_t)HBN_Disable_BOR_IRQ, + [ROM_API_INDEX_HBN_Get_Reset_Event] = (uint32_t)HBN_Get_Reset_Event, + [ROM_API_INDEX_HBN_Clear_Reset_Event] = (uint32_t)HBN_Clear_Reset_Event, + [ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO_Dbg_Pull_Cfg, + [ROM_API_INDEX_HBN_Set_BOR_Cfg] = (uint32_t)HBN_Set_BOR_Cfg, + + [ROM_API_INDEX_L1C_Cache_Write_Set] = (uint32_t)L1C_Cache_Write_Set, + [ROM_API_INDEX_L1C_Cache_Enable_Set] = (uint32_t)L1C_Cache_Enable_Set, + [ROM_API_INDEX_L1C_Cache_Flush] = (uint32_t)L1C_Cache_Flush, + [ROM_API_INDEX_L1C_Cache_Hit_Count_Get] = (uint32_t)L1C_Cache_Hit_Count_Get, + [ROM_API_INDEX_L1C_Cache_Miss_Count_Get] = (uint32_t)L1C_Cache_Miss_Count_Get, + [ROM_API_INDEX_L1C_Cache_Read_Disable] = (uint32_t)L1C_Cache_Read_Disable, + [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap, + [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable, + [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set, + [ROM_API_INDEX_L1C_BMX_Init] = (uint32_t)L1C_BMX_Init, + [ROM_API_INDEX_L1C_BMX_Addr_Monitor_Enable] = (uint32_t)L1C_BMX_Addr_Monitor_Enable, + [ROM_API_INDEX_L1C_BMX_Addr_Monitor_Disable] = (uint32_t)L1C_BMX_Addr_Monitor_Disable, + [ROM_API_INDEX_L1C_BMX_BusErrResponse_Enable] = (uint32_t)L1C_BMX_BusErrResponse_Enable, + [ROM_API_INDEX_L1C_BMX_BusErrResponse_Disable] = (uint32_t)L1C_BMX_BusErrResponse_Disable, + [ROM_API_INDEX_L1C_BMX_Get_Status] = (uint32_t)L1C_BMX_Get_Status, + [ROM_API_INDEX_L1C_BMX_Get_Err_Addr] = (uint32_t)L1C_BMX_Get_Err_Addr, + + [ROM_API_INDEX_PDS_Set_GPIO_Pad_Cfg] = (uint32_t)PDS_Set_GPIO_Pad_Cfg, + [ROM_API_INDEX_PDS_GPIO_Write] = (uint32_t)PDS_GPIO_Write, + [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask] = (uint32_t)PDS_Set_GPIO_Pad_IntMask, + [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode] = (uint32_t)PDS_Set_GPIO_Pad_IntMode, + [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr] = (uint32_t)PDS_Set_GPIO_Pad_IntClr, + [ROM_API_INDEX_PDS_Set_All_GPIO_IntClear] = (uint32_t)PDS_Set_All_GPIO_IntClear, + [ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus] = (uint32_t)PDS_Get_GPIO_Pad_IntStatus, + [ROM_API_INDEX_PDS_Disable_GPIO_Keep] = (uint32_t)PDS_Disable_GPIO_Keep, + [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable, + [ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config, + [ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config, + [ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config, + [ROM_API_INDEX_PDS_Wakeup_Src_En] = (uint32_t)PDS_Wakeup_Src_En, + [ROM_API_INDEX_PDS_Get_Wakeup_Src] = (uint32_t)PDS_Get_Wakeup_Src, + [ROM_API_INDEX_PDS_IntMask] = (uint32_t)PDS_IntMask, + [ROM_API_INDEX_PDS_Get_IntStatus] = (uint32_t)PDS_Get_IntStatus, + [ROM_API_INDEX_PDS_IntClear] = (uint32_t)PDS_IntClear, + [ROM_API_INDEX_PDS_Get_PdsRfStstus] = (uint32_t)PDS_Get_PdsRfStstus, + [ROM_API_INDEX_PDS_Get_PdsStstus] = (uint32_t)PDS_Get_PdsStstus, + [ROM_API_INDEX_PDS_Clear_Reset_Event] = (uint32_t)PDS_Clear_Reset_Event, + [ROM_API_INDEX_PDS_Get_Reset_Event] = (uint32_t)PDS_Get_Reset_Event, + [ROM_API_INDEX_PDS_Auto_Enable] = (uint32_t)PDS_Auto_Enable, + [ROM_API_INDEX_PDS_Manual_Force_Turn_Off] = (uint32_t)PDS_Manual_Force_Turn_Off, + [ROM_API_INDEX_PDS_Manual_Force_Turn_On] = (uint32_t)PDS_Manual_Force_Turn_On, + [ROM_API_INDEX_PDS_Set_KYD_Matrix_Size] = (uint32_t)PDS_Set_KYD_Matrix_Size, + [ROM_API_INDEX_PDS_Set_KYD_Col_Value] = (uint32_t)PDS_Set_KYD_Col_Value, + [ROM_API_INDEX_PDS_Set_KYD_Row_Pull] = (uint32_t)PDS_Set_KYD_Row_Pull, + [ROM_API_INDEX_PDS_Set_KYD_Wakeup_En] = (uint32_t)PDS_Set_KYD_Wakeup_En, + + [ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Internal_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock, + [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify, + [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable, + [ROM_API_INDEX_SF_Ctrl_Psram_Init] = (uint32_t)SF_Ctrl_Psram_Init, + [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Cmds_Set] = (uint32_t)SF_Ctrl_Cmds_Set, + [ROM_API_INDEX_SF_Ctrl_Burst_Toggle_Set] = (uint32_t)SF_Ctrl_Burst_Toggle_Set, + [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad, + [ROM_API_INDEX_SF_Ctrl_Select_Bank] = (uint32_t)SF_Ctrl_Select_Bank, + [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner, + [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable, + [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd, + [ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set] = (uint32_t)SF_Ctrl_Flash_Read_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Write_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Read_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState, + + [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init, + [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode, + [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg, + [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg, + [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Clear_Status_Register] = (uint32_t)SFlash_Clear_Status_Register, + [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy, + [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable, + [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable, + [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable, + [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase, + [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase, + [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase, + [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase, + [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase, + [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program, + [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId, + [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId, + [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId, + [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown, + [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown, + [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown, + [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap, + [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap, + [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset, + [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read, + [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg, + [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable, + [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read, + + [ROM_API_INDEX_UART_SetBaudRate] = (uint32_t)UART_SetBaudRate, + [ROM_API_INDEX_UART_Init] = (uint32_t)UART_Init, + [ROM_API_INDEX_UART_DeInit] = (uint32_t)UART_DeInit, + [ROM_API_INDEX_UART_FifoConfig] = (uint32_t)UART_FifoConfig, + [ROM_API_INDEX_UART_Enable] = (uint32_t)UART_Enable, + [ROM_API_INDEX_UART_Disable] = (uint32_t)UART_Disable, + [ROM_API_INDEX_UART_SetTxDataLength] = (uint32_t)UART_SetTxDataLength, + [ROM_API_INDEX_UART_SetRxDataLength] = (uint32_t)UART_SetRxDataLength, + [ROM_API_INDEX_UART_SetRxTimeoutValue] = (uint32_t)UART_SetRxTimeoutValue, + [ROM_API_INDEX_UART_SetRxByteCount] = (uint32_t)UART_SetRxByteCount, + [ROM_API_INDEX_UART_SetDeglitchCount] = (uint32_t)UART_SetDeglitchCount, + [ROM_API_INDEX_UART_ApplyAbrResult] = (uint32_t)UART_ApplyAbrResult, + [ROM_API_INDEX_UART_SetRtsValue] = (uint32_t)UART_SetRtsValue, + [ROM_API_INDEX_UART_ClrRtsValue] = (uint32_t)UART_ClrRtsValue, + [ROM_API_INDEX_UART_SetTxValue] = (uint32_t)UART_SetTxValue, + [ROM_API_INDEX_UART_ClrTxValue] = (uint32_t)UART_ClrTxValue, + [ROM_API_INDEX_UART_TxFreeRun] = (uint32_t)UART_TxFreeRun, + [ROM_API_INDEX_UART_AutoBaudDetection] = (uint32_t)UART_AutoBaudDetection, + [ROM_API_INDEX_UART_SetAllowableError0X55] = (uint32_t)UART_SetAllowableError0X55, + [ROM_API_INDEX_UART_GetBitWidth0X55] = (uint32_t)UART_GetBitWidth0X55, + [ROM_API_INDEX_UART_SetRS485] = (uint32_t)UART_SetRS485, + [ROM_API_INDEX_UART_TxFifoClear] = (uint32_t)UART_TxFifoClear, + [ROM_API_INDEX_UART_RxFifoClear] = (uint32_t)UART_RxFifoClear, + [ROM_API_INDEX_UART_IntMask] = (uint32_t)UART_IntMask, + [ROM_API_INDEX_UART_IntClear] = (uint32_t)UART_IntClear, + [ROM_API_INDEX_UART_SendData] = (uint32_t)UART_SendData, + [ROM_API_INDEX_UART_SendDataBlock] = (uint32_t)UART_SendDataBlock, + [ROM_API_INDEX_UART_ReceiveData] = (uint32_t)UART_ReceiveData, + [ROM_API_INDEX_UART_GetAutoBaudCount] = (uint32_t)UART_GetAutoBaudCount, + [ROM_API_INDEX_UART_GetRxByteCount] = (uint32_t)UART_GetRxByteCount, + [ROM_API_INDEX_UART_GetTxFifoCount] = (uint32_t)UART_GetTxFifoCount, + [ROM_API_INDEX_UART_GetRxFifoCount] = (uint32_t)UART_GetRxFifoCount, + [ROM_API_INDEX_UART_GetIntStatus] = (uint32_t)UART_GetIntStatus, + [ROM_API_INDEX_UART_GetTxBusBusyStatus] = (uint32_t)UART_GetTxBusBusyStatus, + [ROM_API_INDEX_UART_GetRxBusBusyStatus] = (uint32_t)UART_GetRxBusBusyStatus, + [ROM_API_INDEX_UART_GetOverflowStatus] = (uint32_t)UART_GetOverflowStatus, + + [ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter, + [ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit, + [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save, + [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore, + [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Clear_Status_Register_Need_Lock]= (uint32_t)XIP_SFlash_Clear_Status_Register_Need_Lock, + + [ROM_API_INDEX_IR_TxInit] = (uint32_t)IR_TxInit, + [ROM_API_INDEX_IR_TxPulseWidthConfig] = (uint32_t)IR_TxPulseWidthConfig, + [ROM_API_INDEX_IR_FifoConfig] = (uint32_t)IR_FifoConfig, + [ROM_API_INDEX_IR_DeInit] = (uint32_t)IR_DeInit, + [ROM_API_INDEX_IR_Enable] = (uint32_t)IR_Enable, + [ROM_API_INDEX_IR_Disable] = (uint32_t)IR_Disable, + [ROM_API_INDEX_IR_TxSWM] = (uint32_t)IR_TxSWM, + [ROM_API_INDEX_IR_TxFifoClear] = (uint32_t)IR_TxFifoClear, + [ROM_API_INDEX_IR_SendData] = (uint32_t)IR_SendData, + [ROM_API_INDEX_IR_SWMSendData] = (uint32_t)IR_SWMSendData, + [ROM_API_INDEX_IR_SendCommand] = (uint32_t)IR_SendCommand, + [ROM_API_INDEX_IR_SWMSendCommand] = (uint32_t)IR_SWMSendCommand, + [ROM_API_INDEX_IR_SendNEC] = (uint32_t)IR_SendNEC, + [ROM_API_INDEX_IR_IntMask] = (uint32_t)IR_IntMask, + [ROM_API_INDEX_IR_ClrIntStatus] = (uint32_t)IR_ClrIntStatus, + [ROM_API_INDEX_IR_GetIntStatus] = (uint32_t)IR_GetIntStatus, + [ROM_API_INDEX_IR_GetFifoStatus] = (uint32_t)IR_GetFifoStatus, + [ROM_API_INDEX_IR_GetTxFifoCount] = (uint32_t)IR_GetTxFifoCount, + [ROM_API_INDEX_IR_LEDInit] = (uint32_t)IR_LEDInit, + [ROM_API_INDEX_IR_LEDSend] = (uint32_t)IR_LEDSend, + + [ROM_API_INDEX_KYS_Init] = (uint32_t)KYS_Init, + [ROM_API_INDEX_KYS_Enable] = (uint32_t)KYS_Enable, + [ROM_API_INDEX_KYS_Disable] = (uint32_t)KYS_Disable, + [ROM_API_INDEX_KYS_IntMask] = (uint32_t)KYS_IntMask, + [ROM_API_INDEX_KYS_IntClear] = (uint32_t)KYS_IntClear, + [ROM_API_INDEX_KYS_GetIntStatus] = (uint32_t)KYS_GetIntStatus, + [ROM_API_INDEX_KYS_Get_FIFO_Idx] = (uint32_t)KYS_Get_FIFO_Idx, + [ROM_API_INDEX_KYS_ReadKeyfifo] = (uint32_t)KYS_ReadKeyfifo, + + [ROM_API_INDEX_Psram_Init] = (uint32_t)Psram_Init, + [ROM_API_INDEX_Psram_ReadReg] = (uint32_t)Psram_ReadReg, + [ROM_API_INDEX_Psram_WriteReg] = (uint32_t)Psram_WriteReg, + [ROM_API_INDEX_Psram_SetDriveStrength] = (uint32_t)Psram_SetDriveStrength, + [ROM_API_INDEX_Psram_SetBurstWrap] = (uint32_t)Psram_SetBurstWrap, + [ROM_API_INDEX_Psram_ReadId] = (uint32_t)Psram_ReadId, + [ROM_API_INDEX_Psram_EnterQuadMode] = (uint32_t)Psram_EnterQuadMode, + [ROM_API_INDEX_Psram_ExitQuadMode] = (uint32_t)Psram_ExitQuadMode, + [ROM_API_INDEX_Psram_ToggleBurstLength] = (uint32_t)Psram_ToggleBurstLength, + [ROM_API_INDEX_Psram_SoftwareReset] = (uint32_t)Psram_SoftwareReset, + [ROM_API_INDEX_Psram_Set_IDbus_Cfg] = (uint32_t)Psram_Set_IDbus_Cfg, + [ROM_API_INDEX_Psram_Cache_Write_Set] = (uint32_t)Psram_Cache_Write_Set, + [ROM_API_INDEX_Psram_Write] = (uint32_t)Psram_Write, + [ROM_API_INDEX_Psram_Read] = (uint32_t)Psram_Read, + + [ROM_API_INDEX_TIMER_GetCompValue] = (uint32_t)TIMER_GetCompValue, + [ROM_API_INDEX_TIMER_SetCompValue] = (uint32_t)TIMER_SetCompValue, + [ROM_API_INDEX_TIMER_CompValueEffectImmediately] = (uint32_t)TIMER_CompValueEffectImmediately, + [ROM_API_INDEX_TIMER_GetCounterValue] = (uint32_t)TIMER_GetCounterValue, + [ROM_API_INDEX_TIMER_ResetCounterValue] = (uint32_t)TIMER_ResetCounterValue, + [ROM_API_INDEX_TIMER_GetMatchStatus] = (uint32_t)TIMER_GetMatchStatus, + [ROM_API_INDEX_TIMER_GetPreloadValue] = (uint32_t)TIMER_GetPreloadValue, + [ROM_API_INDEX_TIMER_SetPreloadValue] = (uint32_t)TIMER_SetPreloadValue, + [ROM_API_INDEX_TIMER_SetPreloadTrigSrc] = (uint32_t)TIMER_SetPreloadTrigSrc, + [ROM_API_INDEX_TIMER_SetCountMode] = (uint32_t)TIMER_SetCountMode, + [ROM_API_INDEX_TIMER_ClearIntStatus] = (uint32_t)TIMER_ClearIntStatus, + [ROM_API_INDEX_TIMER_Init] = (uint32_t)TIMER_Init, + [ROM_API_INDEX_TIMER_DeInit] = (uint32_t)TIMER_DeInit, + [ROM_API_INDEX_TIMER_Enable] = (uint32_t)TIMER_Enable, + [ROM_API_INDEX_TIMER_Disable] = (uint32_t)TIMER_Disable, + [ROM_API_INDEX_TIMER_IntMask] = (uint32_t)TIMER_IntMask, + [ROM_API_INDEX_TIMER_GPIOSetPolarity] = (uint32_t)TIMER_GPIOSetPolarity, + [ROM_API_INDEX_TIMER_CH0_SetMeasurePulseWidth] = (uint32_t)TIMER_CH0_SetMeasurePulseWidth, + [ROM_API_INDEX_TIMER_CH0_GetMeasurePulseWidth] = (uint32_t)TIMER_CH0_GetMeasurePulseWidth, + [ROM_API_INDEX_TIMER_ForceClockDivision] = (uint32_t)TIMER_ForceClockDivision, + + [ROM_API_INDEX_WDT_Set_Clock] = (uint32_t)WDT_Set_Clock, + [ROM_API_INDEX_WDT_GetMatchValue] = (uint32_t)WDT_GetMatchValue, + [ROM_API_INDEX_WDT_SetCompValue] = (uint32_t)WDT_SetCompValue, + [ROM_API_INDEX_WDT_CompValueEffectImmediately] = (uint32_t)WDT_CompValueEffectImmediately, + [ROM_API_INDEX_WDT_GetCounterValue] = (uint32_t)WDT_GetCounterValue, + [ROM_API_INDEX_WDT_ResetCounterValue] = (uint32_t)WDT_ResetCounterValue, + [ROM_API_INDEX_WDT_GetResetStatus] = (uint32_t)WDT_GetResetStatus, + [ROM_API_INDEX_WDT_ClearResetStatus] = (uint32_t)WDT_ClearResetStatus, + [ROM_API_INDEX_WDT_Enable] = (uint32_t)WDT_Enable, + [ROM_API_INDEX_WDT_Disable] = (uint32_t)WDT_Disable, + [ROM_API_INDEX_WDT_ForceClockDivision] = (uint32_t)WDT_ForceClockDivision, + [ROM_API_INDEX_WDT_IntMask] = (uint32_t)WDT_IntMask, + [ROM_API_INDEX_WDT_GPIOSetPolarity] = (uint32_t)WDT_GPIOSetPolarity, + + [ROM_API_INDEX_arch_memcpy] = (uint32_t)arch_memcpy, + [ROM_API_INDEX_arch_memcpy4] = (uint32_t)arch_memcpy4, + [ROM_API_INDEX_arch_memcpy_fast] = (uint32_t)arch_memcpy_fast, + [ROM_API_INDEX_arch_memset] = (uint32_t)arch_memset, + [ROM_API_INDEX_arch_memset4] = (uint32_t)arch_memset4, + [ROM_API_INDEX_arch_memcmp] = (uint32_t)arch_memcmp, + + [ROM_API_INDEX_memcopy_to_fifo] = (uint32_t)memcopy_to_fifo, + + [ROM_API_INDEX_fifocopy_to_mem] = (uint32_t)fifocopy_to_mem, + + [ROM_API_INDEX_BFLB_Soft_CRC32_Ex] = (uint32_t)BFLB_Soft_CRC32_Ex, + [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32, + + [ROM_API_INDEX_FUNC_EMPTY_START ... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef, +}; + + +/*@} end of group ROMDRIVER_Global_Variables */ + +/** @defgroup ROMDRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group ROMDRIVER_Private_FunctionDeclaration */ + +/** @defgroup ROMDRIVER_Private_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Functions */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER_COMMON */ + +/*@} end of group BL702L_Periph_Driver */ + + diff --git a/drivers/soc/bl702l/std/src/bl702l_tzc_sec.c b/drivers/soc/bl702l/std/src/bl702l_tzc_sec.c new file mode 100644 index 000000000..9a4b5c192 --- /dev/null +++ b/drivers/soc/bl702l/std/src/bl702l_tzc_sec.c @@ -0,0 +1,237 @@ +/** + ****************************************************************************** + * @file bl702l_tzc_sec.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "string.h" +#include "bl702l_tzc_sec.h" + +/** @addtogroup BL702L_Peripheral_Driver + * @{ + */ + +/** @addtogroup TZC_SEC + * @{ + */ + +/** @defgroup TZC_SEC_Private_Macros + * @{ + */ + +/*@} end of group TZC_SEC_Private_Macros */ + +/** @defgroup TZC_SEC_Private_Types + * @{ + */ + +/*@} end of group TZC_SEC_Private_Types */ + +/** @defgroup TZC_SEC_Private_Variables + * @{ + */ + +/*@} end of group TZC_SEC_Private_Variables */ + +/** @defgroup TZC_SEC_Global_Variables + * @{ + */ + +/*@} end of group TZC_SEC_Global_Variables */ + +/** @defgroup TZC_SEC_Private_Fun_Declaration + * @{ + */ + +/*@} end of group TZC_SEC_Private_Fun_Declaration */ + +/** @defgroup TZC_SEC_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief TZC Security boot set + * + * @param Val: 0 for security boot start, and 0xf for security boot finished + * + * @return None + * +*******************************************************************************/ +void TZC_Sboot_Set(uint8_t Val) +{ + uint32_t tmpVal; + + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, Val); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM0 R0 protect range + * + * @param start: Start address to protect + * @param length: length to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t length) +{ + uint32_t tmpVal; + uint32_t alignEnd = (start + length + 1023) & ~0x3FF; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_START, ((start >> 10) & 0xffff)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_END, ((alignEnd >> 10) & 0xffff) - 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM0 R1 protect range + * + * @param start: Start address to protect + * @param length: length to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t length) +{ + uint32_t tmpVal; + uint32_t alignEnd = (start + length + 1023) & ~0x3FF; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_START, ((start >> 10) & 0xffff)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_END, ((alignEnd >> 10) & 0xffff) - 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM1 R0 protect range + * + * @param start: Start address to protect + * @param length: length to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t length) +{ + uint32_t tmpVal; + uint32_t alignEnd = (start + length + 1023) & ~0x3FF; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_START, ((start >> 10) & 0xffff)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_END, ((alignEnd >> 10) & 0xffff) - 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/****************************************************************************/ /** + * @brief TZC Set ROM1 R1 protect range + * + * @param start: Start address to protect + * @param length: length to protect + * + * @return None + * +*******************************************************************************/ +void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t length) +{ + uint32_t tmpVal; + uint32_t alignEnd = (start + length + 1023) & ~0x3FF; + + /* Set Range */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_START, ((start >> 10) & 0xffff)); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_END, ((alignEnd >> 10) & 0xffff) - 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1, tmpVal); + + /* Enable */ + tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID0_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID1_EN, 0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_EN, 1); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_LOCK, 1); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal); +} + +/*@} end of group TZC_SEC_Public_Functions */ + +/*@} end of group TZC_SEC */ + +/*@} end of group BL702L_Peripheral_Driver */ diff --git a/drivers/soc/bl702l/std/startup/interrupt.c b/drivers/soc/bl702l/std/startup/interrupt.c new file mode 100644 index 000000000..0148af7c2 --- /dev/null +++ b/drivers/soc/bl702l/std/startup/interrupt.c @@ -0,0 +1,212 @@ +/** + * @file interrupt.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bflb_core.h" + +typedef void (*pFunc)(void); + +struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM]; + +extern void default_trap_handler(void); +extern void default_interrupt_handler(void); + +const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = { + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 3 */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 7 */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 11 */ + default_interrupt_handler, /* 12 */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* */ + default_interrupt_handler, /* 16 + 0 */ + default_interrupt_handler, /* 16 + 1 */ + default_interrupt_handler, /* 16 + 2 */ + default_interrupt_handler, /* 16 + 3 */ + default_interrupt_handler, /* 16 + 4 */ + default_interrupt_handler, /* 16 + 5 */ + default_interrupt_handler, /* 16 + 6 */ + default_interrupt_handler, /* 16 + 7 */ + default_interrupt_handler, /* 16 + 8 */ + default_interrupt_handler, /* 16 + 9 */ + default_interrupt_handler, /* 16 + 10 */ + default_interrupt_handler, /* 16 + 11 */ + default_interrupt_handler, /* 16 + 12 */ + default_interrupt_handler, /* 16 + 13 */ + default_interrupt_handler, /* 16 + 14 */ + default_interrupt_handler, /* 16 + 15 */ + default_interrupt_handler, /* 16 + 16 */ + default_interrupt_handler, /* 16 + 17 */ + default_interrupt_handler, /* 16 + 18 */ + default_interrupt_handler, /* 16 + 19 */ + default_interrupt_handler, /* 16 + 20 */ + default_interrupt_handler, /* 16 + 21 */ + default_interrupt_handler, /* 16 + 22 */ + default_interrupt_handler, /* 16 + 23 */ + default_interrupt_handler, /* 16 + 24 */ + default_interrupt_handler, /* 16 + 25 */ + default_interrupt_handler, /* 16 + 26 */ + default_interrupt_handler, /* 16 + 27 */ + default_interrupt_handler, /* 16 + 28 */ + default_interrupt_handler, /* 16 + 29 */ + default_interrupt_handler, /* 16 + 30 */ + default_interrupt_handler, /* 16 + 31 */ + default_interrupt_handler, /* 16 + 32 */ + default_interrupt_handler, /* 16 + 33 */ + default_interrupt_handler, /* 16 + 34 */ + default_interrupt_handler, /* 16 + 35 */ + default_interrupt_handler, /* 16 + 36 */ + default_interrupt_handler, /* 16 + 37 */ + default_interrupt_handler, /* 16 + 38 */ + default_interrupt_handler, /* 16 + 39 */ + default_interrupt_handler, /* 16 + 40 */ + default_interrupt_handler, /* 16 + 41 */ + default_interrupt_handler, /* 16 + 42 */ + default_interrupt_handler, /* 16 + 43 */ + default_interrupt_handler, /* 16 + 44 */ + default_interrupt_handler, /* 16 + 45 */ + default_interrupt_handler, /* 16 + 46 */ + default_interrupt_handler, /* 16 + 47 */ + default_interrupt_handler, /* 16 + 48 */ + default_interrupt_handler, /* 16 + 49 */ + default_interrupt_handler, /* 16 + 50 */ + default_interrupt_handler, /* 16 + 51 */ + default_interrupt_handler, /* 16 + 52 */ + default_interrupt_handler, /* 16 + 53 */ + default_interrupt_handler, /* 16 + 54 */ + default_interrupt_handler, /* 16 + 55 */ + default_interrupt_handler, /* 16 + 56 */ + default_interrupt_handler, /* 16 + 57 */ + default_interrupt_handler, /* 16 + 58 */ + default_interrupt_handler, /* 16 + 59 */ + default_interrupt_handler, /* 16 + 60 */ + default_interrupt_handler, /* 16 + 61 */ + default_interrupt_handler, /* 16 + 62 */ + default_interrupt_handler, /* 16 + 63 */ +}; + +void exception_entry(void) +{ + unsigned long cause; + unsigned long epc; + unsigned long tval; + + printf("exception_entry\r\n"); + + cause = READ_CSR(CSR_MCAUSE); + printf("mcause=%08x\r\n", (int)cause); + epc = READ_CSR(CSR_MEPC); + printf("mepc:%08x\r\n", (int)epc); + tval = READ_CSR(CSR_MTVAL); + printf("mtval:%08x\r\n", (int)tval); + + cause = (cause & 0x3ff); + + const char *mcause_str[] = { + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "RSVD", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "RSVD", + "Store/AMO page fault" + }; + + printf("%s\r\n", mcause_str[cause & 0xf]); + + if ((cause == 8) || (cause == 11)) { + epc += 4; + WRITE_CSR(CSR_MEPC, epc); + } else { + while (1) { +#ifdef CONFIG_COREDUMP + /* For stack check */ + extern uintptr_t __freertos_irq_stack_top; + + /* XXX change sp to irq stack base */ + __asm__ volatile("add sp, x0, %0" ::"r"(&__freertos_irq_stack_top)); + void bl_coredump_run(void); + bl_coredump_run(); +#endif + } + } +} + +void interrupt_entry(void) +{ + irq_callback handler; + void *arg; + volatile uint32_t mcause = 0UL; + uint32_t irq_num; + + mcause = READ_CSR(CSR_MCAUSE); + irq_num = mcause & 0x3FF; + + if (irq_num < CONFIG_IRQ_NUM) { + handler = g_irqvector[irq_num].handler; + arg = g_irqvector[irq_num].arg; + if (handler) { + handler(irq_num, arg); + } else { + } + } else { + } +} + +__attribute__((interrupt, aligned(64))) void default_trap_handler(void) +{ + exception_entry(); +} + +__attribute__((interrupt)) __attribute__((weak)) void default_interrupt_handler(void) +{ + __asm volatile("addi sp,sp,-8"); + __asm volatile("csrr a0,mcause"); + __asm volatile("csrr a1,mepc"); + __asm volatile("sw a0,4(sp)"); + __asm volatile("sw a1,0(sp)"); + __asm volatile("csrsi mstatus,8"); + interrupt_entry(); + __asm volatile("csrci mstatus,8"); + __asm volatile("lw a1,0(sp)"); + __asm volatile("lw a0,4(sp)"); + __asm volatile("csrw mepc,a1"); + __asm volatile("csrw mcause,a0"); + __asm volatile("addi sp,sp,8"); +} diff --git a/drivers/soc/bl702l/std/startup/start.S b/drivers/soc/bl702l/std/startup/start.S new file mode 100644 index 000000000..fd95ddbcc --- /dev/null +++ b/drivers/soc/bl702l/std/startup/start.S @@ -0,0 +1,96 @@ +/* Copyright 2018 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +#include + +/* This code executes before _start, which is contained inside the C library. + * In embedded systems we want to ensure that _enter, which contains the first + * code to be executed, can be loaded at a specific address. To enable this + * feature we provide the '.text.metal.init.enter' section, which is + * defined to have the first address being where execution should start. */ + .section .init + .global __start + .type __start, %function +__start: + .cfi_startproc + + /* Inform the debugger that there is nowhere to backtrace past _enter. */ + .cfi_undefined ra + + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled because + * it's not valid to obtain the address of any symbol without GP + * configured. The C environment might go ahead and do this again, but + * that's safe as it's a fixed register. */ +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* Disable global interrupt */ + csrci mstatus,8 + + /* Set up a simple trap vector to catch anything that goes wrong early in + * the boot process. */ + la t0, default_trap_handler + # /* enable CLIC Vectored mode */ + ori t0,t0,3 + csrw mtvec, t0 + /* enable chicken bit if core is bullet series*/ + la t0, __metal_chicken_bit + beqz t0, 1f + csrwi 0x7C1, 0 +1: + + /* There may be pre-initialization routines inside the MBI code that run in + * C, so here we set up a C environment. First we set up a stack pointer, + * which is left as a weak reference in order to allow initialization + * routines that do not need a stack to be set up to transparently be + * called. */ + .weak __StackTop + la sp, __StackTop + + /* Intial the mtvt, MUST BE 64 bytes aligned*/ + .weak __Vectors + la t0, __Vectors + csrw mtvt, t0 + +#ifdef __riscv_float_abi_single + /* deal with FP */ + /* Is F extension present? */ + csrr t0, misa + andi t0, t0, (1 << ('F' - 'A')) + beqz t0, 1f + /* If so, enable it */ + li t0, MSTATUS_FS + csrs mstatus, t0 + fssr x0 +1: +#endif + + /* Check for an initialization routine and call it if one exists, otherwise + * just skip over the call entirely. Note that __metal_initialize isn't + * actually a full C function, as it doesn't end up with the .bss or .data + * segments having been initialized. This is done to avoid putting a + * burden on systems that can be initialized without having a C environment + * set up. */ + call SystemInit + + /* start load code to itcm like. */ + call start_load + + call System_Post_Init + + /* At this point we can enter the C runtime's startup file. The arguments + * to this function are designed to match those provided to the SEE, just + * so we don't have to write another ABI. */ + csrr a0, mhartid + li a1, 0 + li a2, 0 + call main + + csrci mstatus, (1 << 3) + +__exit: + j __exit + + .cfi_endproc diff --git a/drivers/soc/bl702l/std/startup/start_load.c b/drivers/soc/bl702l/std/startup/start_load.c new file mode 100644 index 000000000..1bc8d9247 --- /dev/null +++ b/drivers/soc/bl702l/std/startup/start_load.c @@ -0,0 +1,114 @@ +/** + * @file start_load.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include + +#define __STARTUP_CLEAR_BSS 1 + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __itcm_load_addr; +extern uint32_t __dtcm_load_addr; +extern uint32_t __system_ram_load_addr; +extern uint32_t __ram_load_addr; + +extern uint32_t __text_code_start__; +extern uint32_t __text_code_end__; +extern uint32_t __tcm_code_start__; +extern uint32_t __tcm_code_end__; +extern uint32_t __tcm_data_start__; +extern uint32_t __tcm_data_end__; +extern uint32_t __system_ram_data_start__; +extern uint32_t __system_ram_data_end__; +extern uint32_t __ram_data_start__; +extern uint32_t __ram_data_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __noinit_data_start__; +extern uint32_t __noinit_data_end__; + +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +extern uint32_t __HeapBase; +extern uint32_t __HeapLimit; + +//extern uint32_t __copy_table_start__; +//extern uint32_t __copy_table_end__; +//extern uint32_t __zero_table_start__; +//extern uint32_t __zero_table_end__; + +void start_load(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + + /* Copy ITCM code */ + pSrc = &__itcm_load_addr; + pDest = &__tcm_code_start__; + + for (; pDest < &__tcm_code_end__;) { + *pDest++ = *pSrc++; + } + + /* Copy DTCM code */ + pSrc = &__dtcm_load_addr; + pDest = &__tcm_data_start__; + + for (; pDest < &__tcm_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add system RAM data copy */ + pSrc = &__system_ram_load_addr; + pDest = &__system_ram_data_start__; + + for (; pDest < &__system_ram_data_end__;) { + *pDest++ = *pSrc++; + } + + /* BF Add OCARAM data copy */ + pSrc = &__ram_load_addr; + pDest = &__ram_data_start__; + + for (; pDest < &__ram_data_end__;) { + *pDest++ = *pSrc++; + } + +#ifdef __STARTUP_CLEAR_BSS + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for (; pDest < &__bss_end__;) { + *pDest++ = 0ul; + } + +#endif +} \ No newline at end of file diff --git a/drivers/soc/bl702l/std/startup/system_bl702l.c b/drivers/soc/bl702l/std/startup/system_bl702l.c new file mode 100644 index 000000000..3b11d0087 --- /dev/null +++ b/drivers/soc/bl702l/std/startup/system_bl702l.c @@ -0,0 +1,80 @@ +/** + * @file system_bl702.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "bl702l_glb.h" +#include + +void SystemInit(void) +{ + uint32_t *p; + uint8_t i; + uint32_t tmpVal = 0; + + /* global IRQ disable */ + __disable_irq(); + + tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); + tmpVal |= (1 << 8); /*mask pds wakeup*/ + tmpVal |= (1 << 10); /*mask rf done*/ + tmpVal |= (1 << 11); /*mask pll done*/ + tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/ + BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); + + /* GLB_Set_EM_Sel(GLB_EM_0KB); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + /* Restore default setting*/ + /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */ + // tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE + // BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + /* CLear all interrupt */ + p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff); + + /* init bor for all platform */ + // HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ }; + // HBN_Set_BOR_Cfg(&borCfg); +} + +void System_Post_Init(void) +{ + GLB_Trim_RC32M(); + HBN_Trim_RC32K(); + GLB_GPIO_O_Latch_Mode_Set(1); + /* global IRQ enable */ + __enable_irq(); +} \ No newline at end of file