FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
| We held the First FireSim and Chipyard User/Developer Workshop at ASPLOS 2023 on March 26, 2023! This workshop featured a full-day of talks from users and developers in the FireSim and Chipyard community. YouTube videos of the talks are available on the 2023 Workshop Page! |
|---|
- Using FireSim
- What is FireSim?
- What can I simulate with FireSim?
- Need help?
- Contributing
- Publications
To get started with FireSim, you can find our extensive documentation and getting-started guide at docs.fires.im. The FireSim codebase is open-source at github.com/firesim/firesim and we welcome pull requests and issues. You can also get help from the FireSim user community on our User Forum. Additionally, we frequently run tutorials at various conferences and events; for overview purposes, you can find the most recent slide decks at fires.im/tutorial-recent (you should still follow docs.fires.im for the most up to date getting-started guide).
Another good overview from a recent event (in video format) can be found on YouTube.
FireSim is an open-source FPGA-accelerated full-system hardware simulation platform that makes it easy to validate, profile, and debug RTL hardware implementations at 10s to 100s of MHz. FireSim simplifies co-simulating ASIC RTL with cycle-accurate hardware and software models for other system components (e.g. I/Os). FireSim can productively scale from individual SoC simulations hosted on on-prem FPGAs (e.g., a single Xilinx Alveo board attached to a desktop) to massive datacenter-scale simulations harnessing hundreds of cloud FPGAs (e.g., on Amazon EC2 F1).
Who's using and developing FireSim? FireSim users across academia and industry (at 20+ institutions) have published over 40 papers using FireSim in many areas, including computer architecture, systems, networking, security, scientific computing, circuits, design automation, and more (see the Publications page). FireSim has also been used in the development of shipping commercial silicon. FireSim was originally developed in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley, but now has industrial and academic contributors from all over the world.
You can learn more about FireSim in the following places:
- FireSim website: https://fires.im
- FireSim ISCA 2018 Paper: Paper PDF | IEEE Xplore | ACM DL | BibTeX | Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”.
- FireSim ISCA-50 Retrospective: Paper PDF
- FireSim documentation: https://docs.fires.im
- Scala API Documentation: https://fires.im/firesim/latest/api/
- LatchUp 2023 Update Talk: YouTube
- FireSim (+Chipyard) Tutorial: https://fires.im/tutorial-recent/
- ASPLOS 2023 Tutorial Videos: YouTube Playlist
- Updates/News: Changelog | FireSim Blog | Twitter
FireSim can simulate arbitrary hardware designs written in Chisel or Verilog. With FireSim, users can write their own RTL (processors, accelerators, etc.) and run it at near-FPGA-prototype speeds on cloud or on-prem FPGAs, while obtaining performance results that match an ASIC implementation of the same design. Depending on the hardware design and the simulation scale, FireSim simulations run at 10s to 100s of MHz. Users can also integrate custom software models for components that they don't need or want to write as RTL. To help construct a closed and deterministic simulated environment around a design, FireSim includes validated and high-performance HW/SW models for I/Os like DRAM, Ethernet, Disks, UART, and more. The User Publications page links to a selection of papers written by FireSim users.
FireSim was originally developed to simulate datacenters by combining open RTL for RISC-V processors with a custom cycle-accurate network simulation. By default, FireSim provides all the RTL and models necessary to cycle-exactly simulate from one to thousands of multi-core compute nodes, derived directly from silicon-proven and open target-RTL (RISC-V Rocket Chip, BOOM, and Chipyard), with an optional cycle-accurate network simulation tying them together. FireSim also provides a Linux distribution that is compatible with the RISC-V systems it simulates and automates the process of including new workloads into this Linux distribution. These simulations run fast enough to interact with Linux on the simulated system at the command line, like a real computer. Users can even SSH into simulated systems in FireSim and access the Internet from within them.
Head to the FireSim Website to learn more.
- Join the FireSim Mailing list: https://groups.google.com/forum/#!forum/firesim
- Post an issue on this repo
- Follow on Twitter for project updates: @firesimproject
- See CONTRIBUTING.md
You can learn more about FireSim in our ISCA 2018 paper, which covers the overall FireSim infrastructure and large distributed simulations of networked clusters. This paper was selected as one of IEEE Micro’s "Top Picks from Computer Architecture Conferences, 2018" and for "ISCA@50 25-year Retrospective 1996-2020".
Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. In proceedings of the 45th International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.
Paper PDF | IEEE Xplore | ACM DL | BibTeX
Our paper from FPGA 2019 details the DRAM model used in FireSim:
David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović, FASED: FPGA-Accelerated Simulation and Evaluation of DRAM, In proceedings of the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2018.
IEEE Micro Top Picks of 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud
This article discusses several updates since the FireSim ISCA 2018 paper:
Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. IEEE Micro, vol. 39, no. 3, pp. 56-65, (Micro Top Picks 2018 Issue). May-June 2019.
Our paper describing FireSim's Compiler, Golden Gate:
Albert Magyar, David T. Biancolin, Jack Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanović, Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes, In proceedings of the 39th International Conference on Computer-Aided Design (ICCAD '19), Westminster, CO, November 2019.
ASPLOS 2020: FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design
Our paper that discusses system-level profiling features in FireSim:
Sagar Karandikar, Albert Ou, Alon Amid, Howard Mao, Randy Katz, Borivoje Nikolić, and Krste Asanović, FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design, In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), Lausanne, Switzerland, March 2020.
In this special issue, we describe the automated instance-multithreading optimization and support for multiple clock domains in the simulated target.
David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolić, Jonathan Bachrach, Krste Asanović. Accessible, FPGA Resource-Optimized Simulation of Multi-Clock Systems in FireSim. In IEEE Micro Volume: 41, Issue: 4, July-Aug. 1 2021
ISCA@50 Retrospective: 1996-2020: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
This retrospective paper, included in the "ISCA@50 Retrospective: 1996-2020" collection, provides an update and retrospective on FireSim's development and evolution since the original ISCA 2018 paper.
Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. In ISCA@50 Retrospective: 1996-2020, Edited by José F. Martínez and Lizy K. John, June 2023.
Our paper from ISCA 2024 explains how the FireSim compiler can partition the design across multiple FPGAs to simulate scale-up SoC designs.
Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolić, Yakun Sophia Shao, and Krste Asanović, “FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs”, To appear, In Proceedings of the 51th ACM/IEEE International Symposium on Computer Architecture (ISCA 2024), Buenos Aires, Argentina, June 2024.
You can find other publications, including publications that use FireSim on the FireSim Website.