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Problems with access information for some TriCore operands #2526

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imbillow opened this issue Oct 26, 2024 · 3 comments
Open

Problems with access information for some TriCore operands #2526

imbillow opened this issue Oct 26, 2024 · 3 comments
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bug Testing Test related issue TriCore Arch

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@imbillow
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imbillow commented Oct 26, 2024

Originally posted by @Rot127 in #2523 (review)

Need to fix all fixme in tests/details/tricore.yaml

@imbillow
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imbillow commented Oct 26, 2024

Also note that when an operand of type TRICORE_OP_MEM is written, the access information is wrong.

Maybe need to construct a new Operand Class in the td file to fix this?

@Rot127
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Rot127 commented Oct 26, 2024

Maybe need to construct a new Operand Class in the td file to fix this?

Yeah, this would be the way. Also we would need to mark all store/load instructions with mayLoad = 1 or mayStore = 1. The mapping table generator will add the read/write details for iPtr operands. So making the registers and immediate values of type iPtr might be even enough.

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Rot127 commented Nov 10, 2024

You can also add supplement information to the TriCore tables. Like here.
It assumes that there is only a single memory operand (hopefully true for TriCore) and the mayStore, mayLoad attributes are set correctly. FIxing mayLoad, mauStore ins the TriCore files is way easier then changing operands.

Then you assign this access value whenever a memory operand is created.

@Rot127 Rot127 added bug TriCore Arch Testing Test related issue labels Nov 10, 2024
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Labels
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