[BPF] Update the BPF arch to match the current specification

[Roeegg2]

Feature

• New architecture module
• Support for processor extension
• Add more instruction details (elaborated below)
• Binding support for: language
• Other (elaborated below)

Describe the feature you'd like
Update the BPF architecture to the current specification

Additional context

• Add JUMP32 instruction class
• Add SDIV, SMOD, MOVSX instructions
• Add ATOMIC instruction modifier
• Add XCHG and CMPXCHG instructions

I think that's everything that needs to be updated, but if you do find something I'm missing, please let me know.

[Roeegg2]

If it's OK I would love to implement that :)

[Rot127]

Sure, go ahead!

[Roeegg2]

Apparently since around 2019 eBPF programs can jump backwards in code too, so all of the branch instructions are invalid now too... (offset is interpreted as signed value instead of unsigned)
I suspect there are other similar major changes too.
Should we add an option for different major eBPF versions? So we can still support older programs.

[Rot127]

Quickly skimmed the kernel ISA and the RFC ISA. They seem to match. So you can change the bpf_op_mem::disp to be a 64bit field and cast it to what the instruction uses.