From d9b24b1f1fd42629b723c97d36ff1d05bb1f1a42 Mon Sep 17 00:00:00 2001
From: Porterlu <1258210724@qq.com>
Date: Fri, 16 Jun 2023 06:04:03 -0700
Subject: [PATCH] divide MSWI.scala to MSWI part and SWI part

---
 src/main/scala/devices/tilelink/CLINT.scala |  2 +-
 src/main/scala/devices/tilelink/MSWI.scala  | 31 +--------------
 src/main/scala/devices/tilelink/SWI.scala   | 42 +++++++++++++++++++++
 3 files changed, 44 insertions(+), 31 deletions(-)
 create mode 100644 src/main/scala/devices/tilelink/SWI.scala

diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala
index d847c47920f..9e9d0a05e0b 100644
--- a/src/main/scala/devices/tilelink/CLINT.scala
+++ b/src/main/scala/devices/tilelink/CLINT.scala
@@ -40,7 +40,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
         val mswiOpt = clintParams.mswi.map { params =>
           val tlbus = locateTLBusWrapper(p(MSWIAttachKey).slaveWhere)
           val beatBytes = tlbus.beatBytes
-          val mswi = LazyModule(new MSWI(params, MTIMERParams(MTIMEBaseAddress = params.BaseAddress + SWIConsts.size), clintParams.isACLINT, beatBytes))
+          val mswi = LazyModule(new MSWI(params, MTIMERParams(mtimeBaseAddress = params.baseAddress + SWIConsts.size), clintParams.isACLINT, beatBytes))
           mswi.node := tlbus.coupleTo("mswi") { TLFragmenter(tlbus) := _ }
 
           InModuleBody {
diff --git a/src/main/scala/devices/tilelink/MSWI.scala b/src/main/scala/devices/tilelink/MSWI.scala
index efb9fd967c8..a0756b5a9e6 100644
--- a/src/main/scala/devices/tilelink/MSWI.scala
+++ b/src/main/scala/devices/tilelink/MSWI.scala
@@ -12,19 +12,9 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 
-object SWIConsts
-{
-  def sipOffset(hart: Int) = hart * sipBytes
-  def sipBytes = 4
-  def size = 0x4000
-  def ipiWidth = 32
-  def ints = 1
-  def clintSize = 0x10000
-}
-
 case class MSWIParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
 {
-  def address = AddressSet(BaseAddress, SWIConsts.size - 1)
+  def address = AddressSet(baseAddress, SWIConsts.size - 1)
 }
 
 case class MSWIAttachParams(
@@ -119,22 +109,3 @@ class MSWI(mswiParams: MSWIParams, mtimerParams: MTIMERParams, isACLINT: Boolean
     node.regmap(mapping:_*)    
   }
 }
-
-object SWI {
-  def apply(mswiType: String, intnode: IntNexusNode, intStages: Int) = {
-    import SWIConsts._ 
-
-    val nTiles  = intnode.out.size
-    val ipi     = Seq.fill(nTiles) { RegInit(0.U(1.W)) }
-    
-    val (intnode_out, _) = intnode.out.unzip
-    intnode_out.zipWithIndex.foreach { case (int, i) =>
-      int(0) := ShiftRegister(ipi(i)(0), intStages)
-    }
-
-    val swiRegGroup = RegFieldGroup(mswiType + "sip", Some(mswiType.toUpperCase + "SIP Bits"), ipi.zipWithIndex.flatMap { case (r, i) => 
-      RegField(1, r, RegFieldDesc(mswiType + s"sip_$i", mswiType.toUpperCase + s"SIP bit for Hart $i", reset=Some(0))) :: RegField(SWIConsts.ipiWidth - 1) :: Nil })
-  
-    swiRegGroup
-  }
-}
\ No newline at end of file
diff --git a/src/main/scala/devices/tilelink/SWI.scala b/src/main/scala/devices/tilelink/SWI.scala
new file mode 100644
index 00000000000..ef670dc7709
--- /dev/null
+++ b/src/main/scala/devices/tilelink/SWI.scala
@@ -0,0 +1,42 @@
+// See LICENSE.SiFive for license details.
+  
+package freechips.rocketchip.devices.tilelink
+
+import chisel3._
+import chisel3.util.ShiftRegister
+import org.chipsalliance.cde.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
+object SWIConsts
+{
+  def sipOffset(hart: Int) = hart * sipBytes
+  def sipBytes = 4
+  def size = 0x4000
+  def ipiWidth = 32
+  def ints = 1
+  def clintSize = 0x10000
+}
+
+object SWI {
+  def apply(swiType: String, intnode: IntNexusNode, intStages: Int) = {
+    import SWIConsts._ 
+
+    val nTiles  = intnode.out.size
+    val ipi     = Seq.fill(nTiles) { RegInit(0.U(1.W)) }
+    
+    val (intnode_out, _) = intnode.out.unzip
+    intnode_out.zipWithIndex.foreach { case (int, i) =>
+      int(0) := ShiftRegister(ipi(i)(0), intStages)
+    }
+
+    val swiRegGroup = RegFieldGroup(swiType + "sip", Some(swiType.toUpperCase + "SIP Bits"), ipi.zipWithIndex.flatMap { case (r, i) => 
+      RegField(1, r, RegFieldDesc(swiType + s"sip_$i", swiType.toUpperCase + s"SIP bit for Hart $i", reset=Some(0))) :: RegField(SWIConsts.ipiWidth - 1) :: Nil })
+  
+    swiRegGroup
+  }
+}
\ No newline at end of file