From 41c0183c0774f48c02a13c2f875d284e88e38693 Mon Sep 17 00:00:00 2001 From: krk Date: Thu, 12 Dec 2024 13:52:55 +0000 Subject: [PATCH] Backport 3c60f0b2bb75150d49da9ab94d88b767275de5e2 --- src/hotspot/cpu/aarch64/register_aarch64.hpp | 8 +++++++- .../cpu/aarch64/vm_version_aarch64.cpp | 20 ++++++++++++++++--- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp index 5a152d62777..459e24639fd 100644 --- a/src/hotspot/cpu/aarch64/register_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.hpp @@ -140,7 +140,13 @@ class FloatRegisterImpl: public AbstractRegisterImpl { max_slots_per_register = 8, save_slots_per_register = 2, slots_per_neon_register = 4, - extra_save_slots_per_neon_register = slots_per_neon_register - save_slots_per_register + extra_save_slots_per_neon_register = slots_per_neon_register - save_slots_per_register, + neon_vl = 16, + // VLmax: The maximum sve vector length is determined by the hardware + // sve_vl_min <= VLmax <= sve_vl_max. + sve_vl_min = 16, + // Maximum supported vector length across all CPUs + sve_vl_max = 256 }; // construction diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index c5046582a61..0bba64e1f45 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -24,6 +24,7 @@ */ #include "precompiled.hpp" +#include "register_aarch64.hpp" #include "runtime/arguments.hpp" #include "runtime/globals_extension.hpp" #include "runtime/java.hpp" @@ -414,14 +415,27 @@ void VM_Version::initialize() { if (FLAG_IS_DEFAULT(UseSVE)) { FLAG_SET_DEFAULT(UseSVE, (_features & CPU_SVE2) ? 2 : 1); } - if (UseSVE > 0) { - _initial_sve_vector_length = get_current_sve_vector_length(); - } } else if (UseSVE > 0) { warning("UseSVE specified, but not supported on current CPU. Disabling SVE."); FLAG_SET_DEFAULT(UseSVE, 0); } + if (UseSVE > 0) { + int vl = get_current_sve_vector_length(); + if (vl < 0) { + warning("Unable to get SVE vector length on this system. " + "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning."); + FLAG_SET_DEFAULT(UseSVE, 0); + } else if ((vl == 0) || ((vl % FloatRegisterImpl::sve_vl_min) != 0) || !is_power_of_2(vl)) { + warning("Detected SVE vector length (%d) should be a power of two and a multiple of %d. " + "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.", + vl, FloatRegisterImpl::sve_vl_min); + FLAG_SET_DEFAULT(UseSVE, 0); + } else { + _initial_sve_vector_length = vl; + } + } + // This machine allows unaligned memory accesses if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { FLAG_SET_DEFAULT(UseUnalignedAccesses, true);