diff --git a/.github/workflows/installer.yml b/.github/workflows/installer.yml index b1ee89850..0dff54fe7 100644 --- a/.github/workflows/installer.yml +++ b/.github/workflows/installer.yml @@ -28,6 +28,8 @@ jobs: - cepheus - vayu-huaxing - vayu-tianma + # sm8250 + - lmi # sm8550 - fuxi # sm7325 diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 01eb4d79c..b505bb194 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -33,6 +33,7 @@ jobs: - guacamole - guacamoleb # sdm845 + - fajita - beryllium-ebbg - beryllium-tianma - polaris diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/DSDT.aml b/Platform/Xiaomi/sm8250/AcpiTables/lmi/DSDT.aml new file mode 100644 index 000000000..9fe87e834 Binary files /dev/null and b/Platform/Xiaomi/sm8250/AcpiTables/lmi/DSDT.aml differ diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/Dsdt.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Dsdt.asl new file mode 100644 index 000000000..dbe7b2285 --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Dsdt.asl @@ -0,0 +1,24 @@ +// +// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support. +// +DefinitionBlock("DSDT.AML", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3) +{ + Scope(\_SB_) { + + // Include("addSub.asl") + Include("dsdt_common.asl") + // Include("cust_dsdt.asl") + + // Include("usb.asl") + + // + // Buttons + // + // Include("cust_arraybutton.asl") + + // + // Bluetooth + // + // Include("wcnss_bt.asl") + } +} diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/Pep_lpi.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Pep_lpi.asl new file mode 100644 index 000000000..08364a758 --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Pep_lpi.asl @@ -0,0 +1,646 @@ +Device (SYSM) { + Name (_HID, "ACPI0010") + Name (_UID, 0x100000) + Name (_LPI, Package() + { + 0, // Version + 0x1000000, // Level ID + 1, // Count + + // DRIPS State - Xo Shutdown + Cx retention + AOSS Sleep + LLC deactivate + Package () { + 9500, // Min residency (us) + 6000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP. + 0, // Residency counter frequency + 0, // Enabled parent state + 0xB300, // Integer entry method PSCI E3 + F3 + LLC + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "platform.DRIPS" // Name + } + }) // End of _LPI + + + Device (CLUS) + { + Name (_HID, "ACPI0010") + Name (_UID, 0x10) + Name (_LPI, Package() + { + 0, // Version + 0x1000000, // Level ID + 2, // Count + + // State 0: D2 + Package () + { + 5900, // Min residency (us) + 3000, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + 0x20, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D2" // Name + }, + // State 1: D4 + Package () + { + 6000, // Min residency (us) + 3300, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Till F1) + 0x40, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D4" // Name + } + }) // End of _LPI + + + Device (CPU0) // Kryo Silver CPU0 < SYSM.CLUS.CPU0 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x0) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C4" // Name + } + + }) // End of _LPI + } // End of CPU0 + + Device (CPU1) // Kyro Silver CPU1 < SYSM.CLUS.CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x1) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C4" // Name + } + + }) // End of _LPI + } // End of CPU1 + + Device (CPU2) // Kyro Silver CPU2 < SYSM.CLUS.CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x2) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C4" // Name + } + + }) // End of _LPI + } // End of CPU2 + + Device (CPU3) // Kyro Silver CPU3 < SYSM.CLUS.CPU3 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x3) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C4" // Name + } + + }) // End of _LPI + } // End of CPU3 + + Device (CPU4) // Kryo Gold CPU0 < SYSM.CLUS.CPU4 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x4) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C4" // Name + } + }) // End of _LPI + } // End of CPU4 + + Device (CPU5) // Kryo Gold CPU1 < SYSM.CLUS.CPU5 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x5) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C4" // Name + } + }) // End of _LPI + } // End of CPU5 + + Device (CPU6) // Kryo Gold CPU2 < SYSM.CLUS.CPU6 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x6) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C4" // Name + } + }) // End of _LPI + } // End of CPU6 + + Device (CPU7) // Kryo Prime CPU0 < SYSM.CLUS.CPU7 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x7) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C2" // Name + }, + // C3 + Package () + { + 3990, // Min residency (us) + 1000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C3" // Name + }, + // C4 + Package () + { + 4490, // Min residency (us) + 1500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C4" // Name + } + }) // End of _LPI + } // End of CPU7 + } // End of CLUS +} // End of SYSM diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/dsdt_common.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/dsdt_common.asl new file mode 100644 index 000000000..b60b66782 --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/dsdt_common.asl @@ -0,0 +1,103 @@ +Name(SOID, 0xffffffff) // Holds the Chip Id +Name(STOR, 0x1) // Holds boot options 0 = nvme, 1 = ufs +Name(SIDS, "899800000000000") // Holds the Chip ID translated to a string +Name(SIDV, 0xffffffff) // Holds the Chip Version as (major<<16)|(minor&0xffff) +Name(SVMJ, 0xffff) // Holds the major Chip Version +Name(SVMI, 0xffff) // Holds the minor Chip Version +Name(SDFE, 0xffff) // Holds the Chip Family enum +Name(SFES, "899800000000000") // Holds the Chip Family translated to a string +Name(SIDM, 0xfffffffff) // Holds the Modem Support bit field +Name(SUFS, 0x0) // Holds secondary UFS enablement (1 = enabled) +Name(PUS3, 0x0) // Holds whether primary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SUS3, 0x0) // Holds whether secondary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SIDT, 0xffffffff) // Holds the Chip Tier value +Name(SJTG, 0xffffffff) // Holds the JTAG ID +Name(SOSN, 0xaaaaaaaabbbbbbbb) // Holds the Chip Serial Number +Name(PLST, 0xffffffff) // Holds the Device platform subtype +Name(EMUL, 0xffffffff) // Holds the Device emulation type +Name (RMTB, 0xaaaaaaaa) // Holds the RemoteFS shared memory base address +Name (RMTX, 0xbbbbbbbb) // Holds the RemoteFS shared memory length +Name (RFMB, 0xcccccccc) // Holds the RFSA MPSS shared memory base address +Name (RFMS, 0xdddddddd) // Holds the RFSA MPSS shared memory length +Name (RFAB, 0xeeeeeeee) // Holds the RFSA ADSP shared memory base address +Name (RFAS, 0x77777777) // Holds the RFSA ADSP shared memory length +Name (TCMA, 0xDEADBEEF) // Holds TrEE Carveout Memory Address +Name (TCML, 0xBEEFDEAD) // Holds TrEE Carveout Memory Length +Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib +Name (PRP1, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 1 present : 0x00000000 - PCIe root port 1 not present +Name (SKUV, 0x1) // Set SKU Version to 1 + +//Audio Drivers +// Include("audio.asl") + + // + // Storage - UFS/SD + // + Include("ufs.asl") + // Include("sdc.asl") // No SD support on polaris + + // + // ASL Bridge Device + // + // Include("abd.asl") + + Name (ESNL, 20) // Exsoc name limit 20 characters + Name (DBFL, 23) // buffer Length, should be ESNL+3 + +// +// PMIC driver +// +// Include("pmic_core.asl") + +// +// PMICTCC driver +// +// Include("pmic_batt.asl") + + // Include("pep.asl") + // Include("bam.asl") + // Include("buses.asl") + + // MPROC Drivers (PIL Driver and Subsystem Drivers) + // Include("win_mproc.asl") + // Include("syscache.asl") + // Include("HoyaSmmu.asl") + // Include("graphics.asl") + + // Include("SCM.asl"); + + // + // SPMI driver + // + // Include("spmi.asl") + + // + // TLMM controller. + // + // Include("qcgpio.asl") + + // Include("pcie.asl") + + // Include("cbsp_mproc.asl") + + // Include("adsprpc.asl") + + // + // RemoteFS + // + // Include("rfs.asl") + + // + // Qualcomm IPA + // Include("ipa.asl") + + // Include("gsi.asl") + + // Include("qcdb.asl") + + // copied from sm7325, need to check + Include("Pep_lpi.asl") + +// QUPV3 GPI device node and resources +// +// Include("qgpi.asl") diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/ufs.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/ufs.asl new file mode 100644 index 000000000..2672f59bf --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/ufs.asl @@ -0,0 +1,40 @@ +// UFS Controller +Device (UFS0) +{ + Method(_STA, 0) + { + Return (0xF) // Set to 0xF to enable + } + + Name (_HID, "QCOM24A5") + Alias(\_SB.EMUL, EMUL) + Name (_UID, 0) + // Check: Cache coherent? + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UFS register address space + Memory32Fixed (ReadWrite, 0x1D84000, 0x1C000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {297} + }) + Return (RBUF) + } + + // UFS Device + Device (DEV0) + { + // Memory Type + Method (_ADR) + { + Return (8) + } + + // Non-removable + Method (_RMV) + { + Return (0) + } + } +} diff --git a/Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb b/Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb new file mode 100644 index 000000000..567c0781c Binary files /dev/null and b/Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb differ diff --git a/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..5dac47198 --- /dev/null +++ b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,68 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { + /* Hypervisor seems needed for windows boot? */ + {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"RAM Partition", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"AOP", 0x80700000, 0x00160000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"XBL Log Buffer", 0x80880000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"Removed Mem", 0x80b00000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"PIL Reserved", 0x86200000, 0x05D00000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x9C000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"DBI Dump", 0x9E400000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + + {"RAM Partition", 0xA0000000, 0x10000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"PSTORE", 0xB0000000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0xB0190000, 0x0FE70000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + {"DXE Heap", 0xC0000000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + + {"RAM Partition", 0xD0000000,0x130000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + /* Other memory regions */ + {"IMEM Base", 0x14680000, 0x00040000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x146BF000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + /* Register regions */ + {"IPC_ROUTER_TOP", 0x00400000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_2_GSI", 0x00800000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x00900000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x00A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x00790000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TCSR_TCSR_REGS", 0x01FC0000, 0x00030000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x02C7D000, 0x00002000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x02C90000, 0x0000A000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_SSC_GSI", 0x05A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x08800000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x0A600000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB_RUMI", 0x0A720000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_SEC", 0x0A800000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"AOSS", 0x0B000000, 0x04000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x0F100000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x0F500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_NORTH", 0x0F900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_HM", 0x17800000, 0x0d981000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"Terminator", 0, 0, 0, 0, 0, 0, 0} +}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} diff --git a/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Platform/Xiaomi/sm8250/lmi.dsc b/Platform/Xiaomi/sm8250/lmi.dsc new file mode 100644 index 000000000..7040cab2a --- /dev/null +++ b/Platform/Xiaomi/sm8250/lmi.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = lmi + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8250/sm8250.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm8250/lmi.fdf.inc + +!include Platform/Qualcomm/sm8250/sm8250.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2400 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|420 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Poco F2" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"lmi" diff --git a/Platform/Xiaomi/sm8250/lmi.fdf.inc b/Platform/Xiaomi/sm8250/lmi.fdf.inc new file mode 100644 index 000000000..f72256396 --- /dev/null +++ b/Platform/Xiaomi/sm8250/lmi.fdf.inc @@ -0,0 +1,22 @@ +// per-device BSP DXEs +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8250/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/alioth/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Platform/Xiaomi/sm8250/AcpiTables/alioth/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Madt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Madt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Facp.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Gtdt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/bgrt.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob +FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb +} diff --git a/configs/devices/lmi.conf b/configs/devices/lmi.conf new file mode 100644 index 000000000..8223c396a --- /dev/null +++ b/configs/devices/lmi.conf @@ -0,0 +1,12 @@ +SOC_PLATFORM="SM8250" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="lmi" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-08" +BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 + +# ACPI config +SPLIT_DSDT=true +USE_IASL=true