From 1b1f5ff8b6fe25d0401b0fbe83df3bdc8dad8953 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 10 Aug 2023 16:39:26 +0300 Subject: [PATCH] update running cocotb tests from makefile and add cocotb to the CI and update documentation to run cocotb using makefile --- .github/workflows/user_project_ci.yml | 18 +++++---------- Makefile | 22 ++++++++++++++----- docs/source/index.rst | 15 +++++++++---- verilog/dv/cocotb/cocotb_tests.py | 8 +++---- .../README.md | 0 .../counter_la/counter_la.c | 0 .../counter_la/counter_la.py | 0 .../counter_la/counter_la.yaml | 0 .../counter_la_clk/counter_la_clk.c | 0 .../counter_la_clk/counter_la_clk.py | 15 +++++++++++++ .../counter_la_clk/counter_la_clk.yaml | 0 .../counter_la_reset/counter_la_reset.c | 0 .../counter_la_reset/counter_la_reset.py | 0 .../counter_la_reset/counter_la_reset.yaml | 0 .../counter_wb/counter_wb.c | 0 .../counter_wb/counter_wb.py | 0 .../counter_wb/counter_wb.yaml | 0 .../user_proj_tests.yaml} | 12 +++++----- .../user_proj_tests_gl.yaml} | 0 19 files changed, 56 insertions(+), 34 deletions(-) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/README.md (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la/counter_la.c (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la/counter_la.py (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la/counter_la.yaml (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la_clk/counter_la_clk.c (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la_clk/counter_la_clk.py (66%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la_clk/counter_la_clk.yaml (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la_reset/counter_la_reset.c (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la_reset/counter_la_reset.py (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_la_reset/counter_la_reset.yaml (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_wb/counter_wb.c (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_wb/counter_wb.py (100%) rename verilog/dv/cocotb/{counter_tests => user_proj_tests}/counter_wb/counter_wb.yaml (100%) rename verilog/dv/cocotb/{counter_tests/counter_tests.yaml => user_proj_tests/user_proj_tests.yaml} (81%) rename verilog/dv/cocotb/{counter_tests/counter_tests_gl.yaml => user_proj_tests/user_proj_tests_gl.yaml} (100%) diff --git a/.github/workflows/user_project_ci.yml b/.github/workflows/user_project_ci.yml index b0eccaa7e..04a842df8 100644 --- a/.github/workflows/user_project_ci.yml +++ b/.github/workflows/user_project_ci.yml @@ -119,16 +119,8 @@ jobs: - name: Run DV RTL tests run: | - make verify-io_ports-rtl - make verify-la_test1-rtl - make verify-la_test2-rtl - make verify-mprj_stimulus-rtl - make verify-wb_port-rtl - - # - name: Run DV GL tests - # run: | - # make verify-io_ports-gl - # make verify-la_test1-gl - # make verify-la_test2-gl - # make verify-mprj_stimulus-gl - # make verify-wb_port-gl + make cocotb-verify-all-rtl + + -name : Run DV GL tests + run: | + make cocotb-verify-all-gl \ No newline at end of file diff --git a/Makefile b/Makefile index 226b3bca4..d07854b7c 100644 --- a/Makefile +++ b/Makefile @@ -116,8 +116,12 @@ $(blocks): % : $(MAKE) -C openlane $* dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d) +cocotb-dv_patterns=$(shell cd verilog/dv/cocotb && find . -name "*.c" | sed -e 's|^.*/||' -e 's/.c//') +$(info VAR1 is $(cocotb-dv_patterns)) dv-targets-rtl=$(dv_patterns:%=verify-%-rtl) +cocotb-dv-targets-rtl=$(cocotb-dv_patterns:%=cocotb-verify-%-rtl) dv-targets-gl=$(dv_patterns:%=verify-%-gl) +cocotb-dv-targets-gl=$(cocotb-dv_patterns:%=cocotb-verify-%-gl) dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf) TARGET_PATH=$(shell pwd) @@ -324,13 +328,19 @@ setup-cocotb: @docker pull efabless/dv:latest @docker pull efabless/dv:cocotb -.PHONY: cocotb-verify-rtl -cocotb-verify-rtl: - @(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl counter_tests/counter_tests.yaml ) +.PHONY: cocotb-verify-all-rtl +cocotb-verify-all-rtl: + @(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl user_proj_tests/user_proj_tests.yaml ) -.PHONY: cocotb-verify-gl -cocotb-verify-gl: - @(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl counter_tests/counter_tests_gl.yaml -verbosity quiet) +.PHONY: cocotb-verify-all-gl +cocotb-verify-all-gl: + @(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl user_proj_tests/user_proj_tests_gl.yaml -verbosity quiet) + +$(cocotb-dv-targets-rtl): cocotb-verify-%-rtl: + @(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -t $* ) + +$(cocotb-dv-targets-gl): cocotb-verify-%-gl: + @(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -t $* -verbosity quiet) ./verilog/gl/user_project_wrapper.v: $(error you don't have $@) diff --git a/docs/source/index.rst b/docs/source/index.rst index 99339d8b7..164b1aef1 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -155,12 +155,19 @@ Starting your project * To make sure the cocotb flow works, run the following commands for testing the counter example .. code:: bash + # To run all tests in user_project_tests list found at ``verilog/dv/cocotb/user_project_tests/user_project_tests.yaml`` + # RTL tests + make cocotb-verify-all-rtl - # RTL tests - make cocotb-verify-rtl + # OR GL simulation using + make cocotb-verify-all-gl + + # To run any test under ``verilog/dv/cocotb/*`` + # RTL + make cocotb-verify--rtl + # GL + make cocotb-verify--gl - # OR GL simulation using - make cocotb-verify-gl * To run cocotb tests on your design, Follow the steps below * Add cocotb tests under ``verilog/dv/cocotb`` follow steps at `Adding_cocotb_test `_ * Run cocotb tests using ``caravel_cocotb`` command steps at `Running_cocotb_tests `_ diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py index e33d52d89..1a6d5b1a8 100644 --- a/verilog/dv/cocotb/cocotb_tests.py +++ b/verilog/dv/cocotb/cocotb_tests.py @@ -16,8 +16,8 @@ from hello_world.hello_world import hello_world from hello_world_uart.hello_world_uart import hello_world_uart -from counter_tests.counter_wb.counter_wb import counter_wb -from counter_tests.counter_la.counter_la import counter_la -from counter_tests.counter_la_reset.counter_la_reset import counter_la_reset -from counter_tests.counter_la_clk.counter_la_clk import counter_la_clk +from user_proj_tests.counter_wb.counter_wb import counter_wb +from user_proj_tests.counter_la.counter_la import counter_la +from user_proj_tests.counter_la_reset.counter_la_reset import counter_la_reset +from user_proj_tests.counter_la_clk.counter_la_clk import counter_la_clk from gpio_test.gpio_test import gpio_test diff --git a/verilog/dv/cocotb/counter_tests/README.md b/verilog/dv/cocotb/user_proj_tests/README.md similarity index 100% rename from verilog/dv/cocotb/counter_tests/README.md rename to verilog/dv/cocotb/user_proj_tests/README.md diff --git a/verilog/dv/cocotb/counter_tests/counter_la/counter_la.c b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la/counter_la.c rename to verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.c diff --git a/verilog/dv/cocotb/counter_tests/counter_la/counter_la.py b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la/counter_la.py rename to verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.py diff --git a/verilog/dv/cocotb/counter_tests/counter_la/counter_la.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la/counter_la.yaml rename to verilog/dv/cocotb/user_proj_tests/counter_la/counter_la.yaml diff --git a/verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.c b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.c rename to verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.c diff --git a/verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.py b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py similarity index 66% rename from verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.py rename to verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py index f3b50e2e6..8fd853527 100644 --- a/verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.py +++ b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.py @@ -1,3 +1,18 @@ +# SPDX-FileCopyrightText: 2023 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 from caravel_cocotb.caravel_interfaces import test_configure from caravel_cocotb.caravel_interfaces import report_test import cocotb diff --git a/verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la_clk/counter_la_clk.yaml rename to verilog/dv/cocotb/user_proj_tests/counter_la_clk/counter_la_clk.yaml diff --git a/verilog/dv/cocotb/counter_tests/counter_la_reset/counter_la_reset.c b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la_reset/counter_la_reset.c rename to verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.c diff --git a/verilog/dv/cocotb/counter_tests/counter_la_reset/counter_la_reset.py b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la_reset/counter_la_reset.py rename to verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.py diff --git a/verilog/dv/cocotb/counter_tests/counter_la_reset/counter_la_reset.yaml b/verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_la_reset/counter_la_reset.yaml rename to verilog/dv/cocotb/user_proj_tests/counter_la_reset/counter_la_reset.yaml diff --git a/verilog/dv/cocotb/counter_tests/counter_wb/counter_wb.c b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_wb/counter_wb.c rename to verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c diff --git a/verilog/dv/cocotb/counter_tests/counter_wb/counter_wb.py b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_wb/counter_wb.py rename to verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.py diff --git a/verilog/dv/cocotb/counter_tests/counter_wb/counter_wb.yaml b/verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_wb/counter_wb.yaml rename to verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.yaml diff --git a/verilog/dv/cocotb/counter_tests/counter_tests.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml similarity index 81% rename from verilog/dv/cocotb/counter_tests/counter_tests.yaml rename to verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml index 13da5c21f..06c03308d 100644 --- a/verilog/dv/cocotb/counter_tests/counter_tests.yaml +++ b/verilog/dv/cocotb/user_proj_tests/user_proj_tests.yaml @@ -18,10 +18,8 @@ # yaml file contain general design information that would mostly need to be updated in the first run only -includes: - - counter_la/counter_la.yaml - - counter_wb/counter_wb.yaml - - counter_la_reset/counter_la_reset.yaml - - counter_la_clk/counter_la_clk.yaml - - +Tests: + - {name: counter_wb, sim: RTL} + - {name: counter_la, sim: RTL} + - {name: counter_la_reset, sim: RTL} + - {name: counter_la_clk, sim: RTL} diff --git a/verilog/dv/cocotb/counter_tests/counter_tests_gl.yaml b/verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml similarity index 100% rename from verilog/dv/cocotb/counter_tests/counter_tests_gl.yaml rename to verilog/dv/cocotb/user_proj_tests/user_proj_tests_gl.yaml