updated the structure

efabless · Sep 4, 2023 · 22ad335 · 22ad335
1 parent ac1205e
commit 22ad335
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Showing 16 changed files with 82 additions and 175 deletions.
diff --git a/Makefile b/Makefile
@@ -28,6 +28,8 @@ export PDK?=sky130A
 #export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
+PYTHON_BIN ?= python3
+
 ROOTLESS ?= 0
 USER_ARGS = -u $$(id -u $$USER):$$(id -g $$USER)
 ifeq ($(ROOTLESS), 1)
@@ -106,6 +108,11 @@ install:
 simenv:
 	docker pull efabless/dv:latest
 
+# Install cocotb docker
+.PHONY: simenv-cocotb
+simenv-cocotb:
+	docker pull efabless/dv:cocotb
+
 .PHONY: setup
 setup: check_dependencies install check-env install_mcw openlane pdk-with-volare setup-timing-scripts setup-cocotb
 
@@ -116,8 +123,12 @@ $(blocks): % :
 	$(MAKE) -C openlane $*
 
 dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+cocotb-dv_patterns=$(shell cd verilog/dv/cocotb && find . -name "*.c"  | sed -e 's|^.*/||' -e 's/.c//')
+$(info VAR1 is $(cocotb-dv_patterns))
 dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+cocotb-dv-targets-rtl=$(cocotb-dv_patterns:%=cocotb-verify-%-rtl)
 dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+cocotb-dv-targets-gl=$(cocotb-dv_patterns:%=cocotb-verify-%-gl)
 dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
 
 TARGET_PATH=$(shell pwd)
@@ -317,20 +328,33 @@ setup-timing-scripts: $(TIMING_ROOT)
 	@( cd $(TIMING_ROOT) && git pull )
 	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
 
-.PHONY: setup-cocotb
-setup-cocotb: 
-	@pip install caravel-cocotb==1.0.0 
+.PHONY: install-caravel-cocotb
+install-caravel-cocotb:
+	rm -rf ./venv
+	$(PYTHON_BIN) -m venv ./venv
+	./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir pip
+	./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir caravel-cocotb
+
+.PHONY: setup-cocotb-env
+setup-cocotb-env:
 	@(python3 $(PROJECT_ROOT)/verilog/dv/setup-cocotb.py $(CARAVEL_ROOT) $(MCW_ROOT) $(PDK_ROOT) $(PDK) $(PROJECT_ROOT))
-	@docker pull efabless/dv:latest
-	@docker pull efabless/dv:cocotb
 
-.PHONY: cocotb-verify-rtl
-cocotb-verify-rtl: 
-	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl counter_tests/counter_tests.yaml -v )
+.PHONY: setup-cocotb
+setup-cocotb: install-caravel-cocotb setup-cocotb-env simenv-cocotb
+
+.PHONY: cocotb-verify-all-rtl
+cocotb-verify-all-rtl: 
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl user_proj_tests/user_proj_tests.yaml )
+
+.PHONY: cocotb-verify-all-gl
+cocotb-verify-all-gl:
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl user_proj_tests/user_proj_tests_gl.yaml -verbosity quiet)
+
+$(cocotb-dv-targets-rtl): cocotb-verify-%-rtl: 
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -t $*  )
 
-.PHONY: cocotb-verify-gl
-cocotb-verify-gl: 
-	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl counter_tests/counter_tests_gl.yaml -v -verbosity quiet)
+$(cocotb-dv-targets-gl): cocotb-verify-%-gl:
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -t $* -verbosity quiet)
 
 ./verilog/gl/user_project_wrapper.v:
 	$(error you don't have $@)
@@ -398,4 +422,4 @@ caravel-sta: ./env/spef-mapping.tcl
 	@echo =================================================================================================
 	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
 	@echo "Check summary.log of a specific corner to point to reports with reg2reg violations" 
-	@echo "Cap and slew violations are inside summary.log file itself"
+	@echo "Cap and slew violations are inside summary.log file itself"
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
@@ -23,28 +23,12 @@
     "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
     "IO_SYNC": 0,
     "MAX_TRANSITION_CONSTRAINT": 1.5,
-    "RUN_LINTER": 0,
-    "QUIT_ON_SYNTH_CHECKS": 0,
-    "FP_PDN_CHECK_NODES": 0,
-    "SYNTH_ELABORATE_ONLY": 1,
-    "PL_RANDOM_GLB_PLACEMENT": 1,
-    "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
-    "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
-    "GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0,
-    "GLB_RESIZER_TIMING_OPTIMIZATIONS": 0,
-    "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
-    "FP_PDN_ENABLE_RAILS": 0,
-    "GRT_REPAIR_ANTENNAS": 0,
-    "RUN_FILL_INSERTION": 0,
-    "RUN_TAP_DECAP_INSERTION": 0,
     "FP_PDN_VPITCH": 180,
     "FP_PDN_HPITCH": 180,
     "RUN_CTS": 0,
     "FP_PDN_VOFFSET": 5,
     "FP_PDN_HOFFSET": 5,
-    "MAGIC_ZEROIZE_ORIGIN": 0,
     "FP_SIZING": "absolute",
-    "RUN_CVC": 0,
     "UNIT": 2.4,
     "FP_IO_VEXTEND": "expr::2 * $UNIT",
     "FP_IO_HEXTEND": "expr::2 * $UNIT",

diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py
@@ -1,7 +1,7 @@
-from hello_world.hello_world import hello_world
-from hello_world_uart.hello_world_uart import hello_world_uart
-from counter_tests.counter_wb.counter_wb import counter_wb
-from counter_tests.counter_la.counter_la import counter_la
-from counter_tests.counter_la_reset.counter_la_reset import counter_la_reset
-from counter_tests.counter_la_clk.counter_la_clk import counter_la_clk
-from gpio_test.gpio_test import gpio_test
+from user_porj_tests.hello_world.hello_world import hello_world
+from user_porj_tests.hello_world_uart.hello_world_uart import hello_world_uart
+from user_porj_tests.counter_tests.counter_wb.counter_wb import counter_wb
+from user_porj_tests.counter_tests.counter_la.counter_la import counter_la
+from user_porj_tests.counter_tests.counter_la_reset.counter_la_reset import counter_la_reset
+from user_porj_tests.counter_tests.counter_la_clk.counter_la_clk import counter_la_clk
+from user_porj_tests.gpio_test.gpio_test import gpio_test
diff --git a/verilog/dv/cocotb/design_info.yaml b/verilog/dv/cocotb/design_info.yaml
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.c b/verilog/dv/cocotb/gpio_test/gpio_test.c
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.py b/verilog/dv/cocotb/gpio_test/gpio_test.py
diff --git a/verilog/dv/cocotb/hello_world/hello_world.c b/verilog/dv/cocotb/hello_world/hello_world.c
diff --git a/verilog/dv/cocotb/hello_world/hello_world.py b/verilog/dv/cocotb/hello_world/hello_world.py
diff --git a/verilog/dv/cocotb/hello_world/hello_world.yaml b/verilog/dv/cocotb/hello_world/hello_world.yaml
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -15,4 +15,4 @@
 
 // Caravel user project includes		
 $USER_PROJECT_VERILOG/gl/user_project_wrapper.v
-$USER_PROJECT_VERILOG/gl/user_proj_example.v
+$USER_PROJECT_VERILOG/gl/my_project.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
@@ -15,4 +15,4 @@
 
 # Caravel user project includes	     
 -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v    
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/gl/my_project.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
@@ -15,6 +15,6 @@
 
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/my_project.v
 
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
@@ -82,6 +82,42 @@ module user_project_wrapper #(
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
+my_project mprj (
+`ifdef USE_POWER_PINS
+	.vccd1(vccd1),	// User area 1 1.8V power
+	.vssd1(vssd1),	// User area 1 digital ground
+`endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+
+    .io_in ({io_in[37:30],io_in[7:0]}),
+    .io_out({io_out[37:30],io_out[7:0]}),
+    .io_oeb({io_oeb[37:30],io_oeb[7:0]}),
+
+    // IRQ
+    .irq(user_irq)
+);
+
 endmodule	// user_project_wrapper
 
 `default_nettype wire