diff --git a/Makefile b/Makefile
index a0a9fbb5f..b05c11346 100644
--- a/Makefile
+++ b/Makefile
@@ -28,6 +28,8 @@ export PDK?=sky130A
 #export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
+PYTHON_BIN ?= python3
+
 ROOTLESS ?= 0
 USER_ARGS = -u $$(id -u $$USER):$$(id -g $$USER)
 ifeq ($(ROOTLESS), 1)
@@ -106,6 +108,11 @@ install:
 simenv:
 	docker pull efabless/dv:latest
 
+# Install cocotb docker
+.PHONY: simenv-cocotb
+simenv-cocotb:
+	docker pull efabless/dv:cocotb
+
 .PHONY: setup
 setup: check_dependencies install check-env install_mcw openlane pdk-with-volare setup-timing-scripts setup-cocotb
 
@@ -116,8 +123,12 @@ $(blocks): % :
 	$(MAKE) -C openlane $*
 
 dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+cocotb-dv_patterns=$(shell cd verilog/dv/cocotb && find . -name "*.c"  | sed -e 's|^.*/||' -e 's/.c//')
+$(info VAR1 is $(cocotb-dv_patterns))
 dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+cocotb-dv-targets-rtl=$(cocotb-dv_patterns:%=cocotb-verify-%-rtl)
 dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+cocotb-dv-targets-gl=$(cocotb-dv_patterns:%=cocotb-verify-%-gl)
 dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
 
 TARGET_PATH=$(shell pwd)
@@ -317,20 +328,33 @@ setup-timing-scripts: $(TIMING_ROOT)
 	@( cd $(TIMING_ROOT) && git pull )
 	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
 
-.PHONY: setup-cocotb
-setup-cocotb: 
-	@pip install caravel-cocotb==1.0.0 
+.PHONY: install-caravel-cocotb
+install-caravel-cocotb:
+	rm -rf ./venv
+	$(PYTHON_BIN) -m venv ./venv
+	./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir pip
+	./venv/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir caravel-cocotb
+
+.PHONY: setup-cocotb-env
+setup-cocotb-env:
 	@(python3 $(PROJECT_ROOT)/verilog/dv/setup-cocotb.py $(CARAVEL_ROOT) $(MCW_ROOT) $(PDK_ROOT) $(PDK) $(PROJECT_ROOT))
-	@docker pull efabless/dv:latest
-	@docker pull efabless/dv:cocotb
 
-.PHONY: cocotb-verify-rtl
-cocotb-verify-rtl: 
-	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl counter_tests/counter_tests.yaml -v )
+.PHONY: setup-cocotb
+setup-cocotb: install-caravel-cocotb setup-cocotb-env simenv-cocotb
+
+.PHONY: cocotb-verify-all-rtl
+cocotb-verify-all-rtl: 
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl user_proj_tests/user_proj_tests.yaml )
+	
+.PHONY: cocotb-verify-all-gl
+cocotb-verify-all-gl:
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl user_proj_tests/user_proj_tests_gl.yaml -verbosity quiet)
+
+$(cocotb-dv-targets-rtl): cocotb-verify-%-rtl: 
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -t $*  )
 	
-.PHONY: cocotb-verify-gl
-cocotb-verify-gl: 
-	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -tl counter_tests/counter_tests_gl.yaml -v -verbosity quiet)
+$(cocotb-dv-targets-gl): cocotb-verify-%-gl:
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && caravel_cocotb -t $* -verbosity quiet)
 
 ./verilog/gl/user_project_wrapper.v:
 	$(error you don't have $@)
@@ -398,4 +422,4 @@ caravel-sta: ./env/spef-mapping.tcl
 	@echo =================================================================================================
 	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
 	@echo "Check summary.log of a specific corner to point to reports with reg2reg violations" 
-	@echo "Cap and slew violations are inside summary.log file itself"
+	@echo "Cap and slew violations are inside summary.log file itself"
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 1d7f07e35..6349f580a 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -23,28 +23,12 @@
     "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
     "IO_SYNC": 0,
     "MAX_TRANSITION_CONSTRAINT": 1.5,
-    "RUN_LINTER": 0,
-    "QUIT_ON_SYNTH_CHECKS": 0,
-    "FP_PDN_CHECK_NODES": 0,
-    "SYNTH_ELABORATE_ONLY": 1,
-    "PL_RANDOM_GLB_PLACEMENT": 1,
-    "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
-    "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
-    "GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0,
-    "GLB_RESIZER_TIMING_OPTIMIZATIONS": 0,
-    "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
-    "FP_PDN_ENABLE_RAILS": 0,
-    "GRT_REPAIR_ANTENNAS": 0,
-    "RUN_FILL_INSERTION": 0,
-    "RUN_TAP_DECAP_INSERTION": 0,
     "FP_PDN_VPITCH": 180,
     "FP_PDN_HPITCH": 180,
     "RUN_CTS": 0,
     "FP_PDN_VOFFSET": 5,
     "FP_PDN_HOFFSET": 5,
-    "MAGIC_ZEROIZE_ORIGIN": 0,
     "FP_SIZING": "absolute",
-    "RUN_CVC": 0,
     "UNIT": 2.4,
     "FP_IO_VEXTEND": "expr::2 * $UNIT",
     "FP_IO_HEXTEND": "expr::2 * $UNIT",
diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py
index 4c676ec58..88cff4ce0 100644
--- a/verilog/dv/cocotb/cocotb_tests.py
+++ b/verilog/dv/cocotb/cocotb_tests.py
@@ -1,7 +1,7 @@
-from hello_world.hello_world import hello_world
-from hello_world_uart.hello_world_uart import hello_world_uart
-from counter_tests.counter_wb.counter_wb import counter_wb
-from counter_tests.counter_la.counter_la import counter_la
-from counter_tests.counter_la_reset.counter_la_reset import counter_la_reset
-from counter_tests.counter_la_clk.counter_la_clk import counter_la_clk
-from gpio_test.gpio_test import gpio_test
+from user_porj_tests.hello_world.hello_world import hello_world
+from user_porj_tests.hello_world_uart.hello_world_uart import hello_world_uart
+from user_porj_tests.counter_tests.counter_wb.counter_wb import counter_wb
+from user_porj_tests.counter_tests.counter_la.counter_la import counter_la
+from user_porj_tests.counter_tests.counter_la_reset.counter_la_reset import counter_la_reset
+from user_porj_tests.counter_tests.counter_la_clk.counter_la_clk import counter_la_clk
+from user_porj_tests.gpio_test.gpio_test import gpio_test
diff --git a/verilog/dv/cocotb/design_info.yaml b/verilog/dv/cocotb/design_info.yaml
deleted file mode 100644
index b4abb868f..000000000
--- a/verilog/dv/cocotb/design_info.yaml
+++ /dev/null
@@ -1,37 +0,0 @@
-# yaml file contain general design information that would mostly need to be updated in the first run only 
-
-#eg CARAVEL_ROOT: "/usr/Desktop/caravel_project/caravel/" 
-#like repo https://github.com/efabless/caravel
-# CARAVEL_ROOT: "/home/usr/caravel/swift/swift2"
-CARAVEL_ROOT: /home/usr/caravel/caravel
-
-#eg MCW_ROOT: "/usr/Desktop/caravel_project/caravel_mgmt_soc_litex/" 
-#like repo https://github.com/efabless/caravel_mgmt_soc_litex 
-# MCW_ROOT: "/home/usr/caravel/swift/swift2"
-MCW_ROOT: /home/usr/caravel/caravel_mgmt_soc_litex/
-
-#eg USER_PROJECT_ROOT: "/usr/Desktop/caravel_project/caravel_user_project/" 
-#like repo https://github.com/efabless/caravel_user_project
-USER_PROJECT_ROOT: /home/usr/caravel/caravel_user_project/
-# USER_PROJECT_ROOT: "/home/usr/caravel/swift/caravel_user_project"
-# USER_PROJECT_ROOT: None
-# USER_PROJECT_ROOT: None
-
-
-
-#eg PDK_ROOT: "/usr/Desktop/caravel_project/pdk/" 
-#exported by volare
-PDK_ROOT: /home/usr/pdk
-
-#eg PDK: "sky130A"
-PDK: sky130A
-#PDK: gf180mcuC
-
-#clock in ns
-clk: 25  
-
-# true when caravan are simulated instead of caravel
-caravan: false
-
-# optional email address to send the results to 
-emailto: [None]
\ No newline at end of file
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.c b/verilog/dv/cocotb/gpio_test/gpio_test.c
deleted file mode 100644
index 0f0f073d1..000000000
--- a/verilog/dv/cocotb/gpio_test/gpio_test.c
+++ /dev/null
@@ -1,15 +0,0 @@
-#include <firmware_apis.h> // include required APIs
-void main(){
-   // Enable managment gpio as output to use as indicator for finishing configuration 
-   ManagmentGpio_outputEnable();
-   ManagmentGpio_write(0);
-   enableHkSpi(0); // disable housekeeping spi
-   //GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUT);
-   GPIOs_configureAll(GPIO_MODE_MGMT_STD_OUTPUT);
-   GPIOs_loadConfigs();
-   set_gpio_l(0x8F);
-   ManagmentGpio_write(1); // configuration finished 
-
-   
-   return;
-}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/gpio_test/gpio_test.py b/verilog/dv/cocotb/gpio_test/gpio_test.py
deleted file mode 100644
index 7ca15952c..000000000
--- a/verilog/dv/cocotb/gpio_test/gpio_test.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from caravel_cocotb.caravel_interfaces import * # import python APIs
-import cocotb
-
-@cocotb.test() # cocotb test marker
-@report_test # wrapper for configure test reporting files
-async def gpio_test(dut):
-   caravelEnv = await test_configure(dut) #configure, start up and reset caravel
-   #await caravelEnv.release_csb()
-   await caravelEnv.wait_mgmt_gpio(1)
-   gpios_value_str = caravelEnv.monitor_gpio(37, 0).binstr
-   cocotb.log.info (f"All gpios '{gpios_value_str}'")
-   gpio_value_int = caravelEnv.monitor_gpio(37, 0).integer
-   #expected_gpio_value = 0xF8
-   expected_gpio_value = 0x8F
-   if (gpio_value_int == expected_gpio_value):
-      cocotb.log.info (f"[TEST] Pass the gpio value is '{hex(gpio_value_int)}'")
-   else:
-      cocotb.log.error (f"[TEST] Fail the gpio value is :'{hex(gpio_value_int)}' expected {hex(expected_gpio_value)}")
-   
-
diff --git a/verilog/dv/cocotb/hello_world/hello_world.c b/verilog/dv/cocotb/hello_world/hello_world.c
deleted file mode 100644
index c6526b824..000000000
--- a/verilog/dv/cocotb/hello_world/hello_world.c
+++ /dev/null
@@ -1,4 +0,0 @@
-#include <firmware_apis.h>
-void main(){
-    return;
-}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world/hello_world.py b/verilog/dv/cocotb/hello_world/hello_world.py
deleted file mode 100644
index 3618d49c0..000000000
--- a/verilog/dv/cocotb/hello_world/hello_world.py
+++ /dev/null
@@ -1,9 +0,0 @@
-from caravel_cocotb.caravel_interfaces import test_configure
-from caravel_cocotb.caravel_interfaces import report_test
-import cocotb
-
-@cocotb.test()
-@report_test
-async def hello_world(dut):
-    caravelEnv = await test_configure(dut,timeout_cycles=9373)
-    cocotb.log.info("Hello World")
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world/hello_world.yaml b/verilog/dv/cocotb/hello_world/hello_world.yaml
deleted file mode 100644
index bd6165dc2..000000000
--- a/verilog/dv/cocotb/hello_world/hello_world.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
----
-# Yalm file contain general design information that would mostly need to be updated in the first run only 
-# example 
-## tests: [debug,clock_redirect]
-## sim: [RTL,RTL]
-Tests: 
-    - {name: hello_world, sim: RTL}
-
-
-
-
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c
deleted file mode 100644
index 098a6d7da..000000000
--- a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <firmware_apis.h>
-
-void main(){
-    ManagmentGpio_write(0);
-    ManagmentGpio_outputEnable();
-    GPIOs_configure(6,GPIO_MODE_MGMT_STD_OUTPUT);
-    GPIOs_loadConfigs();
-    UART_enableTX(1);
-    ManagmentGpio_write(1); // configuration finished 
-
-    print("Hello World\n");
-    return;
-}
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py
deleted file mode 100644
index 66ab6d88b..000000000
--- a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py
+++ /dev/null
@@ -1,21 +0,0 @@
-from caravel_cocotb.caravel_interfaces import test_configure
-from caravel_cocotb.caravel_interfaces import report_test
-import cocotb
-from caravel_cocotb.caravel_interfaces import UART
-
-@cocotb.test()
-@report_test
-async def hello_world_uart(dut):
-    caravelEnv = await test_configure(dut,timeout_cycles=3346140)
-
-    cocotb.log.info(f"[TEST] Start uart test")  
-    expected_msg = "Hello World"
-    uart = UART(caravelEnv)
-    # wait for start of sending
-    await caravelEnv.wait_mgmt_gpio(1)
-    # read the msg sent
-    msg = await uart.get_line()
-    if msg in expected_msg :
-        cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{msg}'")
-    else: 
-        cocotb.log.error (f"[TEST] recieved wrong msg from uart msg recieved:'{msg}' expected '{expected_msg}'")
\ No newline at end of file
diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml
deleted file mode 100644
index 37d5fd1c2..000000000
--- a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml
+++ /dev/null
@@ -1,7 +0,0 @@
----
-# Yalm file contain general design information that would mostly need to be updated in the first run only 
-
-Tests: 
-    - {name: hello_world_uart, sim: RTL}
-
-
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
index 44fa5425a..2e73c2294 100644
--- a/verilog/includes/includes.gl+sdf.caravel_user_project
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -15,4 +15,4 @@
 
 // Caravel user project includes		
 $USER_PROJECT_VERILOG/gl/user_project_wrapper.v
-$USER_PROJECT_VERILOG/gl/user_proj_example.v
+$USER_PROJECT_VERILOG/gl/my_project.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index b62af99f4..323a25e72 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -15,4 +15,4 @@
 
 # Caravel user project includes	     
 -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v    
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/gl/my_project.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index a8c6e021d..6048a94c7 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -15,6 +15,6 @@
 
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/my_project.v
 
  
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bf76cf096..5338cbc8f 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,6 +82,42 @@ module user_project_wrapper #(
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
+my_project mprj (
+`ifdef USE_POWER_PINS
+	.vccd1(vccd1),	// User area 1 1.8V power
+	.vssd1(vssd1),	// User area 1 digital ground
+`endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+
+    .io_in ({io_in[37:30],io_in[7:0]}),
+    .io_out({io_out[37:30],io_out[7:0]}),
+    .io_oeb({io_oeb[37:30],io_oeb[7:0]}),
+
+    // IRQ
+    .irq(user_irq)
+);
+
 endmodule	// user_project_wrapper
 
 `default_nettype wire