diff --git a/openlane/Makefile b/openlane/Makefile
index 6ea860d13..0abd9da3b 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -85,6 +85,7 @@ endif
 	@cp $(PDK_ROOT)/$(PDK)/SOURCES $(PROJECT_ROOT)/signoff/$*/PDK_SOURCES
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/final/*.csv $(PROJECT_ROOT)/signoff/$*/
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/final/def/* $(PROJECT_ROOT)/def/$*.def
+	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/final/sdc/* $(PROJECT_ROOT)/sdc/$*.sdc
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/final/gds/* $(PROJECT_ROOT)/gds/$*.gds
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/final/lef/* $(PROJECT_ROOT)/lef/$*.lef
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/*magic-streamout/*.mag $(PROJECT_ROOT)/mag/$*.mag
@@ -97,6 +98,10 @@ endif
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/final/lib/nom*tt*/* $(PROJECT_ROOT)/lib/$*.lib
 	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/resolved.json $(PROJECT_ROOT)/signoff/$*/
 	@mkdir -p $(PROJECT_ROOT)/signoff/$*/openlane-signoff/timing-reports
+	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/*magic-drc/reports/* $(PROJECT_ROOT)/signoff/$*/openlane-signoff/
+	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/*netgen-lvs/lvs.rpt $(PROJECT_ROOT)/signoff/$*/openlane-signoff/
+	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/*netgen-lvs/lvs.rpt $(PROJECT_ROOT)/signoff/$*/openlane-signoff/
+	@cp $(PROJECT_ROOT)/openlane/$*/runs/$*/*netgen-lvs/netgen-lvs.log $(PROJECT_ROOT)/signoff/$*/openlane-signoff/
 	@cp -r $(PROJECT_ROOT)/openlane/$*/runs/$*/*openroad-stapostpnr/* $(PROJECT_ROOT)/signoff/$*/openlane-signoff/timing-reports
 	# https://github.com/koalaman/shellcheck/wiki/SC2044
 	@while IFS= read -r -d '' file ; \
diff --git a/sdc/user_proj_example.sdc b/sdc/user_proj_example.sdc
index da07eb014..7bca9fc95 100644
--- a/sdc/user_proj_example.sdc
+++ b/sdc/user_proj_example.sdc
@@ -1,1891 +1,145 @@
-###############################################################################
-# Created by write_sdc
-# Wed Jul 19 15:17:31 2023
-###############################################################################
-current_design user_proj_example
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name clk -period 25.0000 [get_ports {wb_clk_i}]
-set_clock_transition 0.1500 [get_clocks {clk}]
-set_clock_uncertainty 0.2500 clk
-set_propagated_clock [get_clocks {clk}]
-set_clock_latency -source -min 4.6500 [get_clocks {clk}]
-set_clock_latency -source -max 5.5700 [get_clocks {clk}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[0]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[0]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[100]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[100]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[101]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[101]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[102]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[102]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[103]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[103]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[104]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[104]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[105]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[105]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[106]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[106]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[107]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[107]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[108]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[108]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[109]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[109]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[10]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[10]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[110]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[110]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[111]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[111]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[112]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[112]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[113]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[113]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[114]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[114]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[115]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[115]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[116]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[116]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[117]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[117]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[118]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[118]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[119]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[119]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[11]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[11]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[120]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[120]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[121]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[121]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[122]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[122]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[123]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[123]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[124]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[124]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[125]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[125]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[126]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[126]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[127]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[127]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[12]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[12]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[13]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[13]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[14]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[14]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[15]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[15]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[16]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[16]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[17]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[17]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[18]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[18]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[19]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[19]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[1]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[1]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[20]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[20]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[21]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[21]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[22]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[22]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[23]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[23]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[24]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[24]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[25]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[25]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[26]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[26]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[27]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[27]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[28]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[28]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[29]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[29]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[2]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[2]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[30]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[30]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[31]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[31]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[32]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[32]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[33]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[33]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[34]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[34]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[35]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[35]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[36]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[36]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[37]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[37]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[38]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[38]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[39]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[39]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[3]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[3]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[40]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[40]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[41]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[41]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[42]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[42]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[43]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[43]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[44]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[44]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[45]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[45]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[46]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[46]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[47]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[47]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[48]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[48]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[49]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[49]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[4]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[4]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[50]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[50]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[51]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[51]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[52]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[52]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[53]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[53]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[54]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[54]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[55]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[55]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[56]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[56]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[57]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[57]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[58]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[58]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[59]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[59]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[5]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[5]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[60]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[60]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[61]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[61]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[62]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[62]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[63]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[63]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[64]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[64]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[65]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[65]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[66]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[66]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[67]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[67]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[68]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[68]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[69]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[69]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[6]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[6]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[70]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[70]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[71]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[71]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[72]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[72]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[73]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[73]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[74]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[74]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[75]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[75]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[76]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[76]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[77]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[77]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[78]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[78]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[79]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[79]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[7]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[7]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[80]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[80]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[81]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[81]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[82]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[82]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[83]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[83]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[84]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[84]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[85]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[85]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[86]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[86]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[87]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[87]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[88]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[88]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[89]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[89]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[8]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[8]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[90]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[90]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[91]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[91]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[92]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[92]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[93]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[93]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[94]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[94]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[95]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[95]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[96]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[96]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[97]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[97]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[98]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[98]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[99]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[99]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[9]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[9]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[0]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[0]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[100]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[100]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[101]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[101]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[102]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[102]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[103]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[103]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[104]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[104]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[105]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[105]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[106]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[106]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[107]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[107]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[108]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[108]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[109]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[109]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[10]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[10]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[110]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[110]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[111]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[111]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[112]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[112]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[113]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[113]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[114]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[114]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[115]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[115]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[116]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[116]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[117]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[117]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[118]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[118]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[119]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[119]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[11]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[11]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[120]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[120]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[121]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[121]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[122]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[122]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[123]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[123]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[124]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[124]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[125]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[125]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[126]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[126]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[127]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[127]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[12]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[12]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[13]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[13]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[14]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[14]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[15]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[15]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[16]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[16]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[17]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[17]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[18]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[18]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[19]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[19]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[1]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[1]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[20]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[20]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[21]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[21]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[22]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[22]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[23]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[23]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[24]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[24]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[25]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[25]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[26]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[26]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[27]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[27]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[28]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[28]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[29]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[29]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[2]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[2]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[30]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[30]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[31]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[31]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[32]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[32]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[33]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[33]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[34]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[34]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[35]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[35]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[36]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[36]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[37]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[37]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[38]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[38]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[39]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[39]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[3]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[3]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[40]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[40]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[41]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[41]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[42]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[42]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[43]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[43]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[44]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[44]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[45]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[45]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[46]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[46]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[47]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[47]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[48]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[48]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[49]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[49]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[4]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[4]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[50]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[50]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[51]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[51]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[52]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[52]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[53]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[53]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[54]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[54]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[55]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[55]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[56]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[56]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[57]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[57]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[58]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[58]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[59]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[59]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[5]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[5]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[60]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[60]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[61]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[61]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[62]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[62]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[63]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[63]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[64]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[64]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[65]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[65]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[66]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[66]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[67]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[67]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[68]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[68]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[69]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[69]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[6]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[6]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[70]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[70]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[71]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[71]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[72]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[72]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[73]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[73]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[74]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[74]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[75]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[75]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[76]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[76]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[77]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[77]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[78]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[78]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[79]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[79]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[7]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[7]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[80]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[80]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[81]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[81]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[82]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[82]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[83]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[83]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[84]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[84]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[85]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[85]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[86]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[86]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[87]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[87]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[88]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[88]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[89]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[89]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[8]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[8]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[90]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[90]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[91]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[91]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[92]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[92]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[93]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[93]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[94]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[94]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[95]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[95]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[96]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[96]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[97]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[97]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[98]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[98]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[99]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[99]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[9]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[9]}]
-set_input_delay 12.5000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_rst_i}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[0]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[0]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[10]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[10]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[11]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[11]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[12]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[12]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[13]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[13]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[14]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[14]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[15]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[15]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[16]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[16]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[17]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[17]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[18]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[18]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[19]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[19]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[1]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[1]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[20]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[20]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[21]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[21]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[22]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[22]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[23]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[23]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[24]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[24]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[25]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[25]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[26]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[26]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[27]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[27]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[28]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[28]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[29]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[29]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[2]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[2]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[30]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[30]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[31]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[31]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[3]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[3]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[4]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[4]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[5]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[5]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[6]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[6]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[7]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[7]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[8]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[8]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[9]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[9]}]
-set_input_delay 1.6900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_cyc_i}]
-set_input_delay 4.7400 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_cyc_i}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[0]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[0]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[10]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[10]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[11]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[11]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[12]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[12]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[13]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[13]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[14]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[14]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[15]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[15]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[16]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[16]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[17]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[17]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[18]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[18]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[19]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[19]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[1]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[1]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[20]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[20]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[21]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[21]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[22]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[22]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[23]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[23]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[24]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[24]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[25]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[25]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[26]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[26]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[27]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[27]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[28]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[28]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[29]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[29]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[2]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[2]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[30]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[30]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[31]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[31]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[3]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[3]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[4]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[4]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[5]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[5]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[6]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[6]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[7]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[7]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[8]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[8]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[9]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[9]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[0]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[0]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[1]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[1]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[2]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[2]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[3]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[3]}]
-set_input_delay 1.8600 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_stb_i}]
-set_input_delay 4.1300 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_stb_i}]
-set_input_delay 1.6500 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_we_i}]
-set_input_delay 3.7400 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_we_i}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[0]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[0]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[100]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[100]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[101]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[101]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[102]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[102]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[103]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[103]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[104]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[104]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[105]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[105]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[106]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[106]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[107]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[107]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[108]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[108]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[109]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[109]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[10]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[10]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[110]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[110]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[111]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[111]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[112]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[112]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[113]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[113]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[114]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[114]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[115]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[115]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[116]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[116]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[117]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[117]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[118]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[118]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[119]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[119]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[11]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[11]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[120]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[120]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[121]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[121]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[122]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[122]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[123]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[123]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[124]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[124]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[125]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[125]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[126]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[126]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[127]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[127]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[12]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[12]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[13]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[13]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[14]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[14]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[15]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[15]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[16]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[16]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[17]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[17]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[18]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[18]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[19]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[19]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[1]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[1]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[20]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[20]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[21]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[21]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[22]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[22]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[23]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[23]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[24]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[24]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[25]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[25]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[26]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[26]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[27]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[27]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[28]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[28]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[29]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[29]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[2]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[2]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[30]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[30]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[31]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[31]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[32]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[32]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[33]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[33]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[34]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[34]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[35]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[35]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[36]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[36]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[37]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[37]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[38]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[38]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[39]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[39]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[3]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[3]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[40]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[40]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[41]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[41]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[42]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[42]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[43]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[43]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[44]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[44]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[45]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[45]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[46]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[46]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[47]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[47]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[48]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[48]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[49]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[49]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[4]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[4]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[50]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[50]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[51]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[51]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[52]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[52]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[53]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[53]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[54]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[54]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[55]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[55]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[56]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[56]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[57]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[57]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[58]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[58]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[59]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[59]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[5]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[5]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[60]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[60]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[61]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[61]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[62]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[62]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[63]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[63]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[64]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[64]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[65]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[65]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[66]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[66]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[67]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[67]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[68]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[68]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[69]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[69]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[6]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[6]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[70]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[70]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[71]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[71]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[72]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[72]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[73]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[73]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[74]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[74]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[75]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[75]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[76]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[76]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[77]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[77]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[78]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[78]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[79]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[79]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[7]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[7]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[80]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[80]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[81]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[81]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[82]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[82]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[83]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[83]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[84]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[84]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[85]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[85]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[86]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[86]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[87]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[87]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[88]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[88]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[89]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[89]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[8]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[8]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[90]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[90]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[91]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[91]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[92]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[92]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[93]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[93]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[94]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[94]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[95]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[95]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[96]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[96]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[97]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[97]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[98]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[98]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[99]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[99]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[9]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[9]}]
-set_output_delay 1.3700 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_ack_o}]
-set_output_delay 8.4100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_ack_o}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[0]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[0]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[10]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[10]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[11]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[11]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[12]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[12]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[13]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[13]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[14]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[14]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[15]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[15]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[16]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[16]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[17]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[17]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[18]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[18]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[19]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[19]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[1]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[1]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[20]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[20]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[21]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[21]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[22]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[22]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[23]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[23]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[24]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[24]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[25]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[25]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[26]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[26]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[27]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[27]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[28]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[28]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[29]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[29]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[2]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[2]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[30]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[30]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[31]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[31]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[3]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[3]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[4]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[4]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[5]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[5]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[6]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[6]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[7]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[7]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[8]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[8]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[9]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[9]}]
-set_multicycle_path -hold\
-    -through [list [get_ports {wbs_ack_o}]\
-           [get_ports {wbs_cyc_i}]\
-           [get_ports {wbs_stb_i}]] 1
-set_multicycle_path -setup\
-    -through [list [get_ports {wbs_ack_o}]\
-           [get_ports {wbs_cyc_i}]\
-           [get_ports {wbs_stb_i}]] 2
-###############################################################################
-# Environment
-###############################################################################
-set_load -pin_load 0.1900 [get_ports {wbs_ack_o}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[15]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[14]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[13]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[12]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[11]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[10]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[9]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[8]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[7]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[6]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[5]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[4]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[3]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[2]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[1]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[0]}]
-set_load -pin_load 0.1900 [get_ports {io_out[15]}]
-set_load -pin_load 0.1900 [get_ports {io_out[14]}]
-set_load -pin_load 0.1900 [get_ports {io_out[13]}]
-set_load -pin_load 0.1900 [get_ports {io_out[12]}]
-set_load -pin_load 0.1900 [get_ports {io_out[11]}]
-set_load -pin_load 0.1900 [get_ports {io_out[10]}]
-set_load -pin_load 0.1900 [get_ports {io_out[9]}]
-set_load -pin_load 0.1900 [get_ports {io_out[8]}]
-set_load -pin_load 0.1900 [get_ports {io_out[7]}]
-set_load -pin_load 0.1900 [get_ports {io_out[6]}]
-set_load -pin_load 0.1900 [get_ports {io_out[5]}]
-set_load -pin_load 0.1900 [get_ports {io_out[4]}]
-set_load -pin_load 0.1900 [get_ports {io_out[3]}]
-set_load -pin_load 0.1900 [get_ports {io_out[2]}]
-set_load -pin_load 0.1900 [get_ports {io_out[1]}]
-set_load -pin_load 0.1900 [get_ports {io_out[0]}]
-set_load -pin_load 0.1900 [get_ports {irq[2]}]
-set_load -pin_load 0.1900 [get_ports {irq[1]}]
-set_load -pin_load 0.1900 [get_ports {irq[0]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[127]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[126]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[125]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[124]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[123]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[122]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[121]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[120]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[119]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[118]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[117]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[116]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[115]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[114]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[113]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[112]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[111]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[110]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[109]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[108]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[107]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[106]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[105]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[104]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[103]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[102]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[101]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[100]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[99]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[98]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[97]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[96]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[95]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[94]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[93]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[92]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[91]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[90]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[89]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[88]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[87]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[86]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[85]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[84]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[83]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[82]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[81]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[80]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[79]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[78]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[77]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[76]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[75]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[74]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[73]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[72]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[71]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[70]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[69]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[68]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[67]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[66]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[65]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[64]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[63]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[62]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[61]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[60]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[59]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[58]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[57]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[56]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[55]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[54]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[53]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[52]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[51]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[50]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[49]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[48]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[47]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[46]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[45]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[44]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[43]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[42]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[41]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[40]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[39]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[38]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[37]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[36]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[35]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[34]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[33]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[32]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[31]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[30]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[29]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[28]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[27]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[26]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[25]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[24]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[23]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[22]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[21]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[20]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[19]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[18]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[17]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[16]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[15]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[14]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[13]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[12]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[11]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[10]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[9]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[8]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[7]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[6]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[5]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[4]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[3]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[2]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[1]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[0]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[31]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[30]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[29]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[28]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[27]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[26]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[25]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[24]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[23]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[22]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[21]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[20]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[19]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[18]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[17]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[16]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[15]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[14]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[13]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[12]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[11]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[10]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[9]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[8]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[7]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[6]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[5]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[4]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[3]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[2]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[1]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[0]}]
-set_input_transition 0.6100 [get_ports {wb_clk_i}]
-set_input_transition -min 0.0900 [get_ports {wbs_cyc_i}]
-set_input_transition -max 0.1700 [get_ports {wbs_cyc_i}]
-set_input_transition 0.1500 [get_ports {wbs_stb_i}]
-set_input_transition -min 0.0900 [get_ports {wbs_we_i}]
-set_input_transition -max 0.1400 [get_ports {wbs_we_i}]
-set_input_transition -min 0.0500 [get_ports {io_in[15]}]
-set_input_transition -max 0.3800 [get_ports {io_in[15]}]
-set_input_transition -min 0.0500 [get_ports {io_in[14]}]
-set_input_transition -max 0.3800 [get_ports {io_in[14]}]
-set_input_transition -min 0.0500 [get_ports {io_in[13]}]
-set_input_transition -max 0.3800 [get_ports {io_in[13]}]
-set_input_transition -min 0.0500 [get_ports {io_in[12]}]
-set_input_transition -max 0.3800 [get_ports {io_in[12]}]
-set_input_transition -min 0.0500 [get_ports {io_in[11]}]
-set_input_transition -max 0.3800 [get_ports {io_in[11]}]
-set_input_transition -min 0.0500 [get_ports {io_in[10]}]
-set_input_transition -max 0.3800 [get_ports {io_in[10]}]
-set_input_transition -min 0.0500 [get_ports {io_in[9]}]
-set_input_transition -max 0.3800 [get_ports {io_in[9]}]
-set_input_transition -min 0.0500 [get_ports {io_in[8]}]
-set_input_transition -max 0.3800 [get_ports {io_in[8]}]
-set_input_transition -min 0.0500 [get_ports {io_in[7]}]
-set_input_transition -max 0.3800 [get_ports {io_in[7]}]
-set_input_transition -min 0.0500 [get_ports {io_in[6]}]
-set_input_transition -max 0.3800 [get_ports {io_in[6]}]
-set_input_transition -min 0.0500 [get_ports {io_in[5]}]
-set_input_transition -max 0.3800 [get_ports {io_in[5]}]
-set_input_transition -min 0.0500 [get_ports {io_in[4]}]
-set_input_transition -max 0.3800 [get_ports {io_in[4]}]
-set_input_transition -min 0.0500 [get_ports {io_in[3]}]
-set_input_transition -max 0.3800 [get_ports {io_in[3]}]
-set_input_transition -min 0.0500 [get_ports {io_in[2]}]
-set_input_transition -max 0.3800 [get_ports {io_in[2]}]
-set_input_transition -min 0.0500 [get_ports {io_in[1]}]
-set_input_transition -max 0.3800 [get_ports {io_in[1]}]
-set_input_transition -min 0.0500 [get_ports {io_in[0]}]
-set_input_transition -max 0.3800 [get_ports {io_in[0]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[127]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[127]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[126]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[126]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[125]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[125]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[124]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[124]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[123]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[123]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[122]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[122]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[121]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[121]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[120]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[120]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[119]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[119]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[118]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[118]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[117]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[117]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[116]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[116]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[115]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[115]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[114]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[114]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[113]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[113]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[112]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[112]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[111]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[111]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[110]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[110]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[109]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[109]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[108]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[108]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[107]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[107]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[106]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[106]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[105]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[105]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[104]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[104]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[103]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[103]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[102]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[102]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[101]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[101]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[100]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[100]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[99]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[99]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[98]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[98]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[97]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[97]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[96]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[96]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[95]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[95]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[94]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[94]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[93]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[93]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[92]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[92]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[91]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[91]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[90]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[90]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[89]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[89]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[88]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[88]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[87]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[87]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[86]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[86]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[85]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[85]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[84]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[84]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[83]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[83]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[82]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[82]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[81]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[81]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[80]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[80]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[79]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[79]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[78]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[78]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[77]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[77]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[76]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[76]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[75]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[75]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[74]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[74]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[73]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[73]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[72]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[72]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[71]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[71]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[70]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[70]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[69]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[69]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[68]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[68]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[67]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[67]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[66]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[66]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[65]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[65]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[64]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[64]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[63]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[63]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[62]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[62]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[61]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[61]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[60]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[60]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[59]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[59]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[58]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[58]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[57]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[57]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[56]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[56]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[55]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[55]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[54]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[54]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[53]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[53]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[52]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[52]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[51]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[51]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[50]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[50]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[49]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[49]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[48]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[48]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[47]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[47]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[46]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[46]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[45]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[45]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[44]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[44]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[43]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[43]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[42]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[42]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[41]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[41]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[40]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[40]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[39]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[39]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[38]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[38]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[37]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[37]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[36]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[36]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[35]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[35]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[34]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[34]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[33]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[33]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[32]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[32]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[31]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[31]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[30]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[30]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[29]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[29]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[28]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[28]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[27]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[27]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[26]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[26]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[25]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[25]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[24]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[24]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[23]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[23]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[22]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[22]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[21]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[21]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[20]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[20]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[19]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[19]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[18]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[18]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[17]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[17]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[16]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[16]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[15]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[15]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[14]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[14]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[13]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[13]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[12]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[12]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[11]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[11]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[10]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[10]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[9]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[9]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[8]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[8]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[7]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[7]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[6]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[6]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[5]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[5]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[4]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[4]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[3]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[3]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[2]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[2]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[1]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[1]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[0]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[0]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[127]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[127]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[126]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[126]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[125]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[125]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[124]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[124]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[123]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[123]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[122]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[122]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[121]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[121]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[120]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[120]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[119]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[119]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[118]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[118]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[117]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[117]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[116]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[116]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[115]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[115]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[114]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[114]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[113]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[113]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[112]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[112]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[111]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[111]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[110]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[110]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[109]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[109]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[108]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[108]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[107]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[107]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[106]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[106]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[105]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[105]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[104]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[104]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[103]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[103]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[102]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[102]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[101]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[101]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[100]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[100]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[99]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[99]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[98]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[98]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[97]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[97]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[96]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[96]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[95]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[95]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[94]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[94]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[93]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[93]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[92]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[92]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[91]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[91]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[90]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[90]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[89]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[89]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[88]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[88]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[87]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[87]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[86]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[86]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[85]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[85]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[84]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[84]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[83]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[83]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[82]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[82]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[81]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[81]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[80]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[80]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[79]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[79]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[78]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[78]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[77]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[77]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[76]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[76]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[75]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[75]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[74]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[74]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[73]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[73]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[72]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[72]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[71]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[71]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[70]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[70]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[69]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[69]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[68]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[68]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[67]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[67]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[66]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[66]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[65]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[65]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[64]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[64]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[63]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[63]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[62]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[62]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[61]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[61]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[60]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[60]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[59]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[59]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[58]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[58]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[57]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[57]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[56]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[56]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[55]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[55]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[54]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[54]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[53]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[53]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[52]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[52]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[51]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[51]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[50]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[50]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[49]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[49]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[48]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[48]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[47]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[47]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[46]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[46]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[45]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[45]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[44]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[44]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[43]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[43]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[42]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[42]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[41]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[41]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[40]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[40]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[39]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[39]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[38]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[38]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[37]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[37]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[36]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[36]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[35]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[35]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[34]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[34]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[33]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[33]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[32]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[32]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[31]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[31]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[30]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[30]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[29]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[29]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[28]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[28]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[27]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[27]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[26]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[26]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[25]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[25]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[24]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[24]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[23]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[23]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[22]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[22]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[21]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[21]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[20]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[20]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[19]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[19]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[18]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[18]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[17]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[17]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[16]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[16]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[15]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[15]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[14]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[14]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[13]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[13]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[12]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[12]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[11]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[11]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[10]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[10]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[9]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[9]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[8]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[8]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[7]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[7]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[6]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[6]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[5]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[5]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[4]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[4]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[3]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[3]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[2]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[2]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[1]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[1]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[0]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[0]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[31]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[31]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[30]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[30]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[29]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[29]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[28]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[28]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[27]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[27]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[26]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[26]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[25]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[25]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[24]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[24]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[23]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[23]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[22]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[22]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[21]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[21]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[20]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[20]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[19]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[19]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[18]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[18]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[17]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[17]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[16]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[16]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[15]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[15]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[14]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[14]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[13]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[13]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[12]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[12]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[11]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[11]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[10]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[10]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[9]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[9]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[8]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[8]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[7]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[7]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[6]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[6]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[5]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[5]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[4]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[4]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[3]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[3]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[2]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[2]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[1]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[1]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[0]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[0]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[31]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[31]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[30]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[30]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[29]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[29]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[28]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[28]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[27]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[27]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[26]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[26]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[25]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[25]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[24]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[24]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[23]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[23]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[22]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[22]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[21]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[21]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[20]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[20]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[19]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[19]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[18]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[18]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[17]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[17]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[16]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[16]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[15]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[15]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[14]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[14]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[13]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[13]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[12]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[12]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[11]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[11]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[10]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[10]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[9]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[9]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[8]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[8]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[7]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[7]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[6]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[6]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[5]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[5]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[4]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[4]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[3]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[3]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[2]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[2]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[1]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[1]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[0]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[0]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[3]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[3]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[2]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[2]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[1]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[1]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[0]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[0]}]
-set_timing_derate -early 0.9500
-set_timing_derate -late 1.0500
-###############################################################################
-# Design Rules
-###############################################################################
-set_max_transition 1.0000 [current_design]
-set_max_fanout 16.0000 [current_design]
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
index 6d4948912..7bca9fc95 100644
--- a/sdc/user_project_wrapper.sdc
+++ b/sdc/user_project_wrapper.sdc
@@ -1,2014 +1,145 @@
-###############################################################################
-# Created by write_sdc
-# Wed Jul 19 15:42:08 2023
-###############################################################################
-current_design user_project_wrapper
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name clk -period 25.0000 [get_ports {wb_clk_i}]
-set_clock_transition 0.1500 [get_clocks {clk}]
-set_clock_uncertainty 0.2500 clk
-set_propagated_clock [get_clocks {clk}]
-set_clock_latency -source -min 4.6500 [get_clocks {clk}]
-set_clock_latency -source -max 5.5700 [get_clocks {clk}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[0]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[0]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[100]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[100]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[101]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[101]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[102]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[102]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[103]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[103]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[104]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[104]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[105]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[105]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[106]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[106]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[107]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[107]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[108]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[108]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[109]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[109]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[10]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[10]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[110]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[110]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[111]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[111]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[112]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[112]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[113]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[113]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[114]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[114]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[115]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[115]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[116]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[116]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[117]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[117]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[118]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[118]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[119]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[119]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[11]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[11]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[120]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[120]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[121]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[121]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[122]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[122]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[123]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[123]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[124]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[124]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[125]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[125]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[126]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[126]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[127]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[127]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[12]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[12]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[13]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[13]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[14]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[14]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[15]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[15]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[16]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[16]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[17]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[17]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[18]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[18]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[19]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[19]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[1]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[1]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[20]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[20]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[21]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[21]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[22]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[22]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[23]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[23]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[24]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[24]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[25]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[25]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[26]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[26]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[27]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[27]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[28]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[28]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[29]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[29]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[2]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[2]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[30]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[30]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[31]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[31]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[32]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[32]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[33]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[33]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[34]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[34]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[35]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[35]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[36]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[36]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[37]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[37]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[38]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[38]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[39]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[39]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[3]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[3]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[40]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[40]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[41]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[41]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[42]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[42]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[43]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[43]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[44]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[44]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[45]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[45]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[46]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[46]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[47]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[47]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[48]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[48]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[49]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[49]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[4]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[4]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[50]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[50]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[51]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[51]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[52]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[52]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[53]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[53]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[54]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[54]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[55]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[55]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[56]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[56]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[57]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[57]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[58]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[58]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[59]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[59]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[5]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[5]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[60]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[60]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[61]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[61]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[62]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[62]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[63]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[63]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[64]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[64]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[65]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[65]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[66]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[66]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[67]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[67]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[68]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[68]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[69]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[69]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[6]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[6]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[70]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[70]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[71]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[71]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[72]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[72]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[73]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[73]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[74]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[74]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[75]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[75]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[76]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[76]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[77]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[77]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[78]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[78]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[79]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[79]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[7]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[7]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[80]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[80]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[81]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[81]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[82]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[82]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[83]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[83]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[84]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[84]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[85]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[85]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[86]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[86]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[87]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[87]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[88]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[88]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[89]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[89]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[8]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[8]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[90]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[90]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[91]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[91]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[92]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[92]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[93]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[93]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[94]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[94]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[95]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[95]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[96]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[96]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[97]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[97]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[98]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[98]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[99]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[99]}]
-set_input_delay 0.1800 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_in[9]}]
-set_input_delay 1.8700 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_in[9]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[0]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[0]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[100]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[100]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[101]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[101]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[102]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[102]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[103]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[103]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[104]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[104]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[105]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[105]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[106]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[106]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[107]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[107]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[108]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[108]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[109]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[109]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[10]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[10]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[110]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[110]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[111]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[111]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[112]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[112]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[113]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[113]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[114]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[114]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[115]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[115]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[116]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[116]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[117]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[117]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[118]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[118]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[119]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[119]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[11]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[11]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[120]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[120]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[121]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[121]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[122]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[122]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[123]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[123]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[124]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[124]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[125]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[125]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[126]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[126]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[127]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[127]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[12]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[12]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[13]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[13]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[14]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[14]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[15]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[15]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[16]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[16]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[17]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[17]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[18]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[18]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[19]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[19]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[1]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[1]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[20]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[20]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[21]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[21]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[22]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[22]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[23]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[23]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[24]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[24]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[25]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[25]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[26]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[26]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[27]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[27]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[28]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[28]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[29]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[29]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[2]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[2]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[30]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[30]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[31]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[31]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[32]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[32]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[33]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[33]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[34]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[34]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[35]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[35]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[36]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[36]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[37]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[37]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[38]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[38]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[39]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[39]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[3]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[3]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[40]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[40]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[41]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[41]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[42]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[42]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[43]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[43]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[44]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[44]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[45]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[45]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[46]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[46]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[47]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[47]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[48]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[48]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[49]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[49]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[4]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[4]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[50]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[50]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[51]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[51]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[52]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[52]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[53]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[53]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[54]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[54]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[55]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[55]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[56]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[56]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[57]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[57]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[58]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[58]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[59]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[59]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[5]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[5]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[60]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[60]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[61]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[61]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[62]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[62]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[63]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[63]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[64]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[64]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[65]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[65]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[66]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[66]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[67]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[67]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[68]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[68]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[69]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[69]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[6]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[6]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[70]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[70]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[71]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[71]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[72]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[72]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[73]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[73]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[74]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[74]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[75]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[75]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[76]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[76]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[77]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[77]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[78]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[78]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[79]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[79]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[7]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[7]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[80]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[80]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[81]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[81]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[82]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[82]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[83]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[83]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[84]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[84]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[85]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[85]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[86]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[86]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[87]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[87]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[88]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[88]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[89]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[89]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[8]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[8]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[90]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[90]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[91]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[91]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[92]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[92]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[93]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[93]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[94]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[94]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[95]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[95]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[96]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[96]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[97]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[97]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[98]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[98]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[99]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[99]}]
-set_input_delay 0.3000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_oenb[9]}]
-set_input_delay 1.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_oenb[9]}]
-set_input_delay 12.5000 -clock [get_clocks {clk}] -add_delay [get_ports {wb_rst_i}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[0]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[0]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[10]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[10]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[11]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[11]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[12]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[12]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[13]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[13]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[14]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[14]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[15]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[15]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[16]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[16]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[17]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[17]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[18]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[18]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[19]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[19]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[1]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[1]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[20]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[20]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[21]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[21]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[22]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[22]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[23]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[23]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[24]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[24]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[25]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[25]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[26]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[26]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[27]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[27]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[28]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[28]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[29]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[29]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[2]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[2]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[30]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[30]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[31]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[31]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[3]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[3]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[4]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[4]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[5]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[5]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[6]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[6]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[7]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[7]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[8]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[8]}]
-set_input_delay 0.7900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_adr_i[9]}]
-set_input_delay 3.8900 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_adr_i[9]}]
-set_input_delay 1.6900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_cyc_i}]
-set_input_delay 4.7400 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_cyc_i}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[0]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[0]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[10]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[10]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[11]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[11]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[12]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[12]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[13]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[13]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[14]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[14]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[15]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[15]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[16]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[16]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[17]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[17]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[18]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[18]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[19]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[19]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[1]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[1]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[20]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[20]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[21]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[21]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[22]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[22]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[23]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[23]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[24]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[24]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[25]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[25]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[26]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[26]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[27]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[27]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[28]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[28]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[29]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[29]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[2]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[2]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[30]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[30]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[31]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[31]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[3]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[3]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[4]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[4]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[5]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[5]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[6]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[6]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[7]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[7]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[8]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[8]}]
-set_input_delay 1.0400 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_i[9]}]
-set_input_delay 4.6100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_i[9]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[0]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[0]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[1]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[1]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[2]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[2]}]
-set_input_delay 1.1900 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_sel_i[3]}]
-set_input_delay 3.1700 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_sel_i[3]}]
-set_input_delay 1.8600 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_stb_i}]
-set_input_delay 4.1300 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_stb_i}]
-set_input_delay 1.6500 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_we_i}]
-set_input_delay 3.7400 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_we_i}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[0]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[0]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[100]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[100]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[101]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[101]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[102]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[102]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[103]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[103]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[104]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[104]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[105]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[105]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[106]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[106]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[107]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[107]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[108]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[108]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[109]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[109]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[10]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[10]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[110]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[110]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[111]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[111]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[112]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[112]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[113]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[113]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[114]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[114]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[115]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[115]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[116]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[116]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[117]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[117]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[118]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[118]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[119]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[119]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[11]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[11]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[120]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[120]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[121]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[121]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[122]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[122]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[123]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[123]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[124]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[124]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[125]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[125]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[126]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[126]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[127]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[127]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[12]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[12]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[13]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[13]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[14]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[14]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[15]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[15]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[16]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[16]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[17]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[17]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[18]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[18]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[19]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[19]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[1]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[1]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[20]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[20]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[21]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[21]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[22]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[22]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[23]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[23]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[24]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[24]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[25]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[25]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[26]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[26]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[27]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[27]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[28]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[28]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[29]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[29]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[2]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[2]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[30]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[30]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[31]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[31]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[32]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[32]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[33]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[33]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[34]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[34]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[35]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[35]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[36]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[36]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[37]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[37]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[38]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[38]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[39]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[39]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[3]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[3]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[40]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[40]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[41]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[41]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[42]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[42]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[43]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[43]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[44]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[44]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[45]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[45]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[46]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[46]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[47]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[47]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[48]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[48]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[49]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[49]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[4]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[4]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[50]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[50]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[51]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[51]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[52]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[52]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[53]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[53]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[54]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[54]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[55]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[55]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[56]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[56]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[57]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[57]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[58]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[58]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[59]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[59]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[5]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[5]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[60]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[60]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[61]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[61]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[62]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[62]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[63]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[63]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[64]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[64]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[65]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[65]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[66]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[66]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[67]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[67]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[68]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[68]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[69]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[69]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[6]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[6]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[70]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[70]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[71]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[71]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[72]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[72]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[73]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[73]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[74]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[74]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[75]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[75]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[76]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[76]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[77]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[77]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[78]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[78]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[79]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[79]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[7]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[7]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[80]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[80]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[81]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[81]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[82]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[82]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[83]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[83]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[84]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[84]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[85]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[85]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[86]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[86]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[87]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[87]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[88]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[88]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[89]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[89]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[8]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[8]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[90]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[90]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[91]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[91]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[92]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[92]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[93]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[93]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[94]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[94]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[95]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[95]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[96]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[96]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[97]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[97]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[98]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[98]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[99]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[99]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {la_data_out[9]}]
-set_output_delay 1.0000 -clock [get_clocks {clk}] -max -add_delay [get_ports {la_data_out[9]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {user_irq[0]}]
-set_output_delay 0.7000 -clock [get_clocks {clk}] -max -add_delay [get_ports {user_irq[0]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {user_irq[1]}]
-set_output_delay 0.7000 -clock [get_clocks {clk}] -max -add_delay [get_ports {user_irq[1]}]
-set_output_delay 0.0000 -clock [get_clocks {clk}] -min -add_delay [get_ports {user_irq[2]}]
-set_output_delay 0.7000 -clock [get_clocks {clk}] -max -add_delay [get_ports {user_irq[2]}]
-set_output_delay 1.3700 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_ack_o}]
-set_output_delay 8.4100 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_ack_o}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[0]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[0]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[10]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[10]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[11]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[11]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[12]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[12]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[13]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[13]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[14]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[14]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[15]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[15]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[16]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[16]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[17]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[17]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[18]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[18]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[19]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[19]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[1]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[1]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[20]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[20]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[21]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[21]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[22]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[22]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[23]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[23]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[24]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[24]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[25]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[25]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[26]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[26]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[27]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[27]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[28]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[28]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[29]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[29]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[2]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[2]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[30]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[30]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[31]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[31]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[3]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[3]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[4]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[4]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[5]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[5]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[6]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[6]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[7]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[7]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[8]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[8]}]
-set_output_delay 1.1300 -clock [get_clocks {clk}] -min -add_delay [get_ports {wbs_dat_o[9]}]
-set_output_delay 3.6200 -clock [get_clocks {clk}] -max -add_delay [get_ports {wbs_dat_o[9]}]
-set_multicycle_path -hold\
-    -through [list [get_ports {wbs_ack_o}]\
-           [get_ports {wbs_cyc_i}]\
-           [get_ports {wbs_stb_i}]] 1
-set_multicycle_path -setup\
-    -through [list [get_ports {wbs_ack_o}]\
-           [get_ports {wbs_cyc_i}]\
-           [get_ports {wbs_stb_i}]] 2
-###############################################################################
-# Environment
-###############################################################################
-set_load -pin_load 0.1900 [get_ports {wbs_ack_o}]
-set_load -pin_load 0.1900 [get_ports {analog_io[28]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[27]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[26]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[25]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[24]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[23]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[22]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[21]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[20]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[19]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[18]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[17]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[16]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[15]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[14]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[13]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[12]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[11]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[10]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[9]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[8]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[7]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[6]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[5]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[4]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[3]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[2]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[1]}]
-set_load -pin_load 0.1900 [get_ports {analog_io[0]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[37]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[36]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[35]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[34]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[33]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[32]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[31]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[30]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[29]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[28]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[27]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[26]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[25]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[24]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[23]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[22]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[21]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[20]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[19]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[18]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[17]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[16]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[15]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[14]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[13]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[12]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[11]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[10]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[9]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[8]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[7]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[6]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[5]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[4]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[3]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[2]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[1]}]
-set_load -pin_load 0.1900 [get_ports {io_oeb[0]}]
-set_load -pin_load 0.1900 [get_ports {io_out[37]}]
-set_load -pin_load 0.1900 [get_ports {io_out[36]}]
-set_load -pin_load 0.1900 [get_ports {io_out[35]}]
-set_load -pin_load 0.1900 [get_ports {io_out[34]}]
-set_load -pin_load 0.1900 [get_ports {io_out[33]}]
-set_load -pin_load 0.1900 [get_ports {io_out[32]}]
-set_load -pin_load 0.1900 [get_ports {io_out[31]}]
-set_load -pin_load 0.1900 [get_ports {io_out[30]}]
-set_load -pin_load 0.1900 [get_ports {io_out[29]}]
-set_load -pin_load 0.1900 [get_ports {io_out[28]}]
-set_load -pin_load 0.1900 [get_ports {io_out[27]}]
-set_load -pin_load 0.1900 [get_ports {io_out[26]}]
-set_load -pin_load 0.1900 [get_ports {io_out[25]}]
-set_load -pin_load 0.1900 [get_ports {io_out[24]}]
-set_load -pin_load 0.1900 [get_ports {io_out[23]}]
-set_load -pin_load 0.1900 [get_ports {io_out[22]}]
-set_load -pin_load 0.1900 [get_ports {io_out[21]}]
-set_load -pin_load 0.1900 [get_ports {io_out[20]}]
-set_load -pin_load 0.1900 [get_ports {io_out[19]}]
-set_load -pin_load 0.1900 [get_ports {io_out[18]}]
-set_load -pin_load 0.1900 [get_ports {io_out[17]}]
-set_load -pin_load 0.1900 [get_ports {io_out[16]}]
-set_load -pin_load 0.1900 [get_ports {io_out[15]}]
-set_load -pin_load 0.1900 [get_ports {io_out[14]}]
-set_load -pin_load 0.1900 [get_ports {io_out[13]}]
-set_load -pin_load 0.1900 [get_ports {io_out[12]}]
-set_load -pin_load 0.1900 [get_ports {io_out[11]}]
-set_load -pin_load 0.1900 [get_ports {io_out[10]}]
-set_load -pin_load 0.1900 [get_ports {io_out[9]}]
-set_load -pin_load 0.1900 [get_ports {io_out[8]}]
-set_load -pin_load 0.1900 [get_ports {io_out[7]}]
-set_load -pin_load 0.1900 [get_ports {io_out[6]}]
-set_load -pin_load 0.1900 [get_ports {io_out[5]}]
-set_load -pin_load 0.1900 [get_ports {io_out[4]}]
-set_load -pin_load 0.1900 [get_ports {io_out[3]}]
-set_load -pin_load 0.1900 [get_ports {io_out[2]}]
-set_load -pin_load 0.1900 [get_ports {io_out[1]}]
-set_load -pin_load 0.1900 [get_ports {io_out[0]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[127]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[126]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[125]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[124]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[123]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[122]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[121]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[120]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[119]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[118]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[117]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[116]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[115]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[114]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[113]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[112]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[111]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[110]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[109]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[108]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[107]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[106]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[105]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[104]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[103]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[102]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[101]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[100]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[99]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[98]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[97]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[96]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[95]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[94]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[93]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[92]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[91]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[90]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[89]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[88]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[87]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[86]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[85]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[84]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[83]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[82]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[81]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[80]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[79]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[78]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[77]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[76]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[75]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[74]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[73]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[72]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[71]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[70]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[69]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[68]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[67]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[66]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[65]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[64]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[63]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[62]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[61]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[60]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[59]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[58]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[57]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[56]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[55]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[54]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[53]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[52]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[51]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[50]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[49]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[48]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[47]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[46]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[45]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[44]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[43]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[42]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[41]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[40]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[39]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[38]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[37]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[36]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[35]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[34]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[33]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[32]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[31]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[30]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[29]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[28]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[27]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[26]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[25]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[24]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[23]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[22]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[21]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[20]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[19]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[18]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[17]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[16]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[15]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[14]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[13]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[12]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[11]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[10]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[9]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[8]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[7]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[6]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[5]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[4]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[3]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[2]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[1]}]
-set_load -pin_load 0.1900 [get_ports {la_data_out[0]}]
-set_load -pin_load 0.1900 [get_ports {user_irq[2]}]
-set_load -pin_load 0.1900 [get_ports {user_irq[1]}]
-set_load -pin_load 0.1900 [get_ports {user_irq[0]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[31]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[30]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[29]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[28]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[27]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[26]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[25]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[24]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[23]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[22]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[21]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[20]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[19]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[18]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[17]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[16]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[15]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[14]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[13]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[12]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[11]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[10]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[9]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[8]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[7]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[6]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[5]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[4]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[3]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[2]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[1]}]
-set_load -pin_load 0.1900 [get_ports {wbs_dat_o[0]}]
-set_input_transition 0.6100 [get_ports {wb_clk_i}]
-set_input_transition -min 0.0900 [get_ports {wbs_cyc_i}]
-set_input_transition -max 0.1700 [get_ports {wbs_cyc_i}]
-set_input_transition 0.1500 [get_ports {wbs_stb_i}]
-set_input_transition -min 0.0900 [get_ports {wbs_we_i}]
-set_input_transition -max 0.1400 [get_ports {wbs_we_i}]
-set_input_transition -min 0.0500 [get_ports {io_in[37]}]
-set_input_transition -max 0.3800 [get_ports {io_in[37]}]
-set_input_transition -min 0.0500 [get_ports {io_in[36]}]
-set_input_transition -max 0.3800 [get_ports {io_in[36]}]
-set_input_transition -min 0.0500 [get_ports {io_in[35]}]
-set_input_transition -max 0.3800 [get_ports {io_in[35]}]
-set_input_transition -min 0.0500 [get_ports {io_in[34]}]
-set_input_transition -max 0.3800 [get_ports {io_in[34]}]
-set_input_transition -min 0.0500 [get_ports {io_in[33]}]
-set_input_transition -max 0.3800 [get_ports {io_in[33]}]
-set_input_transition -min 0.0500 [get_ports {io_in[32]}]
-set_input_transition -max 0.3800 [get_ports {io_in[32]}]
-set_input_transition -min 0.0500 [get_ports {io_in[31]}]
-set_input_transition -max 0.3800 [get_ports {io_in[31]}]
-set_input_transition -min 0.0500 [get_ports {io_in[30]}]
-set_input_transition -max 0.3800 [get_ports {io_in[30]}]
-set_input_transition -min 0.0500 [get_ports {io_in[29]}]
-set_input_transition -max 0.3800 [get_ports {io_in[29]}]
-set_input_transition -min 0.0500 [get_ports {io_in[28]}]
-set_input_transition -max 0.3800 [get_ports {io_in[28]}]
-set_input_transition -min 0.0500 [get_ports {io_in[27]}]
-set_input_transition -max 0.3800 [get_ports {io_in[27]}]
-set_input_transition -min 0.0500 [get_ports {io_in[26]}]
-set_input_transition -max 0.3800 [get_ports {io_in[26]}]
-set_input_transition -min 0.0500 [get_ports {io_in[25]}]
-set_input_transition -max 0.3800 [get_ports {io_in[25]}]
-set_input_transition -min 0.0500 [get_ports {io_in[24]}]
-set_input_transition -max 0.3800 [get_ports {io_in[24]}]
-set_input_transition -min 0.0500 [get_ports {io_in[23]}]
-set_input_transition -max 0.3800 [get_ports {io_in[23]}]
-set_input_transition -min 0.0500 [get_ports {io_in[22]}]
-set_input_transition -max 0.3800 [get_ports {io_in[22]}]
-set_input_transition -min 0.0500 [get_ports {io_in[21]}]
-set_input_transition -max 0.3800 [get_ports {io_in[21]}]
-set_input_transition -min 0.0500 [get_ports {io_in[20]}]
-set_input_transition -max 0.3800 [get_ports {io_in[20]}]
-set_input_transition -min 0.0500 [get_ports {io_in[19]}]
-set_input_transition -max 0.3800 [get_ports {io_in[19]}]
-set_input_transition -min 0.0500 [get_ports {io_in[18]}]
-set_input_transition -max 0.3800 [get_ports {io_in[18]}]
-set_input_transition -min 0.0500 [get_ports {io_in[17]}]
-set_input_transition -max 0.3800 [get_ports {io_in[17]}]
-set_input_transition -min 0.0500 [get_ports {io_in[16]}]
-set_input_transition -max 0.3800 [get_ports {io_in[16]}]
-set_input_transition -min 0.0500 [get_ports {io_in[15]}]
-set_input_transition -max 0.3800 [get_ports {io_in[15]}]
-set_input_transition -min 0.0500 [get_ports {io_in[14]}]
-set_input_transition -max 0.3800 [get_ports {io_in[14]}]
-set_input_transition -min 0.0500 [get_ports {io_in[13]}]
-set_input_transition -max 0.3800 [get_ports {io_in[13]}]
-set_input_transition -min 0.0500 [get_ports {io_in[12]}]
-set_input_transition -max 0.3800 [get_ports {io_in[12]}]
-set_input_transition -min 0.0500 [get_ports {io_in[11]}]
-set_input_transition -max 0.3800 [get_ports {io_in[11]}]
-set_input_transition -min 0.0500 [get_ports {io_in[10]}]
-set_input_transition -max 0.3800 [get_ports {io_in[10]}]
-set_input_transition -min 0.0500 [get_ports {io_in[9]}]
-set_input_transition -max 0.3800 [get_ports {io_in[9]}]
-set_input_transition -min 0.0500 [get_ports {io_in[8]}]
-set_input_transition -max 0.3800 [get_ports {io_in[8]}]
-set_input_transition -min 0.0500 [get_ports {io_in[7]}]
-set_input_transition -max 0.3800 [get_ports {io_in[7]}]
-set_input_transition -min 0.0500 [get_ports {io_in[6]}]
-set_input_transition -max 0.3800 [get_ports {io_in[6]}]
-set_input_transition -min 0.0500 [get_ports {io_in[5]}]
-set_input_transition -max 0.3800 [get_ports {io_in[5]}]
-set_input_transition -min 0.0500 [get_ports {io_in[4]}]
-set_input_transition -max 0.3800 [get_ports {io_in[4]}]
-set_input_transition -min 0.0500 [get_ports {io_in[3]}]
-set_input_transition -max 0.3800 [get_ports {io_in[3]}]
-set_input_transition -min 0.0500 [get_ports {io_in[2]}]
-set_input_transition -max 0.3800 [get_ports {io_in[2]}]
-set_input_transition -min 0.0500 [get_ports {io_in[1]}]
-set_input_transition -max 0.3800 [get_ports {io_in[1]}]
-set_input_transition -min 0.0500 [get_ports {io_in[0]}]
-set_input_transition -max 0.3800 [get_ports {io_in[0]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[127]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[127]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[126]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[126]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[125]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[125]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[124]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[124]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[123]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[123]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[122]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[122]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[121]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[121]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[120]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[120]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[119]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[119]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[118]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[118]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[117]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[117]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[116]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[116]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[115]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[115]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[114]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[114]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[113]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[113]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[112]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[112]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[111]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[111]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[110]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[110]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[109]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[109]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[108]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[108]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[107]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[107]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[106]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[106]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[105]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[105]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[104]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[104]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[103]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[103]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[102]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[102]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[101]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[101]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[100]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[100]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[99]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[99]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[98]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[98]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[97]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[97]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[96]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[96]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[95]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[95]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[94]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[94]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[93]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[93]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[92]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[92]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[91]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[91]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[90]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[90]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[89]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[89]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[88]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[88]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[87]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[87]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[86]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[86]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[85]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[85]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[84]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[84]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[83]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[83]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[82]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[82]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[81]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[81]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[80]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[80]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[79]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[79]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[78]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[78]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[77]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[77]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[76]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[76]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[75]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[75]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[74]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[74]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[73]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[73]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[72]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[72]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[71]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[71]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[70]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[70]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[69]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[69]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[68]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[68]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[67]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[67]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[66]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[66]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[65]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[65]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[64]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[64]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[63]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[63]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[62]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[62]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[61]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[61]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[60]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[60]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[59]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[59]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[58]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[58]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[57]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[57]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[56]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[56]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[55]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[55]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[54]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[54]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[53]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[53]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[52]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[52]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[51]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[51]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[50]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[50]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[49]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[49]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[48]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[48]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[47]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[47]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[46]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[46]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[45]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[45]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[44]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[44]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[43]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[43]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[42]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[42]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[41]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[41]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[40]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[40]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[39]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[39]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[38]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[38]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[37]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[37]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[36]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[36]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[35]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[35]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[34]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[34]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[33]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[33]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[32]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[32]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[31]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[31]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[30]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[30]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[29]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[29]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[28]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[28]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[27]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[27]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[26]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[26]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[25]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[25]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[24]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[24]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[23]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[23]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[22]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[22]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[21]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[21]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[20]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[20]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[19]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[19]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[18]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[18]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[17]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[17]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[16]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[16]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[15]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[15]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[14]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[14]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[13]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[13]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[12]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[12]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[11]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[11]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[10]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[10]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[9]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[9]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[8]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[8]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[7]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[7]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[6]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[6]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[5]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[5]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[4]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[4]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[3]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[3]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[2]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[2]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[1]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[1]}]
-set_input_transition -min 0.0700 [get_ports {la_data_in[0]}]
-set_input_transition -max 0.8600 [get_ports {la_data_in[0]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[127]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[127]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[126]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[126]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[125]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[125]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[124]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[124]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[123]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[123]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[122]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[122]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[121]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[121]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[120]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[120]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[119]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[119]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[118]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[118]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[117]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[117]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[116]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[116]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[115]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[115]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[114]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[114]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[113]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[113]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[112]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[112]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[111]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[111]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[110]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[110]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[109]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[109]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[108]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[108]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[107]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[107]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[106]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[106]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[105]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[105]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[104]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[104]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[103]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[103]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[102]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[102]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[101]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[101]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[100]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[100]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[99]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[99]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[98]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[98]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[97]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[97]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[96]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[96]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[95]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[95]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[94]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[94]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[93]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[93]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[92]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[92]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[91]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[91]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[90]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[90]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[89]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[89]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[88]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[88]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[87]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[87]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[86]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[86]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[85]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[85]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[84]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[84]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[83]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[83]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[82]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[82]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[81]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[81]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[80]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[80]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[79]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[79]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[78]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[78]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[77]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[77]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[76]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[76]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[75]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[75]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[74]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[74]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[73]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[73]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[72]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[72]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[71]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[71]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[70]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[70]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[69]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[69]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[68]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[68]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[67]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[67]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[66]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[66]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[65]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[65]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[64]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[64]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[63]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[63]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[62]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[62]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[61]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[61]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[60]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[60]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[59]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[59]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[58]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[58]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[57]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[57]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[56]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[56]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[55]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[55]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[54]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[54]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[53]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[53]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[52]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[52]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[51]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[51]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[50]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[50]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[49]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[49]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[48]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[48]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[47]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[47]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[46]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[46]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[45]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[45]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[44]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[44]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[43]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[43]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[42]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[42]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[41]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[41]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[40]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[40]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[39]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[39]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[38]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[38]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[37]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[37]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[36]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[36]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[35]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[35]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[34]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[34]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[33]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[33]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[32]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[32]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[31]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[31]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[30]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[30]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[29]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[29]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[28]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[28]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[27]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[27]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[26]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[26]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[25]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[25]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[24]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[24]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[23]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[23]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[22]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[22]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[21]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[21]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[20]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[20]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[19]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[19]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[18]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[18]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[17]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[17]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[16]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[16]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[15]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[15]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[14]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[14]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[13]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[13]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[12]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[12]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[11]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[11]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[10]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[10]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[9]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[9]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[8]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[8]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[7]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[7]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[6]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[6]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[5]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[5]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[4]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[4]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[3]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[3]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[2]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[2]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[1]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[1]}]
-set_input_transition -min 0.0600 [get_ports {la_oenb[0]}]
-set_input_transition -max 0.9700 [get_ports {la_oenb[0]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[31]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[31]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[30]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[30]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[29]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[29]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[28]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[28]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[27]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[27]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[26]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[26]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[25]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[25]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[24]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[24]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[23]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[23]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[22]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[22]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[21]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[21]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[20]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[20]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[19]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[19]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[18]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[18]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[17]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[17]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[16]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[16]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[15]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[15]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[14]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[14]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[13]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[13]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[12]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[12]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[11]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[11]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[10]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[10]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[9]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[9]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[8]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[8]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[7]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[7]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[6]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[6]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[5]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[5]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[4]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[4]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[3]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[3]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[2]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[2]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[1]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[1]}]
-set_input_transition -min 0.0700 [get_ports {wbs_adr_i[0]}]
-set_input_transition -max 0.9200 [get_ports {wbs_adr_i[0]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[31]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[31]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[30]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[30]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[29]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[29]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[28]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[28]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[27]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[27]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[26]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[26]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[25]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[25]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[24]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[24]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[23]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[23]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[22]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[22]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[21]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[21]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[20]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[20]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[19]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[19]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[18]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[18]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[17]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[17]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[16]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[16]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[15]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[15]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[14]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[14]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[13]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[13]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[12]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[12]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[11]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[11]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[10]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[10]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[9]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[9]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[8]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[8]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[7]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[7]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[6]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[6]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[5]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[5]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[4]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[4]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[3]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[3]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[2]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[2]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[1]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[1]}]
-set_input_transition -min 0.0700 [get_ports {wbs_dat_i[0]}]
-set_input_transition -max 0.8400 [get_ports {wbs_dat_i[0]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[3]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[3]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[2]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[2]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[1]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[1]}]
-set_input_transition -min 0.0900 [get_ports {wbs_sel_i[0]}]
-set_input_transition -max 0.1800 [get_ports {wbs_sel_i[0]}]
-set_timing_derate -early 0.9500
-set_timing_derate -late 1.0500
-###############################################################################
-# Design Rules
-###############################################################################
-set_max_transition 1.5000 [current_design]
-set_max_fanout 10.0000 [current_design]
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]
diff --git a/signoff/user_proj_example/openlane-signoff/drc.klayout.xml b/signoff/user_proj_example/openlane-signoff/drc.klayout.xml
new file mode 100644
index 000000000..2824db178
--- /dev/null
+++ b/signoff/user_proj_example/openlane-signoff/drc.klayout.xml
@@ -0,0 +1 @@
+<report-database><cells><cell><name>user_proj_example</name></cell></cells><categories></categories><items></items></report-database>
\ No newline at end of file
diff --git a/signoff/user_proj_example/openlane-signoff/drc.rpt b/signoff/user_proj_example/openlane-signoff/drc.rpt
new file mode 100644
index 000000000..d3d464682
--- /dev/null
+++ b/signoff/user_proj_example/openlane-signoff/drc.rpt
@@ -0,0 +1,5 @@
+user_proj_example
+----------------------------------------
+[INFO] COUNT: 0
+[INFO] Should be divided by 3 or 4
+
diff --git a/signoff/user_proj_example/openlane-signoff/lvs.rpt b/signoff/user_proj_example/openlane-signoff/lvs.rpt
new file mode 100644
index 000000000..30bca5fb3
--- /dev/null
+++ b/signoff/user_proj_example/openlane-signoff/lvs.rpt
@@ -0,0 +1,3067 @@
+
+Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__pfet_01v8_hvt     |Circuit 2: sky130_fd_pr__pfet_01v8_hvt     
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
+
+Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+Warning: Equate pins:  cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_pr__nfet_01v8         |Circuit 2: sky130_fd_pr__nfet_01v8         
+-------------------------------------------|-------------------------------------------
+1                                          |1                                          
+2                                          |2                                          
+3                                          |3                                          
+4                                          |4                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_ef_sc_hd__decap_12       |Circuit 2: sky130_ef_sc_hd__decap_12       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1)            |sky130_fd_pr__pfet_01v8_hvt (1)            
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_ef_sc_hd__decap_12       |Circuit 2: sky130_ef_sc_hd__decap_12       
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_ef_sc_hd__decap_12 and sky130_ef_sc_hd__decap_12 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_6        |Circuit 2: sky130_fd_sc_hd__decap_6        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1)            |sky130_fd_pr__pfet_01v8_hvt (1)            
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_6        |Circuit 2: sky130_fd_sc_hd__decap_6        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_8        |Circuit 2: sky130_fd_sc_hd__decap_8        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1)            |sky130_fd_pr__pfet_01v8_hvt (1)            
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_8        |Circuit 2: sky130_fd_sc_hd__decap_8        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_3        |Circuit 2: sky130_fd_sc_hd__decap_3        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1)            |sky130_fd_pr__pfet_01v8_hvt (1)            
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_3        |Circuit 2: sky130_fd_sc_hd__decap_3        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
+
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
+Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__diode_2        |Circuit 2: sky130_fd_sc_hd__diode_2        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__diode_pw2nd_05v5 (1)         |sky130_fd_pr__diode_pw2nd_05v5 (1)         
+Number of devices: 1                       |Number of devices: 1                       
+Number of nets: 2                          |Number of nets: 2                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__diode_2        |Circuit 2: sky130_fd_sc_hd__diode_2        
+-------------------------------------------|-------------------------------------------
+VNB                                        |VNB                                        
+DIODE                                      |DIODE                                      
+VGND                                       |VGND                                       
+VPB                                        |VPB                                        
+VPWR                                       |VPWR                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_1          |Circuit 2: sky130_fd_sc_hd__buf_1          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2)            |sky130_fd_pr__pfet_01v8_hvt (2)            
+sky130_fd_pr__nfet_01v8 (2)                |sky130_fd_pr__nfet_01v8 (2)                
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_1          |Circuit 2: sky130_fd_sc_hd__buf_1          
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+X                                          |X                                          
+VNB                                        |VNB                                        
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_1 and sky130_fd_sc_hd__buf_1 are equivalent.
+
+Class sky130_fd_sc_hd__buf_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__buf_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_2          |Circuit 2: sky130_fd_sc_hd__buf_2          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2)         |sky130_fd_pr__pfet_01v8_hvt (3->2)         
+sky130_fd_pr__nfet_01v8 (3->2)             |sky130_fd_pr__nfet_01v8 (3->2)             
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_2          |Circuit 2: sky130_fd_sc_hd__buf_2          
+-------------------------------------------|-------------------------------------------
+X                                          |X                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent.
+
+Class sky130_fd_sc_hd__dfxtp_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__dfxtp_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_2        |Circuit 2: sky130_fd_sc_hd__dfxtp_2        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (13->12)           |sky130_fd_pr__nfet_01v8 (13->12)           
+sky130_fd_pr__pfet_01v8_hvt (13->12)       |sky130_fd_pr__pfet_01v8_hvt (13->12)       
+Number of devices: 24                      |Number of devices: 24                      
+Number of nets: 18                         |Number of nets: 18                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_2        |Circuit 2: sky130_fd_sc_hd__dfxtp_2        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+D                                          |D                                          
+Q                                          |Q                                          
+CLK                                        |CLK                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_2 and sky130_fd_sc_hd__dfxtp_2 are equivalent.
+
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
+Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__conb_1         |Circuit 2: sky130_fd_sc_hd__conb_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__res_generic_po (2)           |sky130_fd_pr__res_generic_po (2)           
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Resolving symmetries by property value.
+Resolving symmetries by pin name.
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__conb_1         |Circuit 2: sky130_fd_sc_hd__conb_1         
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+LO                                         |LO                                         
+HI                                         |HI                                         
+VPWR                                       |VPWR                                       
+VNB                                        |VNB                                        
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__decap_4        |Circuit 2: sky130_fd_sc_hd__decap_4        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (1)            |sky130_fd_pr__pfet_01v8_hvt (1)            
+sky130_fd_pr__nfet_01v8 (1)                |sky130_fd_pr__nfet_01v8 (1)                
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 4                          |Number of nets: 4                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__decap_4        |Circuit 2: sky130_fd_sc_hd__decap_4        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1  |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1  
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4)            |sky130_fd_pr__pfet_01v8_hvt (4)            
+sky130_fd_pr__nfet_01v8 (4)                |sky130_fd_pr__nfet_01v8 (4)                
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 9                          |Number of nets: 9                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1  |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1  
+-------------------------------------------|-------------------------------------------
+A                                          |A                                          
+X                                          |X                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlygate4sd3_1 and sky130_fd_sc_hd__dlygate4sd3_1 are equivalent.
+
+Class sky130_fd_sc_hd__dfxtp_4 (0):  Merged 6 parallel devices.
+Class sky130_fd_sc_hd__dfxtp_4 (1):  Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_4        |Circuit 2: sky130_fd_sc_hd__dfxtp_4        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (15->12)       |sky130_fd_pr__pfet_01v8_hvt (15->12)       
+sky130_fd_pr__nfet_01v8 (15->12)           |sky130_fd_pr__nfet_01v8 (15->12)           
+Number of devices: 24                      |Number of devices: 24                      
+Number of nets: 18                         |Number of nets: 18                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_4        |Circuit 2: sky130_fd_sc_hd__dfxtp_4        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+Q                                          |Q                                          
+D                                          |D                                          
+CLK                                        |CLK                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_4 and sky130_fd_sc_hd__dfxtp_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_1         |Circuit 2: sky130_fd_sc_hd__and3_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4)            |sky130_fd_pr__pfet_01v8_hvt (4)            
+sky130_fd_pr__nfet_01v8 (4)                |sky130_fd_pr__nfet_01v8 (4)                
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_1         |Circuit 2: sky130_fd_sc_hd__and3_1         
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+A                                          |A                                          
+B                                          |B                                          
+C                                          |C                                          
+X                                          |X                                          
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_1 and sky130_fd_sc_hd__and3_1 are equivalent.
+
+Class sky130_fd_sc_hd__buf_12 (0):  Merged 28 parallel devices.
+Class sky130_fd_sc_hd__buf_12 (1):  Merged 28 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_12         |Circuit 2: sky130_fd_sc_hd__buf_12         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->2)            |sky130_fd_pr__nfet_01v8 (16->2)            
+sky130_fd_pr__pfet_01v8_hvt (16->2)        |sky130_fd_pr__pfet_01v8_hvt (16->2)        
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_12         |Circuit 2: sky130_fd_sc_hd__buf_12         
+-------------------------------------------|-------------------------------------------
+X                                          |X                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+A                                          |A                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_12 and sky130_fd_sc_hd__buf_12 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_16 (0):  Merged 36 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_16 (1):  Merged 36 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16      |Circuit 2: sky130_fd_sc_hd__clkbuf_16      
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (20->2)        |sky130_fd_pr__pfet_01v8_hvt (20->2)        
+sky130_fd_pr__nfet_01v8 (20->2)            |sky130_fd_pr__nfet_01v8 (20->2)            
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_16      |Circuit 2: sky130_fd_sc_hd__clkbuf_16      
+-------------------------------------------|-------------------------------------------
+VPWR                                       |VPWR                                       
+X                                          |X                                          
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+A                                          |A                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2_1         |Circuit 2: sky130_fd_sc_hd__and2_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3)            |sky130_fd_pr__pfet_01v8_hvt (3)            
+sky130_fd_pr__nfet_01v8 (3)                |sky130_fd_pr__nfet_01v8 (3)                
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 9                          |Number of nets: 9                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2_1         |Circuit 2: sky130_fd_sc_hd__and2_1         
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+X                                          |X                                          
+A                                          |A                                          
+B                                          |B                                          
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__mux2_1         |Circuit 2: sky130_fd_sc_hd__mux2_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6)            |sky130_fd_pr__pfet_01v8_hvt (6)            
+sky130_fd_pr__nfet_01v8 (6)                |sky130_fd_pr__nfet_01v8 (6)                
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 14                         |Number of nets: 14                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__mux2_1         |Circuit 2: sky130_fd_sc_hd__mux2_1         
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+A0                                         |A0                                         
+A1                                         |A1                                         
+X                                          |X                                          
+VPWR                                       |VPWR                                       
+S                                          |S                                          
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a31o_1         |Circuit 2: sky130_fd_sc_hd__a31o_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5)            |sky130_fd_pr__pfet_01v8_hvt (5)            
+sky130_fd_pr__nfet_01v8 (5)                |sky130_fd_pr__nfet_01v8 (5)                
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 13                         |Number of nets: 13                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a31o_1         |Circuit 2: sky130_fd_sc_hd__a31o_1         
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+B1                                         |B1                                         
+X                                          |X                                          
+A2                                         |A2                                         
+A1                                         |A1                                         
+A3                                         |A3                                         
+VNB                                        |VNB                                        
+VPB                                        |VPB                                        
+VPWR                                       |VPWR                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a31o_1 and sky130_fd_sc_hd__a31o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a32o_1         |Circuit 2: sky130_fd_sc_hd__a32o_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6)                |sky130_fd_pr__nfet_01v8 (6)                
+sky130_fd_pr__pfet_01v8_hvt (6)            |sky130_fd_pr__pfet_01v8_hvt (6)            
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 15                         |Number of nets: 15                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a32o_1         |Circuit 2: sky130_fd_sc_hd__a32o_1         
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+B2                                         |B2                                         
+X                                          |X                                          
+B1                                         |B1                                         
+A2                                         |A2                                         
+A3                                         |A3                                         
+A1                                         |A1                                         
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a32o_1 and sky130_fd_sc_hd__a32o_1 are equivalent.
+
+Class sky130_fd_sc_hd__inv_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__inv_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_2          |Circuit 2: sky130_fd_sc_hd__inv_2          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2->1)         |sky130_fd_pr__pfet_01v8_hvt (2->1)         
+sky130_fd_pr__nfet_01v8 (2->1)             |sky130_fd_pr__nfet_01v8 (2->1)             
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 6                          |Number of nets: 6                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_2          |Circuit 2: sky130_fd_sc_hd__inv_2          
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+Y                                          |Y                                          
+A                                          |A                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1        |Circuit 2: sky130_fd_sc_hd__dfxtp_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (12)               |sky130_fd_pr__nfet_01v8 (12)               
+sky130_fd_pr__pfet_01v8_hvt (12)           |sky130_fd_pr__pfet_01v8_hvt (12)           
+Number of devices: 24                      |Number of devices: 24                      
+Number of nets: 18                         |Number of nets: 18                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dfxtp_1        |Circuit 2: sky130_fd_sc_hd__dfxtp_1        
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+D                                          |D                                          
+Q                                          |Q                                          
+CLK                                        |CLK                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dfxtp_1 and sky130_fd_sc_hd__dfxtp_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__or2_1          |Circuit 2: sky130_fd_sc_hd__or2_1          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (3)                |sky130_fd_pr__nfet_01v8 (3)                
+sky130_fd_pr__pfet_01v8_hvt (3)            |sky130_fd_pr__pfet_01v8_hvt (3)            
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 9                          |Number of nets: 9                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__or2_1          |Circuit 2: sky130_fd_sc_hd__or2_1          
+-------------------------------------------|-------------------------------------------
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+X                                          |X                                          
+B                                          |B                                          
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__or2_1 and sky130_fd_sc_hd__or2_1 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_8 (0):  Merged 16 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_8 (1):  Merged 16 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8       |Circuit 2: sky130_fd_sc_hd__clkbuf_8       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (10->2)        |sky130_fd_pr__pfet_01v8_hvt (10->2)        
+sky130_fd_pr__nfet_01v8 (10->2)            |sky130_fd_pr__nfet_01v8 (10->2)            
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_8       |Circuit 2: sky130_fd_sc_hd__clkbuf_8       
+-------------------------------------------|-------------------------------------------
+X                                          |X                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand4_1        |Circuit 2: sky130_fd_sc_hd__nand4_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4)            |sky130_fd_pr__pfet_01v8_hvt (4)            
+sky130_fd_pr__nfet_01v8 (4)                |sky130_fd_pr__nfet_01v8 (4)                
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 12                         |Number of nets: 12                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand4_1        |Circuit 2: sky130_fd_sc_hd__nand4_1        
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+A                                          |A                                          
+C                                          |C                                          
+B                                          |B                                          
+D                                          |D                                          
+Y                                          |Y                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand4_1 and sky130_fd_sc_hd__nand4_1 are equivalent.
+
+Class sky130_fd_sc_hd__and4_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4_2         |Circuit 2: sky130_fd_sc_hd__and4_2         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->5)             |sky130_fd_pr__nfet_01v8 (6->5)             
+sky130_fd_pr__pfet_01v8_hvt (6->5)         |sky130_fd_pr__pfet_01v8_hvt (6->5)         
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 13                         |Number of nets: 13                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4_2         |Circuit 2: sky130_fd_sc_hd__and4_2         
+-------------------------------------------|-------------------------------------------
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+VGND                                       |VGND                                       
+X                                          |X                                          
+A                                          |A                                          
+C                                          |C                                          
+B                                          |B                                          
+D                                          |D                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4_2 and sky130_fd_sc_hd__and4_2 are equivalent.
+
+Class sky130_fd_sc_hd__and4b_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and4b_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and4b_2        |Circuit 2: sky130_fd_sc_hd__and4b_2        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (7->6)         |sky130_fd_pr__pfet_01v8_hvt (7->6)         
+sky130_fd_pr__nfet_01v8 (7->6)             |sky130_fd_pr__nfet_01v8 (7->6)             
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 14                         |Number of nets: 14                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and4b_2        |Circuit 2: sky130_fd_sc_hd__and4b_2        
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+X                                          |X                                          
+D                                          |D                                          
+A_N                                        |A_N                                        
+C                                          |C                                          
+B                                          |B                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and4b_2 and sky130_fd_sc_hd__and4b_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21a_1         |Circuit 2: sky130_fd_sc_hd__o21a_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4)            |sky130_fd_pr__pfet_01v8_hvt (4)            
+sky130_fd_pr__nfet_01v8 (4)                |sky130_fd_pr__nfet_01v8 (4)                
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21a_1         |Circuit 2: sky130_fd_sc_hd__o21a_1         
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+A1                                         |A1                                         
+B1                                         |B1                                         
+X                                          |X                                          
+A2                                         |A2                                         
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21a_1 and sky130_fd_sc_hd__o21a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o2111a_1       |Circuit 2: sky130_fd_sc_hd__o2111a_1       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6)            |sky130_fd_pr__pfet_01v8_hvt (6)            
+sky130_fd_pr__nfet_01v8 (6)                |sky130_fd_pr__nfet_01v8 (6)                
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 15                         |Number of nets: 15                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o2111a_1       |Circuit 2: sky130_fd_sc_hd__o2111a_1       
+-------------------------------------------|-------------------------------------------
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+D1                                         |D1                                         
+C1                                         |C1                                         
+A1                                         |A1                                         
+A2                                         |A2                                         
+B1                                         |B1                                         
+X                                          |X                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o2111a_1 and sky130_fd_sc_hd__o2111a_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3b_1        |Circuit 2: sky130_fd_sc_hd__and3b_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5)                |sky130_fd_pr__nfet_01v8 (5)                
+sky130_fd_pr__pfet_01v8_hvt (5)            |sky130_fd_pr__pfet_01v8_hvt (5)            
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 12                         |Number of nets: 12                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3b_1        |Circuit 2: sky130_fd_sc_hd__and3b_1        
+-------------------------------------------|-------------------------------------------
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+X                                          |X                                          
+A_N                                        |A_N                                        
+C                                          |C                                          
+B                                          |B                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3b_1 and sky130_fd_sc_hd__and3b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o211a_1        |Circuit 2: sky130_fd_sc_hd__o211a_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (5)                |sky130_fd_pr__nfet_01v8 (5)                
+sky130_fd_pr__pfet_01v8_hvt (5)            |sky130_fd_pr__pfet_01v8_hvt (5)            
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 13                         |Number of nets: 13                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o211a_1        |Circuit 2: sky130_fd_sc_hd__o211a_1        
+-------------------------------------------|-------------------------------------------
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+C1                                         |C1                                         
+A1                                         |A1                                         
+B1                                         |B1                                         
+A2                                         |A2                                         
+X                                          |X                                          
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o211a_1 and sky130_fd_sc_hd__o211a_1 are equivalent.
+
+Class sky130_fd_sc_hd__and3_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__and3_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and3_2         |Circuit 2: sky130_fd_sc_hd__and3_2         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4)         |sky130_fd_pr__pfet_01v8_hvt (5->4)         
+sky130_fd_pr__nfet_01v8 (5->4)             |sky130_fd_pr__nfet_01v8 (5->4)             
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and3_2         |Circuit 2: sky130_fd_sc_hd__and3_2         
+-------------------------------------------|-------------------------------------------
+X                                          |X                                          
+VGND                                       |VGND                                       
+A                                          |A                                          
+C                                          |C                                          
+B                                          |B                                          
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and3_2 and sky130_fd_sc_hd__and3_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand3_1        |Circuit 2: sky130_fd_sc_hd__nand3_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3)            |sky130_fd_pr__pfet_01v8_hvt (3)            
+sky130_fd_pr__nfet_01v8 (3)                |sky130_fd_pr__nfet_01v8 (3)                
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 10                         |Number of nets: 10                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand3_1        |Circuit 2: sky130_fd_sc_hd__nand3_1        
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+Y                                          |Y                                          
+A                                          |A                                          
+B                                          |B                                          
+C                                          |C                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand3_1 and sky130_fd_sc_hd__nand3_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__xor2_1         |Circuit 2: sky130_fd_sc_hd__xor2_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5)            |sky130_fd_pr__pfet_01v8_hvt (5)            
+sky130_fd_pr__nfet_01v8 (5)                |sky130_fd_pr__nfet_01v8 (5)                
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__xor2_1         |Circuit 2: sky130_fd_sc_hd__xor2_1         
+-------------------------------------------|-------------------------------------------
+A                                          |A                                          
+VGND                                       |VGND                                       
+B                                          |B                                          
+VNB                                        |VNB                                        
+VPB                                        |VPB                                        
+X                                          |X                                          
+VPWR                                       |VPWR                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__xor2_1 and sky130_fd_sc_hd__xor2_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21o_1         |Circuit 2: sky130_fd_sc_hd__a21o_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (4)                |sky130_fd_pr__nfet_01v8 (4)                
+sky130_fd_pr__pfet_01v8_hvt (4)            |sky130_fd_pr__pfet_01v8_hvt (4)            
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21o_1         |Circuit 2: sky130_fd_sc_hd__a21o_1         
+-------------------------------------------|-------------------------------------------
+VNB                                        |VNB                                        
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+A2                                         |A2                                         
+X                                          |X                                          
+B1                                         |B1                                         
+A1                                         |A1                                         
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21o_1 and sky130_fd_sc_hd__a21o_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a22o_1         |Circuit 2: sky130_fd_sc_hd__a22o_1         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5)            |sky130_fd_pr__pfet_01v8_hvt (5)            
+sky130_fd_pr__nfet_01v8 (5)                |sky130_fd_pr__nfet_01v8 (5)                
+Number of devices: 10                      |Number of devices: 10                      
+Number of nets: 13                         |Number of nets: 13                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a22o_1         |Circuit 2: sky130_fd_sc_hd__a22o_1         
+-------------------------------------------|-------------------------------------------
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+A2                                         |A2                                         
+A1                                         |A1                                         
+B1                                         |B1                                         
+X                                          |X                                          
+B2                                         |B2                                         
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a22o_1 and sky130_fd_sc_hd__a22o_1 are equivalent.
+
+Class sky130_fd_sc_hd__a21o_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__a21o_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a21o_2         |Circuit 2: sky130_fd_sc_hd__a21o_2         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->4)         |sky130_fd_pr__pfet_01v8_hvt (5->4)         
+sky130_fd_pr__nfet_01v8 (5->4)             |sky130_fd_pr__nfet_01v8 (5->4)             
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a21o_2         |Circuit 2: sky130_fd_sc_hd__a21o_2         
+-------------------------------------------|-------------------------------------------
+VNB                                        |VNB                                        
+VPB                                        |VPB                                        
+A1                                         |A1                                         
+X                                          |X                                          
+B1                                         |B1                                         
+A2                                         |A2                                         
+VPWR                                       |VPWR                                       
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a21o_2 and sky130_fd_sc_hd__a21o_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2_1        |Circuit 2: sky130_fd_sc_hd__nand2_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (2)            |sky130_fd_pr__pfet_01v8_hvt (2)            
+sky130_fd_pr__nfet_01v8 (2)                |sky130_fd_pr__nfet_01v8 (2)                
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 8                          |Number of nets: 8                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_1        |Circuit 2: sky130_fd_sc_hd__nand2_1        
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+Y                                          |Y                                          
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+B                                          |B                                          
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_1 and sky130_fd_sc_hd__nand2_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_1       |Circuit 2: sky130_fd_sc_hd__a2bb2o_1       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6)            |sky130_fd_pr__pfet_01v8_hvt (6)            
+sky130_fd_pr__nfet_01v8 (6)                |sky130_fd_pr__nfet_01v8 (6)                
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 14                         |Number of nets: 14                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a2bb2o_1       |Circuit 2: sky130_fd_sc_hd__a2bb2o_1       
+-------------------------------------------|-------------------------------------------
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+A1_N                                       |A1_N                                       
+A2_N                                       |A2_N                                       
+X                                          |X                                          
+B2                                         |B2                                         
+B1                                         |B1                                         
+VGND                                       |VGND                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a2bb2o_1 and sky130_fd_sc_hd__a2bb2o_1 are equivalent.
+
+Class sky130_fd_sc_hd__buf_8 (0):  Merged 18 parallel devices.
+Class sky130_fd_sc_hd__buf_8 (1):  Merged 18 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_8          |Circuit 2: sky130_fd_sc_hd__buf_8          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (11->2)            |sky130_fd_pr__nfet_01v8 (11->2)            
+sky130_fd_pr__pfet_01v8_hvt (11->2)        |sky130_fd_pr__pfet_01v8_hvt (11->2)        
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_8          |Circuit 2: sky130_fd_sc_hd__buf_8          
+-------------------------------------------|-------------------------------------------
+X                                          |X                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+A                                          |A                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1 
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (6)            |sky130_fd_pr__pfet_01v8_hvt (6)            
+sky130_fd_pr__nfet_01v8 (6)                |sky130_fd_pr__nfet_01v8 (6)                
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 11                         |Number of nets: 11                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1 
+-------------------------------------------|-------------------------------------------
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+X                                          |X                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__dlymetal6s2s_1 and sky130_fd_sc_hd__dlymetal6s2s_1 are equivalent.
+
+Class sky130_fd_sc_hd__buf_6 (0):  Merged 12 parallel devices.
+Class sky130_fd_sc_hd__buf_6 (1):  Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_6          |Circuit 2: sky130_fd_sc_hd__buf_6          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->2)         |sky130_fd_pr__pfet_01v8_hvt (8->2)         
+sky130_fd_pr__nfet_01v8 (8->2)             |sky130_fd_pr__nfet_01v8 (8->2)             
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_6          |Circuit 2: sky130_fd_sc_hd__buf_6          
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+X                                          |X                                          
+VNB                                        |VNB                                        
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_6 and sky130_fd_sc_hd__buf_6 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_2 (0):  Merged 2 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_2 (1):  Merged 2 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2       |Circuit 2: sky130_fd_sc_hd__clkbuf_2       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (3->2)         |sky130_fd_pr__pfet_01v8_hvt (3->2)         
+sky130_fd_pr__nfet_01v8 (3->2)             |sky130_fd_pr__nfet_01v8 (3->2)             
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_2       |Circuit 2: sky130_fd_sc_hd__clkbuf_2       
+-------------------------------------------|-------------------------------------------
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+X                                          |X                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
+
+Class sky130_fd_sc_hd__clkbuf_4 (0):  Merged 6 parallel devices.
+Class sky130_fd_sc_hd__clkbuf_4 (1):  Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4       |Circuit 2: sky130_fd_sc_hd__clkbuf_4       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2)         |sky130_fd_pr__pfet_01v8_hvt (5->2)         
+sky130_fd_pr__nfet_01v8 (5->2)             |sky130_fd_pr__nfet_01v8 (5->2)             
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__clkbuf_4       |Circuit 2: sky130_fd_sc_hd__clkbuf_4       
+-------------------------------------------|-------------------------------------------
+VPWR                                       |VPWR                                       
+X                                          |X                                          
+VPB                                        |VPB                                        
+A                                          |A                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
+
+Class sky130_fd_sc_hd__buf_4 (0):  Merged 6 parallel devices.
+Class sky130_fd_sc_hd__buf_4 (1):  Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__buf_4          |Circuit 2: sky130_fd_sc_hd__buf_4          
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (5->2)         |sky130_fd_pr__pfet_01v8_hvt (5->2)         
+sky130_fd_pr__nfet_01v8 (5->2)             |sky130_fd_pr__nfet_01v8 (5->2)             
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 7                          |Number of nets: 7                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__buf_4          |Circuit 2: sky130_fd_sc_hd__buf_4          
+-------------------------------------------|-------------------------------------------
+X                                          |X                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+A                                          |A                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
+
+Class sky130_fd_sc_hd__nand2_8 (0):  Merged 28 parallel devices.
+Class sky130_fd_sc_hd__nand2_8 (1):  Merged 28 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2_8        |Circuit 2: sky130_fd_sc_hd__nand2_8        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (16->2)            |sky130_fd_pr__nfet_01v8 (16->2)            
+sky130_fd_pr__pfet_01v8_hvt (16->2)        |sky130_fd_pr__pfet_01v8_hvt (16->2)        
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 8                          |Number of nets: 8                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2_8        |Circuit 2: sky130_fd_sc_hd__nand2_8        
+-------------------------------------------|-------------------------------------------
+Y                                          |Y                                          
+VGND                                       |VGND                                       
+A                                          |A                                          
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+B                                          |B                                          
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2_8 and sky130_fd_sc_hd__nand2_8 are equivalent.
+
+Class sky130_fd_sc_hd__nor2_4 (0):  Merged 12 parallel devices.
+Class sky130_fd_sc_hd__nor2_4 (1):  Merged 12 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nor2_4         |Circuit 2: sky130_fd_sc_hd__nor2_4         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (8->2)         |sky130_fd_pr__pfet_01v8_hvt (8->2)         
+sky130_fd_pr__nfet_01v8 (8->2)             |sky130_fd_pr__nfet_01v8 (8->2)             
+Number of devices: 4                       |Number of devices: 4                       
+Number of nets: 8                          |Number of nets: 8                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nor2_4         |Circuit 2: sky130_fd_sc_hd__nor2_4         
+-------------------------------------------|-------------------------------------------
+Y                                          |Y                                          
+B                                          |B                                          
+VPB                                        |VPB                                        
+A                                          |A                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nor2_4 and sky130_fd_sc_hd__nor2_4 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__and2b_1        |Circuit 2: sky130_fd_sc_hd__and2b_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (4)            |sky130_fd_pr__pfet_01v8_hvt (4)            
+sky130_fd_pr__nfet_01v8 (4)                |sky130_fd_pr__nfet_01v8 (4)                
+Number of devices: 8                       |Number of devices: 8                       
+Number of nets: 10                         |Number of nets: 10                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__and2b_1        |Circuit 2: sky130_fd_sc_hd__and2b_1        
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+B                                          |B                                          
+X                                          |X                                          
+A_N                                        |A_N                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__and2b_1 and sky130_fd_sc_hd__and2b_1 are equivalent.
+
+Class sky130_fd_sc_hd__inv_12 (0):  Merged 22 parallel devices.
+Class sky130_fd_sc_hd__inv_12 (1):  Merged 22 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__inv_12         |Circuit 2: sky130_fd_sc_hd__inv_12         
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8_hvt (12->1)        |sky130_fd_pr__pfet_01v8_hvt (12->1)        
+sky130_fd_pr__nfet_01v8 (12->1)            |sky130_fd_pr__nfet_01v8 (12->1)            
+Number of devices: 2                       |Number of devices: 2                       
+Number of nets: 6                          |Number of nets: 6                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__inv_12         |Circuit 2: sky130_fd_sc_hd__inv_12         
+-------------------------------------------|-------------------------------------------
+Y                                          |Y                                          
+A                                          |A                                          
+VGND                                       |VGND                                       
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__inv_12 and sky130_fd_sc_hd__inv_12 are equivalent.
+
+Class sky130_fd_sc_hd__o21ai_2 (0):  Merged 6 parallel devices.
+Class sky130_fd_sc_hd__o21ai_2 (1):  Merged 6 parallel devices.
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__o21ai_2        |Circuit 2: sky130_fd_sc_hd__o21ai_2        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6->3)             |sky130_fd_pr__nfet_01v8 (6->3)             
+sky130_fd_pr__pfet_01v8_hvt (6->3)         |sky130_fd_pr__pfet_01v8_hvt (6->3)         
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 10                         |Number of nets: 10                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__o21ai_2        |Circuit 2: sky130_fd_sc_hd__o21ai_2        
+-------------------------------------------|-------------------------------------------
+Y                                          |Y                                          
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+A2                                         |A2                                         
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+B1                                         |B1                                         
+A1                                         |A1                                         
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__o21ai_2 and sky130_fd_sc_hd__o21ai_2 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__nand2b_1       |Circuit 2: sky130_fd_sc_hd__nand2b_1       
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (3)                |sky130_fd_pr__nfet_01v8 (3)                
+sky130_fd_pr__pfet_01v8_hvt (3)            |sky130_fd_pr__pfet_01v8_hvt (3)            
+Number of devices: 6                       |Number of devices: 6                       
+Number of nets: 9                          |Number of nets: 9                          
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__nand2b_1       |Circuit 2: sky130_fd_sc_hd__nand2b_1       
+-------------------------------------------|-------------------------------------------
+Y                                          |Y                                          
+VNB                                        |VNB                                        
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+A_N                                        |A_N                                        
+VGND                                       |VGND                                       
+B                                          |B                                          
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__nand2b_1 and sky130_fd_sc_hd__nand2b_1 are equivalent.
+
+Subcircuit summary:
+Circuit 1: sky130_fd_sc_hd__a221o_1        |Circuit 2: sky130_fd_sc_hd__a221o_1        
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__nfet_01v8 (6)                |sky130_fd_pr__nfet_01v8 (6)                
+sky130_fd_pr__pfet_01v8_hvt (6)            |sky130_fd_pr__pfet_01v8_hvt (6)            
+Number of devices: 12                      |Number of devices: 12                      
+Number of nets: 15                         |Number of nets: 15                         
+---------------------------------------------------------------------------------------
+Netlists match uniquely.
+
+Subcircuit pins:
+Circuit 1: sky130_fd_sc_hd__a221o_1        |Circuit 2: sky130_fd_sc_hd__a221o_1        
+-------------------------------------------|-------------------------------------------
+VGND                                       |VGND                                       
+VPWR                                       |VPWR                                       
+VPB                                        |VPB                                        
+VNB                                        |VNB                                        
+X                                          |X                                          
+B1                                         |B1                                         
+A1                                         |A1                                         
+C1                                         |C1                                         
+A2                                         |A2                                         
+B2                                         |B2                                         
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes sky130_fd_sc_hd__a221o_1 and sky130_fd_sc_hd__a221o_1 are equivalent.
+Flattening unmatched subcell sky130_fd_sc_hd__tapvpwrvgnd_1 in circuit user_proj_example (1)(69228 instances)
+Flattening unmatched subcell sky130_fd_sc_hd__fill_1 in circuit user_proj_example (1)(68948 instances)
+Flattening unmatched subcell sky130_fd_sc_hd__fill_2 in circuit user_proj_example (1)(1654 instances)
+
+Cell user_proj_example (0) disconnected node: io_in[0]
+Cell user_proj_example (0) disconnected node: io_in[10]
+Cell user_proj_example (0) disconnected node: io_in[11]
+Cell user_proj_example (0) disconnected node: io_in[12]
+Cell user_proj_example (0) disconnected node: io_in[13]
+Cell user_proj_example (0) disconnected node: io_in[14]
+Cell user_proj_example (0) disconnected node: io_in[15]
+Cell user_proj_example (0) disconnected node: io_in[1]
+Cell user_proj_example (0) disconnected node: io_in[2]
+Cell user_proj_example (0) disconnected node: io_in[3]
+Cell user_proj_example (0) disconnected node: io_in[4]
+Cell user_proj_example (0) disconnected node: io_in[5]
+Cell user_proj_example (0) disconnected node: io_in[6]
+Cell user_proj_example (0) disconnected node: io_in[7]
+Cell user_proj_example (0) disconnected node: io_in[8]
+Cell user_proj_example (0) disconnected node: io_in[9]
+Cell user_proj_example (0) disconnected node: la_data_in[0]
+Cell user_proj_example (0) disconnected node: la_data_in[100]
+Cell user_proj_example (0) disconnected node: la_data_in[101]
+Cell user_proj_example (0) disconnected node: la_data_in[102]
+Cell user_proj_example (0) disconnected node: la_data_in[103]
+Cell user_proj_example (0) disconnected node: la_data_in[104]
+Cell user_proj_example (0) disconnected node: la_data_in[105]
+Cell user_proj_example (0) disconnected node: la_data_in[106]
+Cell user_proj_example (0) disconnected node: la_data_in[107]
+Cell user_proj_example (0) disconnected node: la_data_in[108]
+Cell user_proj_example (0) disconnected node: la_data_in[109]
+Cell user_proj_example (0) disconnected node: la_data_in[10]
+Cell user_proj_example (0) disconnected node: la_data_in[110]
+Cell user_proj_example (0) disconnected node: la_data_in[111]
+Cell user_proj_example (0) disconnected node: la_data_in[112]
+Cell user_proj_example (0) disconnected node: la_data_in[113]
+Cell user_proj_example (0) disconnected node: la_data_in[114]
+Cell user_proj_example (0) disconnected node: la_data_in[115]
+Cell user_proj_example (0) disconnected node: la_data_in[116]
+Cell user_proj_example (0) disconnected node: la_data_in[117]
+Cell user_proj_example (0) disconnected node: la_data_in[118]
+Cell user_proj_example (0) disconnected node: la_data_in[119]
+Cell user_proj_example (0) disconnected node: la_data_in[11]
+Cell user_proj_example (0) disconnected node: la_data_in[120]
+Cell user_proj_example (0) disconnected node: la_data_in[121]
+Cell user_proj_example (0) disconnected node: la_data_in[122]
+Cell user_proj_example (0) disconnected node: la_data_in[123]
+Cell user_proj_example (0) disconnected node: la_data_in[124]
+Cell user_proj_example (0) disconnected node: la_data_in[125]
+Cell user_proj_example (0) disconnected node: la_data_in[126]
+Cell user_proj_example (0) disconnected node: la_data_in[127]
+Cell user_proj_example (0) disconnected node: la_data_in[12]
+Cell user_proj_example (0) disconnected node: la_data_in[13]
+Cell user_proj_example (0) disconnected node: la_data_in[14]
+Cell user_proj_example (0) disconnected node: la_data_in[15]
+Cell user_proj_example (0) disconnected node: la_data_in[16]
+Cell user_proj_example (0) disconnected node: la_data_in[17]
+Cell user_proj_example (0) disconnected node: la_data_in[18]
+Cell user_proj_example (0) disconnected node: la_data_in[19]
+Cell user_proj_example (0) disconnected node: la_data_in[1]
+Cell user_proj_example (0) disconnected node: la_data_in[20]
+Cell user_proj_example (0) disconnected node: la_data_in[21]
+Cell user_proj_example (0) disconnected node: la_data_in[22]
+Cell user_proj_example (0) disconnected node: la_data_in[23]
+Cell user_proj_example (0) disconnected node: la_data_in[24]
+Cell user_proj_example (0) disconnected node: la_data_in[25]
+Cell user_proj_example (0) disconnected node: la_data_in[26]
+Cell user_proj_example (0) disconnected node: la_data_in[27]
+Cell user_proj_example (0) disconnected node: la_data_in[28]
+Cell user_proj_example (0) disconnected node: la_data_in[29]
+Cell user_proj_example (0) disconnected node: la_data_in[2]
+Cell user_proj_example (0) disconnected node: la_data_in[30]
+Cell user_proj_example (0) disconnected node: la_data_in[31]
+Cell user_proj_example (0) disconnected node: la_data_in[32]
+Cell user_proj_example (0) disconnected node: la_data_in[33]
+Cell user_proj_example (0) disconnected node: la_data_in[34]
+Cell user_proj_example (0) disconnected node: la_data_in[35]
+Cell user_proj_example (0) disconnected node: la_data_in[36]
+Cell user_proj_example (0) disconnected node: la_data_in[37]
+Cell user_proj_example (0) disconnected node: la_data_in[38]
+Cell user_proj_example (0) disconnected node: la_data_in[39]
+Cell user_proj_example (0) disconnected node: la_data_in[3]
+Cell user_proj_example (0) disconnected node: la_data_in[40]
+Cell user_proj_example (0) disconnected node: la_data_in[41]
+Cell user_proj_example (0) disconnected node: la_data_in[42]
+Cell user_proj_example (0) disconnected node: la_data_in[43]
+Cell user_proj_example (0) disconnected node: la_data_in[44]
+Cell user_proj_example (0) disconnected node: la_data_in[45]
+Cell user_proj_example (0) disconnected node: la_data_in[46]
+Cell user_proj_example (0) disconnected node: la_data_in[47]
+Cell user_proj_example (0) disconnected node: la_data_in[4]
+Cell user_proj_example (0) disconnected node: la_data_in[5]
+Cell user_proj_example (0) disconnected node: la_data_in[66]
+Cell user_proj_example (0) disconnected node: la_data_in[67]
+Cell user_proj_example (0) disconnected node: la_data_in[68]
+Cell user_proj_example (0) disconnected node: la_data_in[69]
+Cell user_proj_example (0) disconnected node: la_data_in[6]
+Cell user_proj_example (0) disconnected node: la_data_in[70]
+Cell user_proj_example (0) disconnected node: la_data_in[71]
+Cell user_proj_example (0) disconnected node: la_data_in[72]
+Cell user_proj_example (0) disconnected node: la_data_in[73]
+Cell user_proj_example (0) disconnected node: la_data_in[74]
+Cell user_proj_example (0) disconnected node: la_data_in[75]
+Cell user_proj_example (0) disconnected node: la_data_in[76]
+Cell user_proj_example (0) disconnected node: la_data_in[77]
+Cell user_proj_example (0) disconnected node: la_data_in[78]
+Cell user_proj_example (0) disconnected node: la_data_in[79]
+Cell user_proj_example (0) disconnected node: la_data_in[7]
+Cell user_proj_example (0) disconnected node: la_data_in[80]
+Cell user_proj_example (0) disconnected node: la_data_in[81]
+Cell user_proj_example (0) disconnected node: la_data_in[82]
+Cell user_proj_example (0) disconnected node: la_data_in[83]
+Cell user_proj_example (0) disconnected node: la_data_in[84]
+Cell user_proj_example (0) disconnected node: la_data_in[85]
+Cell user_proj_example (0) disconnected node: la_data_in[86]
+Cell user_proj_example (0) disconnected node: la_data_in[87]
+Cell user_proj_example (0) disconnected node: la_data_in[88]
+Cell user_proj_example (0) disconnected node: la_data_in[89]
+Cell user_proj_example (0) disconnected node: la_data_in[8]
+Cell user_proj_example (0) disconnected node: la_data_in[90]
+Cell user_proj_example (0) disconnected node: la_data_in[91]
+Cell user_proj_example (0) disconnected node: la_data_in[92]
+Cell user_proj_example (0) disconnected node: la_data_in[93]
+Cell user_proj_example (0) disconnected node: la_data_in[94]
+Cell user_proj_example (0) disconnected node: la_data_in[95]
+Cell user_proj_example (0) disconnected node: la_data_in[96]
+Cell user_proj_example (0) disconnected node: la_data_in[97]
+Cell user_proj_example (0) disconnected node: la_data_in[98]
+Cell user_proj_example (0) disconnected node: la_data_in[99]
+Cell user_proj_example (0) disconnected node: la_data_in[9]
+Cell user_proj_example (0) disconnected node: la_oenb[0]
+Cell user_proj_example (0) disconnected node: la_oenb[100]
+Cell user_proj_example (0) disconnected node: la_oenb[101]
+Cell user_proj_example (0) disconnected node: la_oenb[102]
+Cell user_proj_example (0) disconnected node: la_oenb[103]
+Cell user_proj_example (0) disconnected node: la_oenb[104]
+Cell user_proj_example (0) disconnected node: la_oenb[105]
+Cell user_proj_example (0) disconnected node: la_oenb[106]
+Cell user_proj_example (0) disconnected node: la_oenb[107]
+Cell user_proj_example (0) disconnected node: la_oenb[108]
+Cell user_proj_example (0) disconnected node: la_oenb[109]
+Cell user_proj_example (0) disconnected node: la_oenb[10]
+Cell user_proj_example (0) disconnected node: la_oenb[110]
+Cell user_proj_example (0) disconnected node: la_oenb[111]
+Cell user_proj_example (0) disconnected node: la_oenb[112]
+Cell user_proj_example (0) disconnected node: la_oenb[113]
+Cell user_proj_example (0) disconnected node: la_oenb[114]
+Cell user_proj_example (0) disconnected node: la_oenb[115]
+Cell user_proj_example (0) disconnected node: la_oenb[116]
+Cell user_proj_example (0) disconnected node: la_oenb[117]
+Cell user_proj_example (0) disconnected node: la_oenb[118]
+Cell user_proj_example (0) disconnected node: la_oenb[119]
+Cell user_proj_example (0) disconnected node: la_oenb[11]
+Cell user_proj_example (0) disconnected node: la_oenb[120]
+Cell user_proj_example (0) disconnected node: la_oenb[121]
+Cell user_proj_example (0) disconnected node: la_oenb[122]
+Cell user_proj_example (0) disconnected node: la_oenb[123]
+Cell user_proj_example (0) disconnected node: la_oenb[124]
+Cell user_proj_example (0) disconnected node: la_oenb[125]
+Cell user_proj_example (0) disconnected node: la_oenb[126]
+Cell user_proj_example (0) disconnected node: la_oenb[127]
+Cell user_proj_example (0) disconnected node: la_oenb[12]
+Cell user_proj_example (0) disconnected node: la_oenb[13]
+Cell user_proj_example (0) disconnected node: la_oenb[14]
+Cell user_proj_example (0) disconnected node: la_oenb[15]
+Cell user_proj_example (0) disconnected node: la_oenb[16]
+Cell user_proj_example (0) disconnected node: la_oenb[17]
+Cell user_proj_example (0) disconnected node: la_oenb[18]
+Cell user_proj_example (0) disconnected node: la_oenb[19]
+Cell user_proj_example (0) disconnected node: la_oenb[1]
+Cell user_proj_example (0) disconnected node: la_oenb[20]
+Cell user_proj_example (0) disconnected node: la_oenb[21]
+Cell user_proj_example (0) disconnected node: la_oenb[22]
+Cell user_proj_example (0) disconnected node: la_oenb[23]
+Cell user_proj_example (0) disconnected node: la_oenb[24]
+Cell user_proj_example (0) disconnected node: la_oenb[25]
+Cell user_proj_example (0) disconnected node: la_oenb[26]
+Cell user_proj_example (0) disconnected node: la_oenb[27]
+Cell user_proj_example (0) disconnected node: la_oenb[28]
+Cell user_proj_example (0) disconnected node: la_oenb[29]
+Cell user_proj_example (0) disconnected node: la_oenb[2]
+Cell user_proj_example (0) disconnected node: la_oenb[30]
+Cell user_proj_example (0) disconnected node: la_oenb[31]
+Cell user_proj_example (0) disconnected node: la_oenb[32]
+Cell user_proj_example (0) disconnected node: la_oenb[33]
+Cell user_proj_example (0) disconnected node: la_oenb[34]
+Cell user_proj_example (0) disconnected node: la_oenb[35]
+Cell user_proj_example (0) disconnected node: la_oenb[36]
+Cell user_proj_example (0) disconnected node: la_oenb[37]
+Cell user_proj_example (0) disconnected node: la_oenb[38]
+Cell user_proj_example (0) disconnected node: la_oenb[39]
+Cell user_proj_example (0) disconnected node: la_oenb[3]
+Cell user_proj_example (0) disconnected node: la_oenb[40]
+Cell user_proj_example (0) disconnected node: la_oenb[41]
+Cell user_proj_example (0) disconnected node: la_oenb[42]
+Cell user_proj_example (0) disconnected node: la_oenb[43]
+Cell user_proj_example (0) disconnected node: la_oenb[44]
+Cell user_proj_example (0) disconnected node: la_oenb[45]
+Cell user_proj_example (0) disconnected node: la_oenb[46]
+Cell user_proj_example (0) disconnected node: la_oenb[47]
+Cell user_proj_example (0) disconnected node: la_oenb[4]
+Cell user_proj_example (0) disconnected node: la_oenb[5]
+Cell user_proj_example (0) disconnected node: la_oenb[66]
+Cell user_proj_example (0) disconnected node: la_oenb[67]
+Cell user_proj_example (0) disconnected node: la_oenb[68]
+Cell user_proj_example (0) disconnected node: la_oenb[69]
+Cell user_proj_example (0) disconnected node: la_oenb[6]
+Cell user_proj_example (0) disconnected node: la_oenb[70]
+Cell user_proj_example (0) disconnected node: la_oenb[71]
+Cell user_proj_example (0) disconnected node: la_oenb[72]
+Cell user_proj_example (0) disconnected node: la_oenb[73]
+Cell user_proj_example (0) disconnected node: la_oenb[74]
+Cell user_proj_example (0) disconnected node: la_oenb[75]
+Cell user_proj_example (0) disconnected node: la_oenb[76]
+Cell user_proj_example (0) disconnected node: la_oenb[77]
+Cell user_proj_example (0) disconnected node: la_oenb[78]
+Cell user_proj_example (0) disconnected node: la_oenb[79]
+Cell user_proj_example (0) disconnected node: la_oenb[7]
+Cell user_proj_example (0) disconnected node: la_oenb[80]
+Cell user_proj_example (0) disconnected node: la_oenb[81]
+Cell user_proj_example (0) disconnected node: la_oenb[82]
+Cell user_proj_example (0) disconnected node: la_oenb[83]
+Cell user_proj_example (0) disconnected node: la_oenb[84]
+Cell user_proj_example (0) disconnected node: la_oenb[85]
+Cell user_proj_example (0) disconnected node: la_oenb[86]
+Cell user_proj_example (0) disconnected node: la_oenb[87]
+Cell user_proj_example (0) disconnected node: la_oenb[88]
+Cell user_proj_example (0) disconnected node: la_oenb[89]
+Cell user_proj_example (0) disconnected node: la_oenb[8]
+Cell user_proj_example (0) disconnected node: la_oenb[90]
+Cell user_proj_example (0) disconnected node: la_oenb[91]
+Cell user_proj_example (0) disconnected node: la_oenb[92]
+Cell user_proj_example (0) disconnected node: la_oenb[93]
+Cell user_proj_example (0) disconnected node: la_oenb[94]
+Cell user_proj_example (0) disconnected node: la_oenb[95]
+Cell user_proj_example (0) disconnected node: la_oenb[96]
+Cell user_proj_example (0) disconnected node: la_oenb[97]
+Cell user_proj_example (0) disconnected node: la_oenb[98]
+Cell user_proj_example (0) disconnected node: la_oenb[99]
+Cell user_proj_example (0) disconnected node: la_oenb[9]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[0]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[10]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[11]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[12]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[13]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[14]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[15]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[16]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[17]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[18]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[19]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[1]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[20]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[21]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[22]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[23]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[24]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[25]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[26]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[27]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[28]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[29]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[2]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[30]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[31]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[3]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[4]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[5]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[6]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[7]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[8]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[9]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[16]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[17]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[18]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[19]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[20]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[21]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[22]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[23]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[24]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[25]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[26]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[27]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[28]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[29]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[30]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[31]
+Cell user_proj_example (0) disconnected node: wbs_sel_i[2]
+Cell user_proj_example (0) disconnected node: wbs_sel_i[3]
+Cell user_proj_example (1) disconnected node: io_in[15]
+Cell user_proj_example (1) disconnected node: io_in[14]
+Cell user_proj_example (1) disconnected node: io_in[13]
+Cell user_proj_example (1) disconnected node: io_in[12]
+Cell user_proj_example (1) disconnected node: io_in[11]
+Cell user_proj_example (1) disconnected node: io_in[10]
+Cell user_proj_example (1) disconnected node: io_in[9]
+Cell user_proj_example (1) disconnected node: io_in[8]
+Cell user_proj_example (1) disconnected node: io_in[7]
+Cell user_proj_example (1) disconnected node: io_in[6]
+Cell user_proj_example (1) disconnected node: io_in[5]
+Cell user_proj_example (1) disconnected node: io_in[4]
+Cell user_proj_example (1) disconnected node: io_in[3]
+Cell user_proj_example (1) disconnected node: io_in[2]
+Cell user_proj_example (1) disconnected node: io_in[1]
+Cell user_proj_example (1) disconnected node: io_in[0]
+Cell user_proj_example (1) disconnected node: la_data_in[127]
+Cell user_proj_example (1) disconnected node: la_data_in[126]
+Cell user_proj_example (1) disconnected node: la_data_in[125]
+Cell user_proj_example (1) disconnected node: la_data_in[124]
+Cell user_proj_example (1) disconnected node: la_data_in[123]
+Cell user_proj_example (1) disconnected node: la_data_in[122]
+Cell user_proj_example (1) disconnected node: la_data_in[121]
+Cell user_proj_example (1) disconnected node: la_data_in[120]
+Cell user_proj_example (1) disconnected node: la_data_in[119]
+Cell user_proj_example (1) disconnected node: la_data_in[118]
+Cell user_proj_example (1) disconnected node: la_data_in[117]
+Cell user_proj_example (1) disconnected node: la_data_in[116]
+Cell user_proj_example (1) disconnected node: la_data_in[115]
+Cell user_proj_example (1) disconnected node: la_data_in[114]
+Cell user_proj_example (1) disconnected node: la_data_in[113]
+Cell user_proj_example (1) disconnected node: la_data_in[112]
+Cell user_proj_example (1) disconnected node: la_data_in[111]
+Cell user_proj_example (1) disconnected node: la_data_in[110]
+Cell user_proj_example (1) disconnected node: la_data_in[109]
+Cell user_proj_example (1) disconnected node: la_data_in[108]
+Cell user_proj_example (1) disconnected node: la_data_in[107]
+Cell user_proj_example (1) disconnected node: la_data_in[106]
+Cell user_proj_example (1) disconnected node: la_data_in[105]
+Cell user_proj_example (1) disconnected node: la_data_in[104]
+Cell user_proj_example (1) disconnected node: la_data_in[103]
+Cell user_proj_example (1) disconnected node: la_data_in[102]
+Cell user_proj_example (1) disconnected node: la_data_in[101]
+Cell user_proj_example (1) disconnected node: la_data_in[100]
+Cell user_proj_example (1) disconnected node: la_data_in[99]
+Cell user_proj_example (1) disconnected node: la_data_in[98]
+Cell user_proj_example (1) disconnected node: la_data_in[97]
+Cell user_proj_example (1) disconnected node: la_data_in[96]
+Cell user_proj_example (1) disconnected node: la_data_in[95]
+Cell user_proj_example (1) disconnected node: la_data_in[94]
+Cell user_proj_example (1) disconnected node: la_data_in[93]
+Cell user_proj_example (1) disconnected node: la_data_in[92]
+Cell user_proj_example (1) disconnected node: la_data_in[91]
+Cell user_proj_example (1) disconnected node: la_data_in[90]
+Cell user_proj_example (1) disconnected node: la_data_in[89]
+Cell user_proj_example (1) disconnected node: la_data_in[88]
+Cell user_proj_example (1) disconnected node: la_data_in[87]
+Cell user_proj_example (1) disconnected node: la_data_in[86]
+Cell user_proj_example (1) disconnected node: la_data_in[85]
+Cell user_proj_example (1) disconnected node: la_data_in[84]
+Cell user_proj_example (1) disconnected node: la_data_in[83]
+Cell user_proj_example (1) disconnected node: la_data_in[82]
+Cell user_proj_example (1) disconnected node: la_data_in[81]
+Cell user_proj_example (1) disconnected node: la_data_in[80]
+Cell user_proj_example (1) disconnected node: la_data_in[79]
+Cell user_proj_example (1) disconnected node: la_data_in[78]
+Cell user_proj_example (1) disconnected node: la_data_in[77]
+Cell user_proj_example (1) disconnected node: la_data_in[76]
+Cell user_proj_example (1) disconnected node: la_data_in[75]
+Cell user_proj_example (1) disconnected node: la_data_in[74]
+Cell user_proj_example (1) disconnected node: la_data_in[73]
+Cell user_proj_example (1) disconnected node: la_data_in[72]
+Cell user_proj_example (1) disconnected node: la_data_in[71]
+Cell user_proj_example (1) disconnected node: la_data_in[70]
+Cell user_proj_example (1) disconnected node: la_data_in[69]
+Cell user_proj_example (1) disconnected node: la_data_in[68]
+Cell user_proj_example (1) disconnected node: la_data_in[67]
+Cell user_proj_example (1) disconnected node: la_data_in[66]
+Cell user_proj_example (1) disconnected node: la_data_in[47]
+Cell user_proj_example (1) disconnected node: la_data_in[46]
+Cell user_proj_example (1) disconnected node: la_data_in[45]
+Cell user_proj_example (1) disconnected node: la_data_in[44]
+Cell user_proj_example (1) disconnected node: la_data_in[43]
+Cell user_proj_example (1) disconnected node: la_data_in[42]
+Cell user_proj_example (1) disconnected node: la_data_in[41]
+Cell user_proj_example (1) disconnected node: la_data_in[40]
+Cell user_proj_example (1) disconnected node: la_data_in[39]
+Cell user_proj_example (1) disconnected node: la_data_in[38]
+Cell user_proj_example (1) disconnected node: la_data_in[37]
+Cell user_proj_example (1) disconnected node: la_data_in[36]
+Cell user_proj_example (1) disconnected node: la_data_in[35]
+Cell user_proj_example (1) disconnected node: la_data_in[34]
+Cell user_proj_example (1) disconnected node: la_data_in[33]
+Cell user_proj_example (1) disconnected node: la_data_in[32]
+Cell user_proj_example (1) disconnected node: la_data_in[31]
+Cell user_proj_example (1) disconnected node: la_data_in[30]
+Cell user_proj_example (1) disconnected node: la_data_in[29]
+Cell user_proj_example (1) disconnected node: la_data_in[28]
+Cell user_proj_example (1) disconnected node: la_data_in[27]
+Cell user_proj_example (1) disconnected node: la_data_in[26]
+Cell user_proj_example (1) disconnected node: la_data_in[25]
+Cell user_proj_example (1) disconnected node: la_data_in[24]
+Cell user_proj_example (1) disconnected node: la_data_in[23]
+Cell user_proj_example (1) disconnected node: la_data_in[22]
+Cell user_proj_example (1) disconnected node: la_data_in[21]
+Cell user_proj_example (1) disconnected node: la_data_in[20]
+Cell user_proj_example (1) disconnected node: la_data_in[19]
+Cell user_proj_example (1) disconnected node: la_data_in[18]
+Cell user_proj_example (1) disconnected node: la_data_in[17]
+Cell user_proj_example (1) disconnected node: la_data_in[16]
+Cell user_proj_example (1) disconnected node: la_data_in[15]
+Cell user_proj_example (1) disconnected node: la_data_in[14]
+Cell user_proj_example (1) disconnected node: la_data_in[13]
+Cell user_proj_example (1) disconnected node: la_data_in[12]
+Cell user_proj_example (1) disconnected node: la_data_in[11]
+Cell user_proj_example (1) disconnected node: la_data_in[10]
+Cell user_proj_example (1) disconnected node: la_data_in[9]
+Cell user_proj_example (1) disconnected node: la_data_in[8]
+Cell user_proj_example (1) disconnected node: la_data_in[7]
+Cell user_proj_example (1) disconnected node: la_data_in[6]
+Cell user_proj_example (1) disconnected node: la_data_in[5]
+Cell user_proj_example (1) disconnected node: la_data_in[4]
+Cell user_proj_example (1) disconnected node: la_data_in[3]
+Cell user_proj_example (1) disconnected node: la_data_in[2]
+Cell user_proj_example (1) disconnected node: la_data_in[1]
+Cell user_proj_example (1) disconnected node: la_data_in[0]
+Cell user_proj_example (1) disconnected node: la_oenb[127]
+Cell user_proj_example (1) disconnected node: la_oenb[126]
+Cell user_proj_example (1) disconnected node: la_oenb[125]
+Cell user_proj_example (1) disconnected node: la_oenb[124]
+Cell user_proj_example (1) disconnected node: la_oenb[123]
+Cell user_proj_example (1) disconnected node: la_oenb[122]
+Cell user_proj_example (1) disconnected node: la_oenb[121]
+Cell user_proj_example (1) disconnected node: la_oenb[120]
+Cell user_proj_example (1) disconnected node: la_oenb[119]
+Cell user_proj_example (1) disconnected node: la_oenb[118]
+Cell user_proj_example (1) disconnected node: la_oenb[117]
+Cell user_proj_example (1) disconnected node: la_oenb[116]
+Cell user_proj_example (1) disconnected node: la_oenb[115]
+Cell user_proj_example (1) disconnected node: la_oenb[114]
+Cell user_proj_example (1) disconnected node: la_oenb[113]
+Cell user_proj_example (1) disconnected node: la_oenb[112]
+Cell user_proj_example (1) disconnected node: la_oenb[111]
+Cell user_proj_example (1) disconnected node: la_oenb[110]
+Cell user_proj_example (1) disconnected node: la_oenb[109]
+Cell user_proj_example (1) disconnected node: la_oenb[108]
+Cell user_proj_example (1) disconnected node: la_oenb[107]
+Cell user_proj_example (1) disconnected node: la_oenb[106]
+Cell user_proj_example (1) disconnected node: la_oenb[105]
+Cell user_proj_example (1) disconnected node: la_oenb[104]
+Cell user_proj_example (1) disconnected node: la_oenb[103]
+Cell user_proj_example (1) disconnected node: la_oenb[102]
+Cell user_proj_example (1) disconnected node: la_oenb[101]
+Cell user_proj_example (1) disconnected node: la_oenb[100]
+Cell user_proj_example (1) disconnected node: la_oenb[99]
+Cell user_proj_example (1) disconnected node: la_oenb[98]
+Cell user_proj_example (1) disconnected node: la_oenb[97]
+Cell user_proj_example (1) disconnected node: la_oenb[96]
+Cell user_proj_example (1) disconnected node: la_oenb[95]
+Cell user_proj_example (1) disconnected node: la_oenb[94]
+Cell user_proj_example (1) disconnected node: la_oenb[93]
+Cell user_proj_example (1) disconnected node: la_oenb[92]
+Cell user_proj_example (1) disconnected node: la_oenb[91]
+Cell user_proj_example (1) disconnected node: la_oenb[90]
+Cell user_proj_example (1) disconnected node: la_oenb[89]
+Cell user_proj_example (1) disconnected node: la_oenb[88]
+Cell user_proj_example (1) disconnected node: la_oenb[87]
+Cell user_proj_example (1) disconnected node: la_oenb[86]
+Cell user_proj_example (1) disconnected node: la_oenb[85]
+Cell user_proj_example (1) disconnected node: la_oenb[84]
+Cell user_proj_example (1) disconnected node: la_oenb[83]
+Cell user_proj_example (1) disconnected node: la_oenb[82]
+Cell user_proj_example (1) disconnected node: la_oenb[81]
+Cell user_proj_example (1) disconnected node: la_oenb[80]
+Cell user_proj_example (1) disconnected node: la_oenb[79]
+Cell user_proj_example (1) disconnected node: la_oenb[78]
+Cell user_proj_example (1) disconnected node: la_oenb[77]
+Cell user_proj_example (1) disconnected node: la_oenb[76]
+Cell user_proj_example (1) disconnected node: la_oenb[75]
+Cell user_proj_example (1) disconnected node: la_oenb[74]
+Cell user_proj_example (1) disconnected node: la_oenb[73]
+Cell user_proj_example (1) disconnected node: la_oenb[72]
+Cell user_proj_example (1) disconnected node: la_oenb[71]
+Cell user_proj_example (1) disconnected node: la_oenb[70]
+Cell user_proj_example (1) disconnected node: la_oenb[69]
+Cell user_proj_example (1) disconnected node: la_oenb[68]
+Cell user_proj_example (1) disconnected node: la_oenb[67]
+Cell user_proj_example (1) disconnected node: la_oenb[66]
+Cell user_proj_example (1) disconnected node: la_oenb[47]
+Cell user_proj_example (1) disconnected node: la_oenb[46]
+Cell user_proj_example (1) disconnected node: la_oenb[45]
+Cell user_proj_example (1) disconnected node: la_oenb[44]
+Cell user_proj_example (1) disconnected node: la_oenb[43]
+Cell user_proj_example (1) disconnected node: la_oenb[42]
+Cell user_proj_example (1) disconnected node: la_oenb[41]
+Cell user_proj_example (1) disconnected node: la_oenb[40]
+Cell user_proj_example (1) disconnected node: la_oenb[39]
+Cell user_proj_example (1) disconnected node: la_oenb[38]
+Cell user_proj_example (1) disconnected node: la_oenb[37]
+Cell user_proj_example (1) disconnected node: la_oenb[36]
+Cell user_proj_example (1) disconnected node: la_oenb[35]
+Cell user_proj_example (1) disconnected node: la_oenb[34]
+Cell user_proj_example (1) disconnected node: la_oenb[33]
+Cell user_proj_example (1) disconnected node: la_oenb[32]
+Cell user_proj_example (1) disconnected node: la_oenb[31]
+Cell user_proj_example (1) disconnected node: la_oenb[30]
+Cell user_proj_example (1) disconnected node: la_oenb[29]
+Cell user_proj_example (1) disconnected node: la_oenb[28]
+Cell user_proj_example (1) disconnected node: la_oenb[27]
+Cell user_proj_example (1) disconnected node: la_oenb[26]
+Cell user_proj_example (1) disconnected node: la_oenb[25]
+Cell user_proj_example (1) disconnected node: la_oenb[24]
+Cell user_proj_example (1) disconnected node: la_oenb[23]
+Cell user_proj_example (1) disconnected node: la_oenb[22]
+Cell user_proj_example (1) disconnected node: la_oenb[21]
+Cell user_proj_example (1) disconnected node: la_oenb[20]
+Cell user_proj_example (1) disconnected node: la_oenb[19]
+Cell user_proj_example (1) disconnected node: la_oenb[18]
+Cell user_proj_example (1) disconnected node: la_oenb[17]
+Cell user_proj_example (1) disconnected node: la_oenb[16]
+Cell user_proj_example (1) disconnected node: la_oenb[15]
+Cell user_proj_example (1) disconnected node: la_oenb[14]
+Cell user_proj_example (1) disconnected node: la_oenb[13]
+Cell user_proj_example (1) disconnected node: la_oenb[12]
+Cell user_proj_example (1) disconnected node: la_oenb[11]
+Cell user_proj_example (1) disconnected node: la_oenb[10]
+Cell user_proj_example (1) disconnected node: la_oenb[9]
+Cell user_proj_example (1) disconnected node: la_oenb[8]
+Cell user_proj_example (1) disconnected node: la_oenb[7]
+Cell user_proj_example (1) disconnected node: la_oenb[6]
+Cell user_proj_example (1) disconnected node: la_oenb[5]
+Cell user_proj_example (1) disconnected node: la_oenb[4]
+Cell user_proj_example (1) disconnected node: la_oenb[3]
+Cell user_proj_example (1) disconnected node: la_oenb[2]
+Cell user_proj_example (1) disconnected node: la_oenb[1]
+Cell user_proj_example (1) disconnected node: la_oenb[0]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[31]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[30]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[29]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[28]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[27]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[26]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[25]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[24]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[23]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[22]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[21]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[20]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[19]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[18]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[17]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[16]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[15]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[14]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[13]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[12]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[11]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[10]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[9]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[8]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[7]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[6]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[5]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[4]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[3]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[2]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[1]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[0]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[31]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[30]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[29]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[28]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[27]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[26]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[25]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[24]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[23]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[22]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[21]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[20]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[19]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[18]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[17]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[16]
+Cell user_proj_example (1) disconnected node: wbs_sel_i[3]
+Cell user_proj_example (1) disconnected node: wbs_sel_i[2]
+Class user_proj_example (0):  Merged 346769 parallel devices.
+Class user_proj_example (1):  Merged 346769 parallel devices.
+Cell user_proj_example (0) disconnected node: io_in[0]
+Cell user_proj_example (0) disconnected node: io_in[10]
+Cell user_proj_example (0) disconnected node: io_in[11]
+Cell user_proj_example (0) disconnected node: io_in[12]
+Cell user_proj_example (0) disconnected node: io_in[13]
+Cell user_proj_example (0) disconnected node: io_in[14]
+Cell user_proj_example (0) disconnected node: io_in[15]
+Cell user_proj_example (0) disconnected node: io_in[1]
+Cell user_proj_example (0) disconnected node: io_in[2]
+Cell user_proj_example (0) disconnected node: io_in[3]
+Cell user_proj_example (0) disconnected node: io_in[4]
+Cell user_proj_example (0) disconnected node: io_in[5]
+Cell user_proj_example (0) disconnected node: io_in[6]
+Cell user_proj_example (0) disconnected node: io_in[7]
+Cell user_proj_example (0) disconnected node: io_in[8]
+Cell user_proj_example (0) disconnected node: io_in[9]
+Cell user_proj_example (0) disconnected node: la_data_in[0]
+Cell user_proj_example (0) disconnected node: la_data_in[100]
+Cell user_proj_example (0) disconnected node: la_data_in[101]
+Cell user_proj_example (0) disconnected node: la_data_in[102]
+Cell user_proj_example (0) disconnected node: la_data_in[103]
+Cell user_proj_example (0) disconnected node: la_data_in[104]
+Cell user_proj_example (0) disconnected node: la_data_in[105]
+Cell user_proj_example (0) disconnected node: la_data_in[106]
+Cell user_proj_example (0) disconnected node: la_data_in[107]
+Cell user_proj_example (0) disconnected node: la_data_in[108]
+Cell user_proj_example (0) disconnected node: la_data_in[109]
+Cell user_proj_example (0) disconnected node: la_data_in[10]
+Cell user_proj_example (0) disconnected node: la_data_in[110]
+Cell user_proj_example (0) disconnected node: la_data_in[111]
+Cell user_proj_example (0) disconnected node: la_data_in[112]
+Cell user_proj_example (0) disconnected node: la_data_in[113]
+Cell user_proj_example (0) disconnected node: la_data_in[114]
+Cell user_proj_example (0) disconnected node: la_data_in[115]
+Cell user_proj_example (0) disconnected node: la_data_in[116]
+Cell user_proj_example (0) disconnected node: la_data_in[117]
+Cell user_proj_example (0) disconnected node: la_data_in[118]
+Cell user_proj_example (0) disconnected node: la_data_in[119]
+Cell user_proj_example (0) disconnected node: la_data_in[11]
+Cell user_proj_example (0) disconnected node: la_data_in[120]
+Cell user_proj_example (0) disconnected node: la_data_in[121]
+Cell user_proj_example (0) disconnected node: la_data_in[122]
+Cell user_proj_example (0) disconnected node: la_data_in[123]
+Cell user_proj_example (0) disconnected node: la_data_in[124]
+Cell user_proj_example (0) disconnected node: la_data_in[125]
+Cell user_proj_example (0) disconnected node: la_data_in[126]
+Cell user_proj_example (0) disconnected node: la_data_in[127]
+Cell user_proj_example (0) disconnected node: la_data_in[12]
+Cell user_proj_example (0) disconnected node: la_data_in[13]
+Cell user_proj_example (0) disconnected node: la_data_in[14]
+Cell user_proj_example (0) disconnected node: la_data_in[15]
+Cell user_proj_example (0) disconnected node: la_data_in[16]
+Cell user_proj_example (0) disconnected node: la_data_in[17]
+Cell user_proj_example (0) disconnected node: la_data_in[18]
+Cell user_proj_example (0) disconnected node: la_data_in[19]
+Cell user_proj_example (0) disconnected node: la_data_in[1]
+Cell user_proj_example (0) disconnected node: la_data_in[20]
+Cell user_proj_example (0) disconnected node: la_data_in[21]
+Cell user_proj_example (0) disconnected node: la_data_in[22]
+Cell user_proj_example (0) disconnected node: la_data_in[23]
+Cell user_proj_example (0) disconnected node: la_data_in[24]
+Cell user_proj_example (0) disconnected node: la_data_in[25]
+Cell user_proj_example (0) disconnected node: la_data_in[26]
+Cell user_proj_example (0) disconnected node: la_data_in[27]
+Cell user_proj_example (0) disconnected node: la_data_in[28]
+Cell user_proj_example (0) disconnected node: la_data_in[29]
+Cell user_proj_example (0) disconnected node: la_data_in[2]
+Cell user_proj_example (0) disconnected node: la_data_in[30]
+Cell user_proj_example (0) disconnected node: la_data_in[31]
+Cell user_proj_example (0) disconnected node: la_data_in[32]
+Cell user_proj_example (0) disconnected node: la_data_in[33]
+Cell user_proj_example (0) disconnected node: la_data_in[34]
+Cell user_proj_example (0) disconnected node: la_data_in[35]
+Cell user_proj_example (0) disconnected node: la_data_in[36]
+Cell user_proj_example (0) disconnected node: la_data_in[37]
+Cell user_proj_example (0) disconnected node: la_data_in[38]
+Cell user_proj_example (0) disconnected node: la_data_in[39]
+Cell user_proj_example (0) disconnected node: la_data_in[3]
+Cell user_proj_example (0) disconnected node: la_data_in[40]
+Cell user_proj_example (0) disconnected node: la_data_in[41]
+Cell user_proj_example (0) disconnected node: la_data_in[42]
+Cell user_proj_example (0) disconnected node: la_data_in[43]
+Cell user_proj_example (0) disconnected node: la_data_in[44]
+Cell user_proj_example (0) disconnected node: la_data_in[45]
+Cell user_proj_example (0) disconnected node: la_data_in[46]
+Cell user_proj_example (0) disconnected node: la_data_in[47]
+Cell user_proj_example (0) disconnected node: la_data_in[4]
+Cell user_proj_example (0) disconnected node: la_data_in[5]
+Cell user_proj_example (0) disconnected node: la_data_in[66]
+Cell user_proj_example (0) disconnected node: la_data_in[67]
+Cell user_proj_example (0) disconnected node: la_data_in[68]
+Cell user_proj_example (0) disconnected node: la_data_in[69]
+Cell user_proj_example (0) disconnected node: la_data_in[6]
+Cell user_proj_example (0) disconnected node: la_data_in[70]
+Cell user_proj_example (0) disconnected node: la_data_in[71]
+Cell user_proj_example (0) disconnected node: la_data_in[72]
+Cell user_proj_example (0) disconnected node: la_data_in[73]
+Cell user_proj_example (0) disconnected node: la_data_in[74]
+Cell user_proj_example (0) disconnected node: la_data_in[75]
+Cell user_proj_example (0) disconnected node: la_data_in[76]
+Cell user_proj_example (0) disconnected node: la_data_in[77]
+Cell user_proj_example (0) disconnected node: la_data_in[78]
+Cell user_proj_example (0) disconnected node: la_data_in[79]
+Cell user_proj_example (0) disconnected node: la_data_in[7]
+Cell user_proj_example (0) disconnected node: la_data_in[80]
+Cell user_proj_example (0) disconnected node: la_data_in[81]
+Cell user_proj_example (0) disconnected node: la_data_in[82]
+Cell user_proj_example (0) disconnected node: la_data_in[83]
+Cell user_proj_example (0) disconnected node: la_data_in[84]
+Cell user_proj_example (0) disconnected node: la_data_in[85]
+Cell user_proj_example (0) disconnected node: la_data_in[86]
+Cell user_proj_example (0) disconnected node: la_data_in[87]
+Cell user_proj_example (0) disconnected node: la_data_in[88]
+Cell user_proj_example (0) disconnected node: la_data_in[89]
+Cell user_proj_example (0) disconnected node: la_data_in[8]
+Cell user_proj_example (0) disconnected node: la_data_in[90]
+Cell user_proj_example (0) disconnected node: la_data_in[91]
+Cell user_proj_example (0) disconnected node: la_data_in[92]
+Cell user_proj_example (0) disconnected node: la_data_in[93]
+Cell user_proj_example (0) disconnected node: la_data_in[94]
+Cell user_proj_example (0) disconnected node: la_data_in[95]
+Cell user_proj_example (0) disconnected node: la_data_in[96]
+Cell user_proj_example (0) disconnected node: la_data_in[97]
+Cell user_proj_example (0) disconnected node: la_data_in[98]
+Cell user_proj_example (0) disconnected node: la_data_in[99]
+Cell user_proj_example (0) disconnected node: la_data_in[9]
+Cell user_proj_example (0) disconnected node: la_oenb[0]
+Cell user_proj_example (0) disconnected node: la_oenb[100]
+Cell user_proj_example (0) disconnected node: la_oenb[101]
+Cell user_proj_example (0) disconnected node: la_oenb[102]
+Cell user_proj_example (0) disconnected node: la_oenb[103]
+Cell user_proj_example (0) disconnected node: la_oenb[104]
+Cell user_proj_example (0) disconnected node: la_oenb[105]
+Cell user_proj_example (0) disconnected node: la_oenb[106]
+Cell user_proj_example (0) disconnected node: la_oenb[107]
+Cell user_proj_example (0) disconnected node: la_oenb[108]
+Cell user_proj_example (0) disconnected node: la_oenb[109]
+Cell user_proj_example (0) disconnected node: la_oenb[10]
+Cell user_proj_example (0) disconnected node: la_oenb[110]
+Cell user_proj_example (0) disconnected node: la_oenb[111]
+Cell user_proj_example (0) disconnected node: la_oenb[112]
+Cell user_proj_example (0) disconnected node: la_oenb[113]
+Cell user_proj_example (0) disconnected node: la_oenb[114]
+Cell user_proj_example (0) disconnected node: la_oenb[115]
+Cell user_proj_example (0) disconnected node: la_oenb[116]
+Cell user_proj_example (0) disconnected node: la_oenb[117]
+Cell user_proj_example (0) disconnected node: la_oenb[118]
+Cell user_proj_example (0) disconnected node: la_oenb[119]
+Cell user_proj_example (0) disconnected node: la_oenb[11]
+Cell user_proj_example (0) disconnected node: la_oenb[120]
+Cell user_proj_example (0) disconnected node: la_oenb[121]
+Cell user_proj_example (0) disconnected node: la_oenb[122]
+Cell user_proj_example (0) disconnected node: la_oenb[123]
+Cell user_proj_example (0) disconnected node: la_oenb[124]
+Cell user_proj_example (0) disconnected node: la_oenb[125]
+Cell user_proj_example (0) disconnected node: la_oenb[126]
+Cell user_proj_example (0) disconnected node: la_oenb[127]
+Cell user_proj_example (0) disconnected node: la_oenb[12]
+Cell user_proj_example (0) disconnected node: la_oenb[13]
+Cell user_proj_example (0) disconnected node: la_oenb[14]
+Cell user_proj_example (0) disconnected node: la_oenb[15]
+Cell user_proj_example (0) disconnected node: la_oenb[16]
+Cell user_proj_example (0) disconnected node: la_oenb[17]
+Cell user_proj_example (0) disconnected node: la_oenb[18]
+Cell user_proj_example (0) disconnected node: la_oenb[19]
+Cell user_proj_example (0) disconnected node: la_oenb[1]
+Cell user_proj_example (0) disconnected node: la_oenb[20]
+Cell user_proj_example (0) disconnected node: la_oenb[21]
+Cell user_proj_example (0) disconnected node: la_oenb[22]
+Cell user_proj_example (0) disconnected node: la_oenb[23]
+Cell user_proj_example (0) disconnected node: la_oenb[24]
+Cell user_proj_example (0) disconnected node: la_oenb[25]
+Cell user_proj_example (0) disconnected node: la_oenb[26]
+Cell user_proj_example (0) disconnected node: la_oenb[27]
+Cell user_proj_example (0) disconnected node: la_oenb[28]
+Cell user_proj_example (0) disconnected node: la_oenb[29]
+Cell user_proj_example (0) disconnected node: la_oenb[2]
+Cell user_proj_example (0) disconnected node: la_oenb[30]
+Cell user_proj_example (0) disconnected node: la_oenb[31]
+Cell user_proj_example (0) disconnected node: la_oenb[32]
+Cell user_proj_example (0) disconnected node: la_oenb[33]
+Cell user_proj_example (0) disconnected node: la_oenb[34]
+Cell user_proj_example (0) disconnected node: la_oenb[35]
+Cell user_proj_example (0) disconnected node: la_oenb[36]
+Cell user_proj_example (0) disconnected node: la_oenb[37]
+Cell user_proj_example (0) disconnected node: la_oenb[38]
+Cell user_proj_example (0) disconnected node: la_oenb[39]
+Cell user_proj_example (0) disconnected node: la_oenb[3]
+Cell user_proj_example (0) disconnected node: la_oenb[40]
+Cell user_proj_example (0) disconnected node: la_oenb[41]
+Cell user_proj_example (0) disconnected node: la_oenb[42]
+Cell user_proj_example (0) disconnected node: la_oenb[43]
+Cell user_proj_example (0) disconnected node: la_oenb[44]
+Cell user_proj_example (0) disconnected node: la_oenb[45]
+Cell user_proj_example (0) disconnected node: la_oenb[46]
+Cell user_proj_example (0) disconnected node: la_oenb[47]
+Cell user_proj_example (0) disconnected node: la_oenb[4]
+Cell user_proj_example (0) disconnected node: la_oenb[5]
+Cell user_proj_example (0) disconnected node: la_oenb[66]
+Cell user_proj_example (0) disconnected node: la_oenb[67]
+Cell user_proj_example (0) disconnected node: la_oenb[68]
+Cell user_proj_example (0) disconnected node: la_oenb[69]
+Cell user_proj_example (0) disconnected node: la_oenb[6]
+Cell user_proj_example (0) disconnected node: la_oenb[70]
+Cell user_proj_example (0) disconnected node: la_oenb[71]
+Cell user_proj_example (0) disconnected node: la_oenb[72]
+Cell user_proj_example (0) disconnected node: la_oenb[73]
+Cell user_proj_example (0) disconnected node: la_oenb[74]
+Cell user_proj_example (0) disconnected node: la_oenb[75]
+Cell user_proj_example (0) disconnected node: la_oenb[76]
+Cell user_proj_example (0) disconnected node: la_oenb[77]
+Cell user_proj_example (0) disconnected node: la_oenb[78]
+Cell user_proj_example (0) disconnected node: la_oenb[79]
+Cell user_proj_example (0) disconnected node: la_oenb[7]
+Cell user_proj_example (0) disconnected node: la_oenb[80]
+Cell user_proj_example (0) disconnected node: la_oenb[81]
+Cell user_proj_example (0) disconnected node: la_oenb[82]
+Cell user_proj_example (0) disconnected node: la_oenb[83]
+Cell user_proj_example (0) disconnected node: la_oenb[84]
+Cell user_proj_example (0) disconnected node: la_oenb[85]
+Cell user_proj_example (0) disconnected node: la_oenb[86]
+Cell user_proj_example (0) disconnected node: la_oenb[87]
+Cell user_proj_example (0) disconnected node: la_oenb[88]
+Cell user_proj_example (0) disconnected node: la_oenb[89]
+Cell user_proj_example (0) disconnected node: la_oenb[8]
+Cell user_proj_example (0) disconnected node: la_oenb[90]
+Cell user_proj_example (0) disconnected node: la_oenb[91]
+Cell user_proj_example (0) disconnected node: la_oenb[92]
+Cell user_proj_example (0) disconnected node: la_oenb[93]
+Cell user_proj_example (0) disconnected node: la_oenb[94]
+Cell user_proj_example (0) disconnected node: la_oenb[95]
+Cell user_proj_example (0) disconnected node: la_oenb[96]
+Cell user_proj_example (0) disconnected node: la_oenb[97]
+Cell user_proj_example (0) disconnected node: la_oenb[98]
+Cell user_proj_example (0) disconnected node: la_oenb[99]
+Cell user_proj_example (0) disconnected node: la_oenb[9]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[0]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[10]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[11]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[12]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[13]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[14]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[15]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[16]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[17]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[18]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[19]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[1]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[20]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[21]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[22]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[23]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[24]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[25]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[26]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[27]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[28]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[29]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[2]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[30]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[31]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[3]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[4]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[5]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[6]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[7]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[8]
+Cell user_proj_example (0) disconnected node: wbs_adr_i[9]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[16]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[17]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[18]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[19]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[20]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[21]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[22]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[23]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[24]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[25]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[26]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[27]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[28]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[29]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[30]
+Cell user_proj_example (0) disconnected node: wbs_dat_i[31]
+Cell user_proj_example (0) disconnected node: wbs_sel_i[2]
+Cell user_proj_example (0) disconnected node: wbs_sel_i[3]
+Cell user_proj_example (1) disconnected node: io_in[15]
+Cell user_proj_example (1) disconnected node: io_in[14]
+Cell user_proj_example (1) disconnected node: io_in[13]
+Cell user_proj_example (1) disconnected node: io_in[12]
+Cell user_proj_example (1) disconnected node: io_in[11]
+Cell user_proj_example (1) disconnected node: io_in[10]
+Cell user_proj_example (1) disconnected node: io_in[9]
+Cell user_proj_example (1) disconnected node: io_in[8]
+Cell user_proj_example (1) disconnected node: io_in[7]
+Cell user_proj_example (1) disconnected node: io_in[6]
+Cell user_proj_example (1) disconnected node: io_in[5]
+Cell user_proj_example (1) disconnected node: io_in[4]
+Cell user_proj_example (1) disconnected node: io_in[3]
+Cell user_proj_example (1) disconnected node: io_in[2]
+Cell user_proj_example (1) disconnected node: io_in[1]
+Cell user_proj_example (1) disconnected node: io_in[0]
+Cell user_proj_example (1) disconnected node: la_data_in[127]
+Cell user_proj_example (1) disconnected node: la_data_in[126]
+Cell user_proj_example (1) disconnected node: la_data_in[125]
+Cell user_proj_example (1) disconnected node: la_data_in[124]
+Cell user_proj_example (1) disconnected node: la_data_in[123]
+Cell user_proj_example (1) disconnected node: la_data_in[122]
+Cell user_proj_example (1) disconnected node: la_data_in[121]
+Cell user_proj_example (1) disconnected node: la_data_in[120]
+Cell user_proj_example (1) disconnected node: la_data_in[119]
+Cell user_proj_example (1) disconnected node: la_data_in[118]
+Cell user_proj_example (1) disconnected node: la_data_in[117]
+Cell user_proj_example (1) disconnected node: la_data_in[116]
+Cell user_proj_example (1) disconnected node: la_data_in[115]
+Cell user_proj_example (1) disconnected node: la_data_in[114]
+Cell user_proj_example (1) disconnected node: la_data_in[113]
+Cell user_proj_example (1) disconnected node: la_data_in[112]
+Cell user_proj_example (1) disconnected node: la_data_in[111]
+Cell user_proj_example (1) disconnected node: la_data_in[110]
+Cell user_proj_example (1) disconnected node: la_data_in[109]
+Cell user_proj_example (1) disconnected node: la_data_in[108]
+Cell user_proj_example (1) disconnected node: la_data_in[107]
+Cell user_proj_example (1) disconnected node: la_data_in[106]
+Cell user_proj_example (1) disconnected node: la_data_in[105]
+Cell user_proj_example (1) disconnected node: la_data_in[104]
+Cell user_proj_example (1) disconnected node: la_data_in[103]
+Cell user_proj_example (1) disconnected node: la_data_in[102]
+Cell user_proj_example (1) disconnected node: la_data_in[101]
+Cell user_proj_example (1) disconnected node: la_data_in[100]
+Cell user_proj_example (1) disconnected node: la_data_in[99]
+Cell user_proj_example (1) disconnected node: la_data_in[98]
+Cell user_proj_example (1) disconnected node: la_data_in[97]
+Cell user_proj_example (1) disconnected node: la_data_in[96]
+Cell user_proj_example (1) disconnected node: la_data_in[95]
+Cell user_proj_example (1) disconnected node: la_data_in[94]
+Cell user_proj_example (1) disconnected node: la_data_in[93]
+Cell user_proj_example (1) disconnected node: la_data_in[92]
+Cell user_proj_example (1) disconnected node: la_data_in[91]
+Cell user_proj_example (1) disconnected node: la_data_in[90]
+Cell user_proj_example (1) disconnected node: la_data_in[89]
+Cell user_proj_example (1) disconnected node: la_data_in[88]
+Cell user_proj_example (1) disconnected node: la_data_in[87]
+Cell user_proj_example (1) disconnected node: la_data_in[86]
+Cell user_proj_example (1) disconnected node: la_data_in[85]
+Cell user_proj_example (1) disconnected node: la_data_in[84]
+Cell user_proj_example (1) disconnected node: la_data_in[83]
+Cell user_proj_example (1) disconnected node: la_data_in[82]
+Cell user_proj_example (1) disconnected node: la_data_in[81]
+Cell user_proj_example (1) disconnected node: la_data_in[80]
+Cell user_proj_example (1) disconnected node: la_data_in[79]
+Cell user_proj_example (1) disconnected node: la_data_in[78]
+Cell user_proj_example (1) disconnected node: la_data_in[77]
+Cell user_proj_example (1) disconnected node: la_data_in[76]
+Cell user_proj_example (1) disconnected node: la_data_in[75]
+Cell user_proj_example (1) disconnected node: la_data_in[74]
+Cell user_proj_example (1) disconnected node: la_data_in[73]
+Cell user_proj_example (1) disconnected node: la_data_in[72]
+Cell user_proj_example (1) disconnected node: la_data_in[71]
+Cell user_proj_example (1) disconnected node: la_data_in[70]
+Cell user_proj_example (1) disconnected node: la_data_in[69]
+Cell user_proj_example (1) disconnected node: la_data_in[68]
+Cell user_proj_example (1) disconnected node: la_data_in[67]
+Cell user_proj_example (1) disconnected node: la_data_in[66]
+Cell user_proj_example (1) disconnected node: la_data_in[47]
+Cell user_proj_example (1) disconnected node: la_data_in[46]
+Cell user_proj_example (1) disconnected node: la_data_in[45]
+Cell user_proj_example (1) disconnected node: la_data_in[44]
+Cell user_proj_example (1) disconnected node: la_data_in[43]
+Cell user_proj_example (1) disconnected node: la_data_in[42]
+Cell user_proj_example (1) disconnected node: la_data_in[41]
+Cell user_proj_example (1) disconnected node: la_data_in[40]
+Cell user_proj_example (1) disconnected node: la_data_in[39]
+Cell user_proj_example (1) disconnected node: la_data_in[38]
+Cell user_proj_example (1) disconnected node: la_data_in[37]
+Cell user_proj_example (1) disconnected node: la_data_in[36]
+Cell user_proj_example (1) disconnected node: la_data_in[35]
+Cell user_proj_example (1) disconnected node: la_data_in[34]
+Cell user_proj_example (1) disconnected node: la_data_in[33]
+Cell user_proj_example (1) disconnected node: la_data_in[32]
+Cell user_proj_example (1) disconnected node: la_data_in[31]
+Cell user_proj_example (1) disconnected node: la_data_in[30]
+Cell user_proj_example (1) disconnected node: la_data_in[29]
+Cell user_proj_example (1) disconnected node: la_data_in[28]
+Cell user_proj_example (1) disconnected node: la_data_in[27]
+Cell user_proj_example (1) disconnected node: la_data_in[26]
+Cell user_proj_example (1) disconnected node: la_data_in[25]
+Cell user_proj_example (1) disconnected node: la_data_in[24]
+Cell user_proj_example (1) disconnected node: la_data_in[23]
+Cell user_proj_example (1) disconnected node: la_data_in[22]
+Cell user_proj_example (1) disconnected node: la_data_in[21]
+Cell user_proj_example (1) disconnected node: la_data_in[20]
+Cell user_proj_example (1) disconnected node: la_data_in[19]
+Cell user_proj_example (1) disconnected node: la_data_in[18]
+Cell user_proj_example (1) disconnected node: la_data_in[17]
+Cell user_proj_example (1) disconnected node: la_data_in[16]
+Cell user_proj_example (1) disconnected node: la_data_in[15]
+Cell user_proj_example (1) disconnected node: la_data_in[14]
+Cell user_proj_example (1) disconnected node: la_data_in[13]
+Cell user_proj_example (1) disconnected node: la_data_in[12]
+Cell user_proj_example (1) disconnected node: la_data_in[11]
+Cell user_proj_example (1) disconnected node: la_data_in[10]
+Cell user_proj_example (1) disconnected node: la_data_in[9]
+Cell user_proj_example (1) disconnected node: la_data_in[8]
+Cell user_proj_example (1) disconnected node: la_data_in[7]
+Cell user_proj_example (1) disconnected node: la_data_in[6]
+Cell user_proj_example (1) disconnected node: la_data_in[5]
+Cell user_proj_example (1) disconnected node: la_data_in[4]
+Cell user_proj_example (1) disconnected node: la_data_in[3]
+Cell user_proj_example (1) disconnected node: la_data_in[2]
+Cell user_proj_example (1) disconnected node: la_data_in[1]
+Cell user_proj_example (1) disconnected node: la_data_in[0]
+Cell user_proj_example (1) disconnected node: la_oenb[127]
+Cell user_proj_example (1) disconnected node: la_oenb[126]
+Cell user_proj_example (1) disconnected node: la_oenb[125]
+Cell user_proj_example (1) disconnected node: la_oenb[124]
+Cell user_proj_example (1) disconnected node: la_oenb[123]
+Cell user_proj_example (1) disconnected node: la_oenb[122]
+Cell user_proj_example (1) disconnected node: la_oenb[121]
+Cell user_proj_example (1) disconnected node: la_oenb[120]
+Cell user_proj_example (1) disconnected node: la_oenb[119]
+Cell user_proj_example (1) disconnected node: la_oenb[118]
+Cell user_proj_example (1) disconnected node: la_oenb[117]
+Cell user_proj_example (1) disconnected node: la_oenb[116]
+Cell user_proj_example (1) disconnected node: la_oenb[115]
+Cell user_proj_example (1) disconnected node: la_oenb[114]
+Cell user_proj_example (1) disconnected node: la_oenb[113]
+Cell user_proj_example (1) disconnected node: la_oenb[112]
+Cell user_proj_example (1) disconnected node: la_oenb[111]
+Cell user_proj_example (1) disconnected node: la_oenb[110]
+Cell user_proj_example (1) disconnected node: la_oenb[109]
+Cell user_proj_example (1) disconnected node: la_oenb[108]
+Cell user_proj_example (1) disconnected node: la_oenb[107]
+Cell user_proj_example (1) disconnected node: la_oenb[106]
+Cell user_proj_example (1) disconnected node: la_oenb[105]
+Cell user_proj_example (1) disconnected node: la_oenb[104]
+Cell user_proj_example (1) disconnected node: la_oenb[103]
+Cell user_proj_example (1) disconnected node: la_oenb[102]
+Cell user_proj_example (1) disconnected node: la_oenb[101]
+Cell user_proj_example (1) disconnected node: la_oenb[100]
+Cell user_proj_example (1) disconnected node: la_oenb[99]
+Cell user_proj_example (1) disconnected node: la_oenb[98]
+Cell user_proj_example (1) disconnected node: la_oenb[97]
+Cell user_proj_example (1) disconnected node: la_oenb[96]
+Cell user_proj_example (1) disconnected node: la_oenb[95]
+Cell user_proj_example (1) disconnected node: la_oenb[94]
+Cell user_proj_example (1) disconnected node: la_oenb[93]
+Cell user_proj_example (1) disconnected node: la_oenb[92]
+Cell user_proj_example (1) disconnected node: la_oenb[91]
+Cell user_proj_example (1) disconnected node: la_oenb[90]
+Cell user_proj_example (1) disconnected node: la_oenb[89]
+Cell user_proj_example (1) disconnected node: la_oenb[88]
+Cell user_proj_example (1) disconnected node: la_oenb[87]
+Cell user_proj_example (1) disconnected node: la_oenb[86]
+Cell user_proj_example (1) disconnected node: la_oenb[85]
+Cell user_proj_example (1) disconnected node: la_oenb[84]
+Cell user_proj_example (1) disconnected node: la_oenb[83]
+Cell user_proj_example (1) disconnected node: la_oenb[82]
+Cell user_proj_example (1) disconnected node: la_oenb[81]
+Cell user_proj_example (1) disconnected node: la_oenb[80]
+Cell user_proj_example (1) disconnected node: la_oenb[79]
+Cell user_proj_example (1) disconnected node: la_oenb[78]
+Cell user_proj_example (1) disconnected node: la_oenb[77]
+Cell user_proj_example (1) disconnected node: la_oenb[76]
+Cell user_proj_example (1) disconnected node: la_oenb[75]
+Cell user_proj_example (1) disconnected node: la_oenb[74]
+Cell user_proj_example (1) disconnected node: la_oenb[73]
+Cell user_proj_example (1) disconnected node: la_oenb[72]
+Cell user_proj_example (1) disconnected node: la_oenb[71]
+Cell user_proj_example (1) disconnected node: la_oenb[70]
+Cell user_proj_example (1) disconnected node: la_oenb[69]
+Cell user_proj_example (1) disconnected node: la_oenb[68]
+Cell user_proj_example (1) disconnected node: la_oenb[67]
+Cell user_proj_example (1) disconnected node: la_oenb[66]
+Cell user_proj_example (1) disconnected node: la_oenb[47]
+Cell user_proj_example (1) disconnected node: la_oenb[46]
+Cell user_proj_example (1) disconnected node: la_oenb[45]
+Cell user_proj_example (1) disconnected node: la_oenb[44]
+Cell user_proj_example (1) disconnected node: la_oenb[43]
+Cell user_proj_example (1) disconnected node: la_oenb[42]
+Cell user_proj_example (1) disconnected node: la_oenb[41]
+Cell user_proj_example (1) disconnected node: la_oenb[40]
+Cell user_proj_example (1) disconnected node: la_oenb[39]
+Cell user_proj_example (1) disconnected node: la_oenb[38]
+Cell user_proj_example (1) disconnected node: la_oenb[37]
+Cell user_proj_example (1) disconnected node: la_oenb[36]
+Cell user_proj_example (1) disconnected node: la_oenb[35]
+Cell user_proj_example (1) disconnected node: la_oenb[34]
+Cell user_proj_example (1) disconnected node: la_oenb[33]
+Cell user_proj_example (1) disconnected node: la_oenb[32]
+Cell user_proj_example (1) disconnected node: la_oenb[31]
+Cell user_proj_example (1) disconnected node: la_oenb[30]
+Cell user_proj_example (1) disconnected node: la_oenb[29]
+Cell user_proj_example (1) disconnected node: la_oenb[28]
+Cell user_proj_example (1) disconnected node: la_oenb[27]
+Cell user_proj_example (1) disconnected node: la_oenb[26]
+Cell user_proj_example (1) disconnected node: la_oenb[25]
+Cell user_proj_example (1) disconnected node: la_oenb[24]
+Cell user_proj_example (1) disconnected node: la_oenb[23]
+Cell user_proj_example (1) disconnected node: la_oenb[22]
+Cell user_proj_example (1) disconnected node: la_oenb[21]
+Cell user_proj_example (1) disconnected node: la_oenb[20]
+Cell user_proj_example (1) disconnected node: la_oenb[19]
+Cell user_proj_example (1) disconnected node: la_oenb[18]
+Cell user_proj_example (1) disconnected node: la_oenb[17]
+Cell user_proj_example (1) disconnected node: la_oenb[16]
+Cell user_proj_example (1) disconnected node: la_oenb[15]
+Cell user_proj_example (1) disconnected node: la_oenb[14]
+Cell user_proj_example (1) disconnected node: la_oenb[13]
+Cell user_proj_example (1) disconnected node: la_oenb[12]
+Cell user_proj_example (1) disconnected node: la_oenb[11]
+Cell user_proj_example (1) disconnected node: la_oenb[10]
+Cell user_proj_example (1) disconnected node: la_oenb[9]
+Cell user_proj_example (1) disconnected node: la_oenb[8]
+Cell user_proj_example (1) disconnected node: la_oenb[7]
+Cell user_proj_example (1) disconnected node: la_oenb[6]
+Cell user_proj_example (1) disconnected node: la_oenb[5]
+Cell user_proj_example (1) disconnected node: la_oenb[4]
+Cell user_proj_example (1) disconnected node: la_oenb[3]
+Cell user_proj_example (1) disconnected node: la_oenb[2]
+Cell user_proj_example (1) disconnected node: la_oenb[1]
+Cell user_proj_example (1) disconnected node: la_oenb[0]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[31]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[30]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[29]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[28]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[27]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[26]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[25]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[24]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[23]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[22]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[21]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[20]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[19]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[18]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[17]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[16]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[15]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[14]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[13]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[12]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[11]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[10]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[9]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[8]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[7]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[6]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[5]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[4]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[3]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[2]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[1]
+Cell user_proj_example (1) disconnected node: wbs_adr_i[0]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[31]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[30]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[29]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[28]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[27]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[26]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[25]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[24]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[23]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[22]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[21]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[20]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[19]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[18]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[17]
+Cell user_proj_example (1) disconnected node: wbs_dat_i[16]
+Cell user_proj_example (1) disconnected node: wbs_sel_i[3]
+Cell user_proj_example (1) disconnected node: wbs_sel_i[2]
+Subcircuit summary:
+Circuit 1: user_proj_example               |Circuit 2: user_proj_example               
+-------------------------------------------|-------------------------------------------
+sky130_ef_sc_hd__decap_12 (275419->1)      |sky130_ef_sc_hd__decap_12 (275419->1)      
+sky130_fd_sc_hd__decap_6 (67936->1)        |sky130_fd_sc_hd__decap_6 (67936->1)        
+sky130_fd_sc_hd__decap_8 (484->1)          |sky130_fd_sc_hd__decap_8 (484->1)          
+sky130_fd_sc_hd__decap_3 (1862->1)         |sky130_fd_sc_hd__decap_3 (1862->1)         
+sky130_fd_sc_hd__diode_2 (719->213)        |sky130_fd_sc_hd__diode_2 (719->213)        
+sky130_fd_sc_hd__buf_1 (34)                |sky130_fd_sc_hd__buf_1 (34)                
+sky130_fd_sc_hd__buf_2 (138)               |sky130_fd_sc_hd__buf_2 (138)               
+sky130_fd_sc_hd__dfxtp_2 (5)               |sky130_fd_sc_hd__dfxtp_2 (5)               
+sky130_fd_sc_hd__conb_1 (262)              |sky130_fd_sc_hd__conb_1 (262)              
+sky130_fd_sc_hd__decap_4 (567->1)          |sky130_fd_sc_hd__decap_4 (567->1)          
+sky130_fd_sc_hd__dlygate4sd3_1 (174)       |sky130_fd_sc_hd__dlygate4sd3_1 (174)       
+sky130_fd_sc_hd__dfxtp_4 (15)              |sky130_fd_sc_hd__dfxtp_4 (15)              
+sky130_fd_sc_hd__and3_1 (7)                |sky130_fd_sc_hd__and3_1 (7)                
+sky130_fd_sc_hd__buf_12 (83)               |sky130_fd_sc_hd__buf_12 (83)               
+sky130_fd_sc_hd__clkbuf_16 (13)            |sky130_fd_sc_hd__clkbuf_16 (13)            
+sky130_fd_sc_hd__and2_1 (13)               |sky130_fd_sc_hd__and2_1 (13)               
+sky130_fd_sc_hd__mux2_1 (17)               |sky130_fd_sc_hd__mux2_1 (17)               
+sky130_fd_sc_hd__a31o_1 (12)               |sky130_fd_sc_hd__a31o_1 (12)               
+sky130_fd_sc_hd__a32o_1 (17)               |sky130_fd_sc_hd__a32o_1 (17)               
+sky130_fd_sc_hd__inv_2 (20)                |sky130_fd_sc_hd__inv_2 (20)                
+sky130_fd_sc_hd__dfxtp_1 (13)              |sky130_fd_sc_hd__dfxtp_1 (13)              
+sky130_fd_sc_hd__or2_1 (4)                 |sky130_fd_sc_hd__or2_1 (4)                 
+sky130_fd_sc_hd__clkbuf_8 (11)             |sky130_fd_sc_hd__clkbuf_8 (11)             
+sky130_fd_sc_hd__nand4_1 (1)               |sky130_fd_sc_hd__nand4_1 (1)               
+sky130_fd_sc_hd__and4_2 (3)                |sky130_fd_sc_hd__and4_2 (3)                
+sky130_fd_sc_hd__and4b_2 (1)               |sky130_fd_sc_hd__and4b_2 (1)               
+sky130_fd_sc_hd__o21a_1 (7)                |sky130_fd_sc_hd__o21a_1 (7)                
+sky130_fd_sc_hd__o2111a_1 (1)              |sky130_fd_sc_hd__o2111a_1 (1)              
+sky130_fd_sc_hd__and3b_1 (1)               |sky130_fd_sc_hd__and3b_1 (1)               
+sky130_fd_sc_hd__o211a_1 (1)               |sky130_fd_sc_hd__o211a_1 (1)               
+sky130_fd_sc_hd__and3_2 (2)                |sky130_fd_sc_hd__and3_2 (2)                
+sky130_fd_sc_hd__nand3_1 (4)               |sky130_fd_sc_hd__nand3_1 (4)               
+sky130_fd_sc_hd__xor2_1 (1)                |sky130_fd_sc_hd__xor2_1 (1)                
+sky130_fd_sc_hd__a21o_1 (9)                |sky130_fd_sc_hd__a21o_1 (9)                
+sky130_fd_sc_hd__a22o_1 (1)                |sky130_fd_sc_hd__a22o_1 (1)                
+sky130_fd_sc_hd__a21o_2 (1)                |sky130_fd_sc_hd__a21o_2 (1)                
+sky130_fd_sc_hd__nand2_1 (7)               |sky130_fd_sc_hd__nand2_1 (7)               
+sky130_fd_sc_hd__a2bb2o_1 (1)              |sky130_fd_sc_hd__a2bb2o_1 (1)              
+sky130_fd_sc_hd__buf_8 (10)                |sky130_fd_sc_hd__buf_8 (10)                
+sky130_fd_sc_hd__dlymetal6s2s_1 (1)        |sky130_fd_sc_hd__dlymetal6s2s_1 (1)        
+sky130_fd_sc_hd__buf_6 (6)                 |sky130_fd_sc_hd__buf_6 (6)                 
+sky130_fd_sc_hd__clkbuf_2 (13)             |sky130_fd_sc_hd__clkbuf_2 (13)             
+sky130_fd_sc_hd__clkbuf_4 (15)             |sky130_fd_sc_hd__clkbuf_4 (15)             
+sky130_fd_sc_hd__buf_4 (2)                 |sky130_fd_sc_hd__buf_4 (2)                 
+sky130_fd_sc_hd__nand2_8 (2)               |sky130_fd_sc_hd__nand2_8 (2)               
+sky130_fd_sc_hd__nor2_4 (1)                |sky130_fd_sc_hd__nor2_4 (1)                
+sky130_fd_sc_hd__and2b_1 (1)               |sky130_fd_sc_hd__and2b_1 (1)               
+sky130_fd_sc_hd__inv_12 (1)                |sky130_fd_sc_hd__inv_12 (1)                
+sky130_fd_sc_hd__o21ai_2 (1)               |sky130_fd_sc_hd__o21ai_2 (1)               
+sky130_fd_sc_hd__nand2b_1 (1)              |sky130_fd_sc_hd__nand2b_1 (1)              
+sky130_fd_sc_hd__a221o_1 (1)               |sky130_fd_sc_hd__a221o_1 (1)               
+Number of devices: 1152                    |Number of devices: 1152                    
+Number of nets: 1257                       |Number of nets: 1257                       
+---------------------------------------------------------------------------------------
+Resolving symmetries by property value.
+Resolving symmetries by pin name.
+Netlists match with 4 symmetries.
+
+Subcircuit pins:
+Circuit 1: user_proj_example               |Circuit 2: user_proj_example               
+-------------------------------------------|-------------------------------------------
+la_data_out[124]                           |la_data_out[124]                           
+la_data_out[91]                            |la_data_out[91]                            
+irq[1]                                     |irq[1]                                     
+la_data_out[108]                           |la_data_out[108]                           
+la_data_out[125]                           |la_data_out[125]                           
+la_data_out[32]                            |la_data_out[32]                            
+la_data_out[92]                            |la_data_out[92]                            
+irq[2]                                     |irq[2]                                     
+la_data_out[109]                           |la_data_out[109]                           
+la_data_out[16]                            |la_data_out[16]                            
+la_data_out[126]                           |la_data_out[126]                           
+la_data_out[33]                            |la_data_out[33]                            
+la_data_out[93]                            |la_data_out[93]                            
+la_data_out[110]                           |la_data_out[110]                           
+la_data_out[17]                            |la_data_out[17]                            
+la_data_out[127]                           |la_data_out[127]                           
+la_data_out[34]                            |la_data_out[34]                            
+la_data_out[111]                           |la_data_out[111]                           
+la_data_out[18]                            |la_data_out[18]                            
+wbs_dat_o[16]                              |wbs_dat_o[16]                              
+la_data_out[35]                            |la_data_out[35]                            
+la_data_out[52]                            |la_data_out[52]                            
+la_data_out[112]                           |la_data_out[112]                           
+la_data_out[19]                            |la_data_out[19]                            
+wbs_dat_o[17]                              |wbs_dat_o[17]                              
+la_data_out[36]                            |la_data_out[36]                            
+la_data_out[113]                           |la_data_out[113]                           
+la_data_out[20]                            |la_data_out[20]                            
+wbs_dat_o[18]                              |wbs_dat_o[18]                              
+la_data_out[37]                            |la_data_out[37]                            
+la_data_out[21]                            |la_data_out[21]                            
+la_data_out[54]                            |la_data_out[54]                            
+wbs_dat_o[19]                              |wbs_dat_o[19]                              
+la_data_out[38]                            |la_data_out[38]                            
+la_data_out[55]                            |la_data_out[55]                            
+wbs_dat_o[20]                              |wbs_dat_o[20]                              
+la_data_out[39]                            |la_data_out[39]                            
+la_data_out[56]                            |la_data_out[56]                            
+wbs_dat_o[21]                              |wbs_dat_o[21]                              
+la_data_out[40]                            |la_data_out[40]                            
+la_data_out[57]                            |la_data_out[57]                            
+la_data_out[41]                            |la_data_out[41]                            
+la_data_out[74]                            |la_data_out[74]                            
+la_data_out[58]                            |la_data_out[58]                            
+la_data_out[75]                            |la_data_out[75]                            
+la_data_out[59]                            |la_data_out[59]                            
+la_data_out[76]                            |la_data_out[76]                            
+la_data_out[60]                            |la_data_out[60]                            
+la_data_out[77]                            |la_data_out[77]                            
+la_data_out[94]                            |la_data_out[94]                            
+la_data_out[61]                            |la_data_out[61]                            
+la_data_out[78]                            |la_data_out[78]                            
+la_data_out[95]                            |la_data_out[95]                            
+la_data_out[62]                            |la_data_out[62]                            
+la_data_out[79]                            |la_data_out[79]                            
+la_data_out[96]                            |la_data_out[96]                            
+la_data_out[63]                            |la_data_out[63]                            
+la_data_out[80]                            |la_data_out[80]                            
+la_data_out[97]                            |la_data_out[97]                            
+la_data_out[114]                           |la_data_out[114]                           
+la_data_out[81]                            |la_data_out[81]                            
+la_data_out[98]                            |la_data_out[98]                            
+la_data_out[115]                           |la_data_out[115]                           
+la_data_out[22]                            |la_data_out[22]                            
+la_data_out[82]                            |la_data_out[82]                            
+la_data_out[99]                            |la_data_out[99]                            
+la_data_out[116]                           |la_data_out[116]                           
+la_data_out[23]                            |la_data_out[23]                            
+la_data_out[83]                            |la_data_out[83]                            
+la_data_out[100]                           |la_data_out[100]                           
+la_data_out[117]                           |la_data_out[117]                           
+la_data_out[24]                            |la_data_out[24]                            
+wbs_dat_o[22]                              |wbs_dat_o[22]                              
+la_data_out[101]                           |la_data_out[101]                           
+la_data_out[118]                           |la_data_out[118]                           
+la_data_out[25]                            |la_data_out[25]                            
+wbs_dat_o[23]                              |wbs_dat_o[23]                              
+la_data_out[42]                            |la_data_out[42]                            
+la_data_out[102]                           |la_data_out[102]                           
+la_data_out[119]                           |la_data_out[119]                           
+la_data_out[26]                            |la_data_out[26]                            
+wbs_dat_o[24]                              |wbs_dat_o[24]                              
+la_data_out[43]                            |la_data_out[43]                            
+la_data_out[103]                           |la_data_out[103]                           
+la_data_out[120]                           |la_data_out[120]                           
+la_data_out[27]                            |la_data_out[27]                            
+wbs_dat_o[25]                              |wbs_dat_o[25]                              
+la_data_out[44]                            |la_data_out[44]                            
+la_data_out[121]                           |la_data_out[121]                           
+la_data_out[28]                            |la_data_out[28]                            
+wbs_dat_o[26]                              |wbs_dat_o[26]                              
+la_data_out[45]                            |la_data_out[45]                            
+la_data_out[122]                           |la_data_out[122]                           
+la_data_out[29]                            |la_data_out[29]                            
+wbs_dat_o[27]                              |wbs_dat_o[27]                              
+la_data_out[46]                            |la_data_out[46]                            
+la_data_out[123]                           |la_data_out[123]                           
+la_data_out[30]                            |la_data_out[30]                            
+wbs_dat_o[28]                              |wbs_dat_o[28]                              
+la_data_out[47]                            |la_data_out[47]                            
+la_data_out[31]                            |la_data_out[31]                            
+la_data_out[64]                            |la_data_out[64]                            
+wbs_dat_o[29]                              |wbs_dat_o[29]                              
+la_data_out[48]                            |la_data_out[48]                            
+la_data_out[65]                            |la_data_out[65]                            
+wbs_dat_o[30]                              |wbs_dat_o[30]                              
+la_data_out[49]                            |la_data_out[49]                            
+la_data_out[66]                            |la_data_out[66]                            
+wbs_dat_o[31]                              |wbs_dat_o[31]                              
+la_data_out[50]                            |la_data_out[50]                            
+la_data_out[67]                            |la_data_out[67]                            
+la_data_out[51]                            |la_data_out[51]                            
+la_data_out[84]                            |la_data_out[84]                            
+la_data_out[68]                            |la_data_out[68]                            
+la_data_out[85]                            |la_data_out[85]                            
+la_data_out[69]                            |la_data_out[69]                            
+la_data_out[86]                            |la_data_out[86]                            
+la_data_out[53]                            |la_data_out[53]                            
+la_data_out[70]                            |la_data_out[70]                            
+la_data_out[87]                            |la_data_out[87]                            
+la_data_out[104]                           |la_data_out[104]                           
+la_data_out[71]                            |la_data_out[71]                            
+la_data_out[88]                            |la_data_out[88]                            
+la_data_out[105]                           |la_data_out[105]                           
+la_data_out[72]                            |la_data_out[72]                            
+la_data_out[89]                            |la_data_out[89]                            
+la_data_out[106]                           |la_data_out[106]                           
+la_data_out[73]                            |la_data_out[73]                            
+la_data_out[90]                            |la_data_out[90]                            
+irq[0]                                     |irq[0]                                     
+la_data_out[107]                           |la_data_out[107]                           
+la_oenb[58]                                |la_oenb[58]                                
+la_data_in[64]                             |la_data_in[64]                             
+la_oenb[64]                                |la_oenb[64]                                
+wbs_dat_i[13]                              |wbs_dat_i[13]                              
+wbs_dat_i[14]                              |wbs_dat_i[14]                              
+wbs_dat_i[15]                              |wbs_dat_i[15]                              
+wbs_dat_i[12]                              |wbs_dat_i[12]                              
+wbs_dat_i[10]                              |wbs_dat_i[10]                              
+wb_rst_i                                   |wb_rst_i                                   
+wbs_dat_i[1]                               |wbs_dat_i[1]                               
+wbs_dat_i[3]                               |wbs_dat_i[3]                               
+wbs_dat_i[0]                               |wbs_dat_i[0]                               
+wbs_dat_i[2]                               |wbs_dat_i[2]                               
+wbs_dat_i[4]                               |wbs_dat_i[4]                               
+wbs_dat_i[5]                               |wbs_dat_i[5]                               
+wbs_dat_i[8]                               |wbs_dat_i[8]                               
+wbs_dat_i[6]                               |wbs_dat_i[6]                               
+wbs_dat_i[7]                               |wbs_dat_i[7]                               
+wbs_dat_i[11]                              |wbs_dat_i[11]                              
+wbs_dat_i[9]                               |wbs_dat_i[9]                               
+wbs_sel_i[0]                               |wbs_sel_i[0]                               
+wbs_sel_i[1]                               |wbs_sel_i[1]                               
+wbs_stb_i                                  |wbs_stb_i                                  
+wbs_we_i                                   |wbs_we_i                                   
+io_oeb[15]                                 |io_oeb[15]                                 
+io_out[12]                                 |io_out[12]                                 
+io_out[11]                                 |io_out[11]                                 
+io_out[13]                                 |io_out[13]                                 
+io_out[15]                                 |io_out[15]                                 
+io_out[14]                                 |io_out[14]                                 
+io_out[4]                                  |io_out[4]                                  
+io_out[2]                                  |io_out[2]                                  
+io_out[1]                                  |io_out[1]                                  
+la_data_out[10]                            |la_data_out[10]                            
+la_data_out[0]                             |la_data_out[0]                             
+la_data_out[11]                            |la_data_out[11]                            
+la_data_out[12]                            |la_data_out[12]                            
+la_data_out[9]                             |la_data_out[9]                             
+la_data_out[13]                            |la_data_out[13]                            
+la_data_out[4]                             |la_data_out[4]                             
+io_out[7]                                  |io_out[7]                                  
+la_data_out[1]                             |la_data_out[1]                             
+io_out[6]                                  |io_out[6]                                  
+la_data_out[14]                            |la_data_out[14]                            
+la_data_out[15]                            |la_data_out[15]                            
+la_data_out[3]                             |la_data_out[3]                             
+la_data_out[5]                             |la_data_out[5]                             
+la_data_out[6]                             |la_data_out[6]                             
+la_data_out[7]                             |la_data_out[7]                             
+la_data_out[8]                             |la_data_out[8]                             
+io_out[3]                                  |io_out[3]                                  
+io_out[5]                                  |io_out[5]                                  
+io_out[0]                                  |io_out[0]                                  
+io_oeb[7]                                  |io_oeb[7]                                  
+io_oeb[6]                                  |io_oeb[6]                                  
+io_oeb[5]                                  |io_oeb[5]                                  
+io_oeb[0]                                  |io_oeb[0]                                  
+io_oeb[4]                                  |io_oeb[4]                                  
+io_oeb[3]                                  |io_oeb[3]                                  
+io_oeb[2]                                  |io_oeb[2]                                  
+io_oeb[1]                                  |io_oeb[1]                                  
+io_oeb[9]                                  |io_oeb[9]                                  
+io_oeb[13]                                 |io_oeb[13]                                 
+io_oeb[8]                                  |io_oeb[8]                                  
+io_oeb[12]                                 |io_oeb[12]                                 
+io_oeb[11]                                 |io_oeb[11]                                 
+io_oeb[10]                                 |io_oeb[10]                                 
+io_oeb[14]                                 |io_oeb[14]                                 
+la_data_out[2]                             |la_data_out[2]                             
+io_out[9]                                  |io_out[9]                                  
+wbs_ack_o                                  |wbs_ack_o                                  
+wbs_dat_o[2]                               |wbs_dat_o[2]                               
+wbs_dat_o[0]                               |wbs_dat_o[0]                               
+wbs_dat_o[1]                               |wbs_dat_o[1]                               
+wbs_dat_o[3]                               |wbs_dat_o[3]                               
+wbs_dat_o[15]                              |wbs_dat_o[15]                              
+wbs_dat_o[14]                              |wbs_dat_o[14]                              
+wbs_dat_o[4]                               |wbs_dat_o[4]                               
+wbs_dat_o[5]                               |wbs_dat_o[5]                               
+wbs_dat_o[7]                               |wbs_dat_o[7]                               
+wbs_dat_o[9]                               |wbs_dat_o[9]                               
+wbs_dat_o[10]                              |wbs_dat_o[10]                              
+wbs_dat_o[12]                              |wbs_dat_o[12]                              
+wbs_dat_o[11]                              |wbs_dat_o[11]                              
+wbs_dat_o[13]                              |wbs_dat_o[13]                              
+wbs_dat_o[6]                               |wbs_dat_o[6]                               
+wbs_dat_o[8]                               |wbs_dat_o[8]                               
+io_out[8]                                  |io_out[8]                                  
+io_out[10]                                 |io_out[10]                                 
+wb_clk_i                                   |wb_clk_i                                   
+wbs_cyc_i                                  |wbs_cyc_i                                  
+la_data_in[48]                             |la_data_in[48]                             
+la_data_in[50]                             |la_data_in[50]                             
+la_data_in[49]                             |la_data_in[49]                             
+la_data_in[57]                             |la_data_in[57]                             
+la_data_in[59]                             |la_data_in[59]                             
+la_data_in[60]                             |la_data_in[60]                             
+la_oenb[53]                                |la_oenb[53]                                
+la_oenb[55]                                |la_oenb[55]                                
+la_oenb[54]                                |la_oenb[54]                                
+la_data_in[52]                             |la_data_in[52]                             
+la_data_in[53]                             |la_data_in[53]                             
+la_data_in[55]                             |la_data_in[55]                             
+la_data_in[54]                             |la_data_in[54]                             
+la_data_in[56]                             |la_data_in[56]                             
+la_oenb[51]                                |la_oenb[51]                                
+la_oenb[52]                                |la_oenb[52]                                
+la_oenb[49]                                |la_oenb[49]                                
+la_oenb[50]                                |la_oenb[50]                                
+la_oenb[48]                                |la_oenb[48]                                
+la_oenb[56]                                |la_oenb[56]                                
+la_data_in[51]                             |la_data_in[51]                             
+la_data_in[58]                             |la_data_in[58]                             
+la_data_in[65]                             |la_data_in[65]                             
+la_data_in[61]                             |la_data_in[61]                             
+la_data_in[62]                             |la_data_in[62]                             
+la_data_in[63]                             |la_data_in[63]                             
+la_oenb[65]                                |la_oenb[65]                                
+la_oenb[59]                                |la_oenb[59]                                
+la_oenb[57]                                |la_oenb[57]                                
+la_oenb[61]                                |la_oenb[61]                                
+la_oenb[63]                                |la_oenb[63]                                
+la_oenb[62]                                |la_oenb[62]                                
+la_oenb[60]                                |la_oenb[60]                                
+vssd1                                      |vssd1                                      
+vccd1                                      |vccd1                                      
+io_in[0]                                   |io_in[0]                                   
+io_in[10]                                  |io_in[10]                                  
+io_in[11]                                  |io_in[11]                                  
+io_in[12]                                  |io_in[12]                                  
+io_in[13]                                  |io_in[13]                                  
+io_in[14]                                  |io_in[14]                                  
+io_in[15]                                  |io_in[15]                                  
+io_in[1]                                   |io_in[1]                                   
+io_in[2]                                   |io_in[2]                                   
+io_in[3]                                   |io_in[3]                                   
+io_in[4]                                   |io_in[4]                                   
+io_in[5]                                   |io_in[5]                                   
+io_in[6]                                   |io_in[6]                                   
+io_in[7]                                   |io_in[7]                                   
+io_in[8]                                   |io_in[8]                                   
+io_in[9]                                   |io_in[9]                                   
+la_data_in[0]                              |la_data_in[0]                              
+la_data_in[100]                            |la_data_in[100]                            
+la_data_in[101]                            |la_data_in[101]                            
+la_data_in[102]                            |la_data_in[102]                            
+la_data_in[103]                            |la_data_in[103]                            
+la_data_in[104]                            |la_data_in[104]                            
+la_data_in[105]                            |la_data_in[105]                            
+la_data_in[106]                            |la_data_in[106]                            
+la_data_in[107]                            |la_data_in[107]                            
+la_data_in[108]                            |la_data_in[108]                            
+la_data_in[109]                            |la_data_in[109]                            
+la_data_in[10]                             |la_data_in[10]                             
+la_data_in[110]                            |la_data_in[110]                            
+la_data_in[111]                            |la_data_in[111]                            
+la_data_in[112]                            |la_data_in[112]                            
+la_data_in[113]                            |la_data_in[113]                            
+la_data_in[114]                            |la_data_in[114]                            
+la_data_in[115]                            |la_data_in[115]                            
+la_data_in[116]                            |la_data_in[116]                            
+la_data_in[117]                            |la_data_in[117]                            
+la_data_in[118]                            |la_data_in[118]                            
+la_data_in[119]                            |la_data_in[119]                            
+la_data_in[11]                             |la_data_in[11]                             
+la_data_in[120]                            |la_data_in[120]                            
+la_data_in[121]                            |la_data_in[121]                            
+la_data_in[122]                            |la_data_in[122]                            
+la_data_in[123]                            |la_data_in[123]                            
+la_data_in[124]                            |la_data_in[124]                            
+la_data_in[125]                            |la_data_in[125]                            
+la_data_in[126]                            |la_data_in[126]                            
+la_data_in[127]                            |la_data_in[127]                            
+la_data_in[12]                             |la_data_in[12]                             
+la_data_in[13]                             |la_data_in[13]                             
+la_data_in[14]                             |la_data_in[14]                             
+la_data_in[15]                             |la_data_in[15]                             
+la_data_in[16]                             |la_data_in[16]                             
+la_data_in[17]                             |la_data_in[17]                             
+la_data_in[18]                             |la_data_in[18]                             
+la_data_in[19]                             |la_data_in[19]                             
+la_data_in[1]                              |la_data_in[1]                              
+la_data_in[20]                             |la_data_in[20]                             
+la_data_in[21]                             |la_data_in[21]                             
+la_data_in[22]                             |la_data_in[22]                             
+la_data_in[23]                             |la_data_in[23]                             
+la_data_in[24]                             |la_data_in[24]                             
+la_data_in[25]                             |la_data_in[25]                             
+la_data_in[26]                             |la_data_in[26]                             
+la_data_in[27]                             |la_data_in[27]                             
+la_data_in[28]                             |la_data_in[28]                             
+la_data_in[29]                             |la_data_in[29]                             
+la_data_in[2]                              |la_data_in[2]                              
+la_data_in[30]                             |la_data_in[30]                             
+la_data_in[31]                             |la_data_in[31]                             
+la_data_in[32]                             |la_data_in[32]                             
+la_data_in[33]                             |la_data_in[33]                             
+la_data_in[34]                             |la_data_in[34]                             
+la_data_in[35]                             |la_data_in[35]                             
+la_data_in[36]                             |la_data_in[36]                             
+la_data_in[37]                             |la_data_in[37]                             
+la_data_in[38]                             |la_data_in[38]                             
+la_data_in[39]                             |la_data_in[39]                             
+la_data_in[3]                              |la_data_in[3]                              
+la_data_in[40]                             |la_data_in[40]                             
+la_data_in[41]                             |la_data_in[41]                             
+la_data_in[42]                             |la_data_in[42]                             
+la_data_in[43]                             |la_data_in[43]                             
+la_data_in[44]                             |la_data_in[44]                             
+la_data_in[45]                             |la_data_in[45]                             
+la_data_in[46]                             |la_data_in[46]                             
+la_data_in[47]                             |la_data_in[47]                             
+la_data_in[4]                              |la_data_in[4]                              
+la_data_in[5]                              |la_data_in[5]                              
+la_data_in[66]                             |la_data_in[66]                             
+la_data_in[67]                             |la_data_in[67]                             
+la_data_in[68]                             |la_data_in[68]                             
+la_data_in[69]                             |la_data_in[69]                             
+la_data_in[6]                              |la_data_in[6]                              
+la_data_in[70]                             |la_data_in[70]                             
+la_data_in[71]                             |la_data_in[71]                             
+la_data_in[72]                             |la_data_in[72]                             
+la_data_in[73]                             |la_data_in[73]                             
+la_data_in[74]                             |la_data_in[74]                             
+la_data_in[75]                             |la_data_in[75]                             
+la_data_in[76]                             |la_data_in[76]                             
+la_data_in[77]                             |la_data_in[77]                             
+la_data_in[78]                             |la_data_in[78]                             
+la_data_in[79]                             |la_data_in[79]                             
+la_data_in[7]                              |la_data_in[7]                              
+la_data_in[80]                             |la_data_in[80]                             
+la_data_in[81]                             |la_data_in[81]                             
+la_data_in[82]                             |la_data_in[82]                             
+la_data_in[83]                             |la_data_in[83]                             
+la_data_in[84]                             |la_data_in[84]                             
+la_data_in[85]                             |la_data_in[85]                             
+la_data_in[86]                             |la_data_in[86]                             
+la_data_in[87]                             |la_data_in[87]                             
+la_data_in[88]                             |la_data_in[88]                             
+la_data_in[89]                             |la_data_in[89]                             
+la_data_in[8]                              |la_data_in[8]                              
+la_data_in[90]                             |la_data_in[90]                             
+la_data_in[91]                             |la_data_in[91]                             
+la_data_in[92]                             |la_data_in[92]                             
+la_data_in[93]                             |la_data_in[93]                             
+la_data_in[94]                             |la_data_in[94]                             
+la_data_in[95]                             |la_data_in[95]                             
+la_data_in[96]                             |la_data_in[96]                             
+la_data_in[97]                             |la_data_in[97]                             
+la_data_in[98]                             |la_data_in[98]                             
+la_data_in[99]                             |la_data_in[99]                             
+la_data_in[9]                              |la_data_in[9]                              
+la_oenb[0]                                 |la_oenb[0]                                 
+la_oenb[100]                               |la_oenb[100]                               
+la_oenb[101]                               |la_oenb[101]                               
+la_oenb[102]                               |la_oenb[102]                               
+la_oenb[103]                               |la_oenb[103]                               
+la_oenb[104]                               |la_oenb[104]                               
+la_oenb[105]                               |la_oenb[105]                               
+la_oenb[106]                               |la_oenb[106]                               
+la_oenb[107]                               |la_oenb[107]                               
+la_oenb[108]                               |la_oenb[108]                               
+la_oenb[109]                               |la_oenb[109]                               
+la_oenb[10]                                |la_oenb[10]                                
+la_oenb[110]                               |la_oenb[110]                               
+la_oenb[111]                               |la_oenb[111]                               
+la_oenb[112]                               |la_oenb[112]                               
+la_oenb[113]                               |la_oenb[113]                               
+la_oenb[114]                               |la_oenb[114]                               
+la_oenb[115]                               |la_oenb[115]                               
+la_oenb[116]                               |la_oenb[116]                               
+la_oenb[117]                               |la_oenb[117]                               
+la_oenb[118]                               |la_oenb[118]                               
+la_oenb[119]                               |la_oenb[119]                               
+la_oenb[11]                                |la_oenb[11]                                
+la_oenb[120]                               |la_oenb[120]                               
+la_oenb[121]                               |la_oenb[121]                               
+la_oenb[122]                               |la_oenb[122]                               
+la_oenb[123]                               |la_oenb[123]                               
+la_oenb[124]                               |la_oenb[124]                               
+la_oenb[125]                               |la_oenb[125]                               
+la_oenb[126]                               |la_oenb[126]                               
+la_oenb[127]                               |la_oenb[127]                               
+la_oenb[12]                                |la_oenb[12]                                
+la_oenb[13]                                |la_oenb[13]                                
+la_oenb[14]                                |la_oenb[14]                                
+la_oenb[15]                                |la_oenb[15]                                
+la_oenb[16]                                |la_oenb[16]                                
+la_oenb[17]                                |la_oenb[17]                                
+la_oenb[18]                                |la_oenb[18]                                
+la_oenb[19]                                |la_oenb[19]                                
+la_oenb[1]                                 |la_oenb[1]                                 
+la_oenb[20]                                |la_oenb[20]                                
+la_oenb[21]                                |la_oenb[21]                                
+la_oenb[22]                                |la_oenb[22]                                
+la_oenb[23]                                |la_oenb[23]                                
+la_oenb[24]                                |la_oenb[24]                                
+la_oenb[25]                                |la_oenb[25]                                
+la_oenb[26]                                |la_oenb[26]                                
+la_oenb[27]                                |la_oenb[27]                                
+la_oenb[28]                                |la_oenb[28]                                
+la_oenb[29]                                |la_oenb[29]                                
+la_oenb[2]                                 |la_oenb[2]                                 
+la_oenb[30]                                |la_oenb[30]                                
+la_oenb[31]                                |la_oenb[31]                                
+la_oenb[32]                                |la_oenb[32]                                
+la_oenb[33]                                |la_oenb[33]                                
+la_oenb[34]                                |la_oenb[34]                                
+la_oenb[35]                                |la_oenb[35]                                
+la_oenb[36]                                |la_oenb[36]                                
+la_oenb[37]                                |la_oenb[37]                                
+la_oenb[38]                                |la_oenb[38]                                
+la_oenb[39]                                |la_oenb[39]                                
+la_oenb[3]                                 |la_oenb[3]                                 
+la_oenb[40]                                |la_oenb[40]                                
+la_oenb[41]                                |la_oenb[41]                                
+la_oenb[42]                                |la_oenb[42]                                
+la_oenb[43]                                |la_oenb[43]                                
+la_oenb[44]                                |la_oenb[44]                                
+la_oenb[45]                                |la_oenb[45]                                
+la_oenb[46]                                |la_oenb[46]                                
+la_oenb[47]                                |la_oenb[47]                                
+la_oenb[4]                                 |la_oenb[4]                                 
+la_oenb[5]                                 |la_oenb[5]                                 
+la_oenb[66]                                |la_oenb[66]                                
+la_oenb[67]                                |la_oenb[67]                                
+la_oenb[68]                                |la_oenb[68]                                
+la_oenb[69]                                |la_oenb[69]                                
+la_oenb[6]                                 |la_oenb[6]                                 
+la_oenb[70]                                |la_oenb[70]                                
+la_oenb[71]                                |la_oenb[71]                                
+la_oenb[72]                                |la_oenb[72]                                
+la_oenb[73]                                |la_oenb[73]                                
+la_oenb[74]                                |la_oenb[74]                                
+la_oenb[75]                                |la_oenb[75]                                
+la_oenb[76]                                |la_oenb[76]                                
+la_oenb[77]                                |la_oenb[77]                                
+la_oenb[78]                                |la_oenb[78]                                
+la_oenb[79]                                |la_oenb[79]                                
+la_oenb[7]                                 |la_oenb[7]                                 
+la_oenb[80]                                |la_oenb[80]                                
+la_oenb[81]                                |la_oenb[81]                                
+la_oenb[82]                                |la_oenb[82]                                
+la_oenb[83]                                |la_oenb[83]                                
+la_oenb[84]                                |la_oenb[84]                                
+la_oenb[85]                                |la_oenb[85]                                
+la_oenb[86]                                |la_oenb[86]                                
+la_oenb[87]                                |la_oenb[87]                                
+la_oenb[88]                                |la_oenb[88]                                
+la_oenb[89]                                |la_oenb[89]                                
+la_oenb[8]                                 |la_oenb[8]                                 
+la_oenb[90]                                |la_oenb[90]                                
+la_oenb[91]                                |la_oenb[91]                                
+la_oenb[92]                                |la_oenb[92]                                
+la_oenb[93]                                |la_oenb[93]                                
+la_oenb[94]                                |la_oenb[94]                                
+la_oenb[95]                                |la_oenb[95]                                
+la_oenb[96]                                |la_oenb[96]                                
+la_oenb[97]                                |la_oenb[97]                                
+la_oenb[98]                                |la_oenb[98]                                
+la_oenb[99]                                |la_oenb[99]                                
+la_oenb[9]                                 |la_oenb[9]                                 
+wbs_adr_i[0]                               |wbs_adr_i[0]                               
+wbs_adr_i[10]                              |wbs_adr_i[10]                              
+wbs_adr_i[11]                              |wbs_adr_i[11]                              
+wbs_adr_i[12]                              |wbs_adr_i[12]                              
+wbs_adr_i[13]                              |wbs_adr_i[13]                              
+wbs_adr_i[14]                              |wbs_adr_i[14]                              
+wbs_adr_i[15]                              |wbs_adr_i[15]                              
+wbs_adr_i[16]                              |wbs_adr_i[16]                              
+wbs_adr_i[17]                              |wbs_adr_i[17]                              
+wbs_adr_i[18]                              |wbs_adr_i[18]                              
+wbs_adr_i[19]                              |wbs_adr_i[19]                              
+wbs_adr_i[1]                               |wbs_adr_i[1]                               
+wbs_adr_i[20]                              |wbs_adr_i[20]                              
+wbs_adr_i[21]                              |wbs_adr_i[21]                              
+wbs_adr_i[22]                              |wbs_adr_i[22]                              
+wbs_adr_i[23]                              |wbs_adr_i[23]                              
+wbs_adr_i[24]                              |wbs_adr_i[24]                              
+wbs_adr_i[25]                              |wbs_adr_i[25]                              
+wbs_adr_i[26]                              |wbs_adr_i[26]                              
+wbs_adr_i[27]                              |wbs_adr_i[27]                              
+wbs_adr_i[28]                              |wbs_adr_i[28]                              
+wbs_adr_i[29]                              |wbs_adr_i[29]                              
+wbs_adr_i[2]                               |wbs_adr_i[2]                               
+wbs_adr_i[30]                              |wbs_adr_i[30]                              
+wbs_adr_i[31]                              |wbs_adr_i[31]                              
+wbs_adr_i[3]                               |wbs_adr_i[3]                               
+wbs_adr_i[4]                               |wbs_adr_i[4]                               
+wbs_adr_i[5]                               |wbs_adr_i[5]                               
+wbs_adr_i[6]                               |wbs_adr_i[6]                               
+wbs_adr_i[7]                               |wbs_adr_i[7]                               
+wbs_adr_i[8]                               |wbs_adr_i[8]                               
+wbs_adr_i[9]                               |wbs_adr_i[9]                               
+wbs_dat_i[16]                              |wbs_dat_i[16]                              
+wbs_dat_i[17]                              |wbs_dat_i[17]                              
+wbs_dat_i[18]                              |wbs_dat_i[18]                              
+wbs_dat_i[19]                              |wbs_dat_i[19]                              
+wbs_dat_i[20]                              |wbs_dat_i[20]                              
+wbs_dat_i[21]                              |wbs_dat_i[21]                              
+wbs_dat_i[22]                              |wbs_dat_i[22]                              
+wbs_dat_i[23]                              |wbs_dat_i[23]                              
+wbs_dat_i[24]                              |wbs_dat_i[24]                              
+wbs_dat_i[25]                              |wbs_dat_i[25]                              
+wbs_dat_i[26]                              |wbs_dat_i[26]                              
+wbs_dat_i[27]                              |wbs_dat_i[27]                              
+wbs_dat_i[28]                              |wbs_dat_i[28]                              
+wbs_dat_i[29]                              |wbs_dat_i[29]                              
+wbs_dat_i[30]                              |wbs_dat_i[30]                              
+wbs_dat_i[31]                              |wbs_dat_i[31]                              
+wbs_sel_i[2]                               |wbs_sel_i[2]                               
+wbs_sel_i[3]                               |wbs_sel_i[3]                               
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes user_proj_example and user_proj_example are equivalent.
+
+Final result: Circuits match uniquely.
+.
diff --git a/signoff/user_proj_example/openlane-signoff/netgen-lvs.log b/signoff/user_proj_example/openlane-signoff/netgen-lvs.log
new file mode 100644
index 000000000..0eedc850c
--- /dev/null
+++ b/signoff/user_proj_example/openlane-signoff/netgen-lvs.log
@@ -0,0 +1,1620 @@
+Netgen 1.5.255 compiled on Thu Jul 13 06:58:56 UTC 2023
+Warning: netgen command 'format' use fully-qualified name '::netgen::format'
+Warning: netgen command 'global' use fully-qualified name '::netgen::global'
+Reading SPICE netlist file '/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice'...
+Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
+Creating placeholder cell definition.
+Call to undefined subcircuit sky130_fd_pr__nfet_01v8
+Creating placeholder cell definition.
+Reading SPICE netlist file '/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice'...
+Reading SPICE netlist file '/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'...
+Reading SPICE netlist file '/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice'...
+Call to undefined subcircuit sky130_fd_sc_hd__nand2_2
+Creating placeholder cell definition.
+Call to undefined subcircuit sky130_fd_sc_hd__nor2_2
+Creating placeholder cell definition.
+Reading SPICE netlist file '/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fakediode_2.spice'...
+Reading SPICE netlist file '/home/karim/work/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice'...
+Generating JSON file result
+Reading netlist file /home/karim/work/caravel_user_project/openlane/user_proj_example/runs/23_08_27_13_11/45-magic-spiceextraction/user_proj_example.spice
+Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
+Creating placeholder cell definition.
+Call to undefined subcircuit sky130_fd_pr__nfet_01v8
+Creating placeholder cell definition.
+Reading netlist file /home/karim/work/caravel_user_project/openlane/user_proj_example/runs/23_08_27_13_11/34-openroad-fillinsertion/user_proj_example.pnl.v
+Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
+Note:  Implicit pin HI in instance _309__145 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _310__146 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _311__147 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _312__148 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _313__149 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _314__150 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _315__151 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _316__152 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _317__153 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _318__154 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _319__155 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _320__156 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _321__157 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _322__158 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _323__159 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _324__160 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _325__161 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _326__162 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _327__163 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _328__164 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _329__165 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _330__166 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _331__167 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _332__168 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _333__169 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _334__170 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _335__171 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _336__172 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _337__173 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _338__174 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _339__175 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _340__176 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _341__177 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _342__178 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _343__179 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _344__180 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _345__181 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _346__182 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _347__183 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _348__184 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _349__185 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _350__186 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _351__187 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _352__188 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _353__189 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _354__190 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _355__191 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _356__192 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _357__193 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _358__194 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _359__195 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _360__196 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _361__197 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _362__198 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _363__199 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _364__200 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _365__201 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _366__202 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _367__203 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _368__204 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _369__205 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _370__206 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _371__207 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _372__208 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _373__209 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _374__210 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _375__211 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _376__212 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _377__213 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _378__214 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _379__215 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _380__216 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _381__217 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _382__218 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _383__219 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _384__220 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _385__221 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _386__222 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _387__223 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _388__224 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _389__225 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _390__226 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _391__227 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _392__228 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _393__229 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _394__230 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _395__231 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _396__232 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _397__233 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _398__234 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _399__235 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _415__236 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _416__237 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _417__238 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _434__239 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _435__240 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _436__241 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _437__242 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _438__243 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _439__244 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _440__245 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _441__246 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _442__247 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _443__248 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _444__249 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _445__250 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _446__251 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _447__252 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _448__253 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _449__254 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _450__255 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _451__256 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _452__257 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _453__258 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _454__259 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _455__260 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _456__261 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _457__262 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _458__263 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _459__264 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _460__265 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _461__266 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _462__267 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _463__268 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _464__269 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _465__270 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _466__271 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _467__272 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _468__273 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _469__274 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance _470__275 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__470__A_276 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__469__A_277 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__468__A_278 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__467__A_279 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__466__A_280 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__465__A_281 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__464__A_282 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__463__A_283 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__462__A_284 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__461__A_285 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__460__A_286 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__459__A_287 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__458__A_288 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__457__A_289 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__456__A_290 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__455__A_291 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__454__A_292 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__453__A_293 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__452__A_294 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__451__A_295 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__450__A_296 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__449__A_297 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__448__A_298 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__447__A_299 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__446__A_300 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__445__A_301 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__444__A_302 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__443__A_303 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__442__A_304 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__441__A_305 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__440__A_306 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__439__A_307 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__438__A_308 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__437__A_309 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__436__A_310 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__435__A_311 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__434__A_312 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__417__A_313 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__416__A_314 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__415__A_315 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__399__A_316 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__398__A_317 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__397__A_318 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__396__A_319 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__395__A_320 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__394__A_321 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__393__A_322 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__392__A_323 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__391__A_324 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__390__A_325 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__389__A_326 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__388__A_327 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__387__A_328 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__386__A_329 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__385__A_330 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__384__A_331 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__383__A_332 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__382__A_333 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__381__A_334 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__380__A_335 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__379__A_336 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__378__A_337 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__377__A_338 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__376__A_339 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__375__A_340 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__374__A_341 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__373__A_342 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__372__A_343 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__371__A_344 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__370__A_345 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__369__A_346 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__368__A_347 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__367__A_348 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__366__A_349 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__365__A_350 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__364__A_351 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__363__A_352 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__362__A_353 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__361__A_354 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__360__A_355 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__359__A_356 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__358__A_357 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__357__A_358 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__356__A_359 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__355__A_360 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__354__A_361 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__353__A_362 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__352__A_363 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__351__A_364 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__350__A_365 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__349__A_366 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__348__A_367 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__347__A_368 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__346__A_369 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__345__A_370 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__344__A_371 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__343__A_372 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__342__A_373 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__341__A_374 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__340__A_375 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__339__A_376 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__338__A_377 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__337__A_378 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__336__A_379 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__335__A_380 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__334__A_381 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__333__A_382 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__332__A_383 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__331__A_384 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__330__A_385 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__329__A_386 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__328__A_387 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__327__A_388 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__326__A_389 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__325__A_390 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__324__A_391 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__323__A_392 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__322__A_393 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__321__A_394 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__320__A_395 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__319__A_396 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__318__A_397 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__317__A_398 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__316__A_399 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__315__A_400 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__314__A_401 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__313__A_402 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__312__A_403 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__311__A_404 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__310__A_405 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+Note:  Implicit pin HI in instance ANTENNA__309__A_406 of sky130_fd_sc_hd__conb_1 in cell user_proj_example
+
+Reading setup file /home/karim/work/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
+
+Model sky130_fd_pr__res_generic_po pin end_a == end_b
+No property mult found for device sky130_fd_pr__res_generic_po
+Model sky130_fd_pr__res_generic_po pin end_a == end_b
+No property mult found for device sky130_fd_pr__res_generic_po
+Model sky130_fd_pr__nfet_01v8 pin 1 == 3
+No property mult found for device sky130_fd_pr__nfet_01v8
+No property sa found for device sky130_fd_pr__nfet_01v8
+No property sb found for device sky130_fd_pr__nfet_01v8
+No property sd found for device sky130_fd_pr__nfet_01v8
+No property nf found for device sky130_fd_pr__nfet_01v8
+No property nrd found for device sky130_fd_pr__nfet_01v8
+No property nrs found for device sky130_fd_pr__nfet_01v8
+No property area found for device sky130_fd_pr__nfet_01v8
+No property perim found for device sky130_fd_pr__nfet_01v8
+No property topography found for device sky130_fd_pr__nfet_01v8
+Model sky130_fd_pr__nfet_01v8 pin 1 == 3
+No property mult found for device sky130_fd_pr__nfet_01v8
+No property sa found for device sky130_fd_pr__nfet_01v8
+No property sb found for device sky130_fd_pr__nfet_01v8
+No property sd found for device sky130_fd_pr__nfet_01v8
+No property nf found for device sky130_fd_pr__nfet_01v8
+No property nrd found for device sky130_fd_pr__nfet_01v8
+No property nrs found for device sky130_fd_pr__nfet_01v8
+No property area found for device sky130_fd_pr__nfet_01v8
+No property perim found for device sky130_fd_pr__nfet_01v8
+No property topography found for device sky130_fd_pr__nfet_01v8
+Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3
+No property mult found for device sky130_fd_pr__pfet_01v8_hvt
+No property sa found for device sky130_fd_pr__pfet_01v8_hvt
+No property sb found for device sky130_fd_pr__pfet_01v8_hvt
+No property sd found for device sky130_fd_pr__pfet_01v8_hvt
+No property nf found for device sky130_fd_pr__pfet_01v8_hvt
+No property nrd found for device sky130_fd_pr__pfet_01v8_hvt
+No property nrs found for device sky130_fd_pr__pfet_01v8_hvt
+No property area found for device sky130_fd_pr__pfet_01v8_hvt
+No property perim found for device sky130_fd_pr__pfet_01v8_hvt
+No property topography found for device sky130_fd_pr__pfet_01v8_hvt
+Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3
+No property mult found for device sky130_fd_pr__pfet_01v8_hvt
+No property sa found for device sky130_fd_pr__pfet_01v8_hvt
+No property sb found for device sky130_fd_pr__pfet_01v8_hvt
+No property sd found for device sky130_fd_pr__pfet_01v8_hvt
+No property nf found for device sky130_fd_pr__pfet_01v8_hvt
+No property nrd found for device sky130_fd_pr__pfet_01v8_hvt
+No property nrs found for device sky130_fd_pr__pfet_01v8_hvt
+No property area found for device sky130_fd_pr__pfet_01v8_hvt
+No property perim found for device sky130_fd_pr__pfet_01v8_hvt
+No property topography found for device sky130_fd_pr__pfet_01v8_hvt
+No property value found for device sky130_fd_pr__diode_pw2nd_05v5
+No property mult found for device sky130_fd_pr__diode_pw2nd_05v5
+No property perim found for device sky130_fd_pr__diode_pw2nd_05v5
+No property value found for device sky130_fd_pr__diode_pw2nd_05v5
+No property mult found for device sky130_fd_pr__diode_pw2nd_05v5
+No property perim found for device sky130_fd_pr__diode_pw2nd_05v5
+Comparison output logged to file /home/karim/work/caravel_user_project/openlane/user_proj_example/runs/23_08_27_13_11/47-netgen-lvs/lvs.rpt
+Logging to file "/home/karim/work/caravel_user_project/openlane/user_proj_example/runs/23_08_27_13_11/47-netgen-lvs/lvs.rpt" enabled
+Circuit sky130_fd_pr__pfet_01v8_hvt contains no devices.
+Circuit sky130_fd_pr__nfet_01v8 contains no devices.
+
+Contents of circuit 1:  Circuit: 'sky130_ef_sc_hd__decap_12'
+Circuit sky130_ef_sc_hd__decap_12 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+Contents of circuit 2:  Circuit: 'sky130_ef_sc_hd__decap_12'
+Circuit sky130_ef_sc_hd__decap_12 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 4 nets,    Circuit 2 contains 4 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_6'
+Circuit sky130_fd_sc_hd__decap_6 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_6'
+Circuit sky130_fd_sc_hd__decap_6 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 4 nets,    Circuit 2 contains 4 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_8'
+Circuit sky130_fd_sc_hd__decap_8 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_8'
+Circuit sky130_fd_sc_hd__decap_8 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 4 nets,    Circuit 2 contains 4 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_3'
+Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_3'
+Circuit sky130_fd_sc_hd__decap_3 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 4 nets,    Circuit 2 contains 4 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__diode_2'
+Circuit sky130_fd_sc_hd__diode_2 contains 1 device instances.
+  Class: sky130_fd_pr__diode_pw2nd_05v5 instances:   1
+Circuit contains 2 nets, and 3 disconnected pins.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__diode_2'
+Circuit sky130_fd_sc_hd__diode_2 contains 1 device instances.
+  Class: sky130_fd_pr__diode_pw2nd_05v5 instances:   1
+Circuit contains 2 nets, and 3 disconnected pins.
+
+Circuit 1 contains 1 devices, Circuit 2 contains 1 devices.
+Circuit 1 contains 2 nets,    Circuit 2 contains 2 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_1'
+Circuit sky130_fd_sc_hd__buf_1 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_1'
+Circuit sky130_fd_sc_hd__buf_1 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_2'
+Circuit sky130_fd_sc_hd__buf_2 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_2'
+Circuit sky130_fd_sc_hd__buf_2 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_2'
+Circuit sky130_fd_sc_hd__buf_2 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_2'
+Circuit sky130_fd_sc_hd__buf_2 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfxtp_2'
+Circuit sky130_fd_sc_hd__dfxtp_2 contains 26 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  13
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  13
+Circuit contains 18 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfxtp_2'
+Circuit sky130_fd_sc_hd__dfxtp_2 contains 26 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  13
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  13
+Circuit contains 18 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfxtp_2'
+Circuit sky130_fd_sc_hd__dfxtp_2 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 18 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfxtp_2'
+Circuit sky130_fd_sc_hd__dfxtp_2 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 18 nets.
+
+Circuit 1 contains 24 devices, Circuit 2 contains 24 devices.
+Circuit 1 contains 18 nets,    Circuit 2 contains 18 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__conb_1'
+Circuit sky130_fd_sc_hd__conb_1 contains 2 device instances.
+  Class: sky130_fd_pr__res_generic_po instances:   2
+Circuit contains 4 nets, and 2 disconnected pins.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__conb_1'
+Circuit sky130_fd_sc_hd__conb_1 contains 2 device instances.
+  Class: sky130_fd_pr__res_generic_po instances:   2
+Circuit contains 4 nets, and 2 disconnected pins.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 4 nets,    Circuit 2 contains 4 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__decap_4'
+Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__decap_4'
+Circuit sky130_fd_sc_hd__decap_4 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 4 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 4 nets,    Circuit 2 contains 4 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dlygate4sd3_1'
+Circuit sky130_fd_sc_hd__dlygate4sd3_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 9 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dlygate4sd3_1'
+Circuit sky130_fd_sc_hd__dlygate4sd3_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 9 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 9 nets,    Circuit 2 contains 9 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfxtp_4'
+Circuit sky130_fd_sc_hd__dfxtp_4 contains 30 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  15
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  15
+Circuit contains 18 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfxtp_4'
+Circuit sky130_fd_sc_hd__dfxtp_4 contains 30 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  15
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  15
+Circuit contains 18 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfxtp_4'
+Circuit sky130_fd_sc_hd__dfxtp_4 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 18 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfxtp_4'
+Circuit sky130_fd_sc_hd__dfxtp_4 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 18 nets.
+
+Circuit 1 contains 24 devices, Circuit 2 contains 24 devices.
+Circuit 1 contains 18 nets,    Circuit 2 contains 18 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3_1'
+Circuit sky130_fd_sc_hd__and3_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3_1'
+Circuit sky130_fd_sc_hd__and3_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_12'
+Circuit sky130_fd_sc_hd__buf_12 contains 32 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  16
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  16
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_12'
+Circuit sky130_fd_sc_hd__buf_12 contains 32 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  16
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  16
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_12'
+Circuit sky130_fd_sc_hd__buf_12 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_12'
+Circuit sky130_fd_sc_hd__buf_12 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'
+Circuit sky130_fd_sc_hd__clkbuf_16 contains 40 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  20
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  20
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'
+Circuit sky130_fd_sc_hd__clkbuf_16 contains 40 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  20
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  20
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'
+Circuit sky130_fd_sc_hd__clkbuf_16 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_16'
+Circuit sky130_fd_sc_hd__clkbuf_16 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and2_1'
+Circuit sky130_fd_sc_hd__and2_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 9 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and2_1'
+Circuit sky130_fd_sc_hd__and2_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 9 nets.
+
+Circuit 1 contains 6 devices, Circuit 2 contains 6 devices.
+Circuit 1 contains 9 nets,    Circuit 2 contains 9 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__mux2_1'
+Circuit sky130_fd_sc_hd__mux2_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 14 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__mux2_1'
+Circuit sky130_fd_sc_hd__mux2_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 14 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 14 nets,    Circuit 2 contains 14 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a31o_1'
+Circuit sky130_fd_sc_hd__a31o_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a31o_1'
+Circuit sky130_fd_sc_hd__a31o_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+
+Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
+Circuit 1 contains 13 nets,    Circuit 2 contains 13 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a32o_1'
+Circuit sky130_fd_sc_hd__a32o_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 15 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a32o_1'
+Circuit sky130_fd_sc_hd__a32o_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 15 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 15 nets,    Circuit 2 contains 15 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__inv_2'
+Circuit sky130_fd_sc_hd__inv_2 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 6 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__inv_2'
+Circuit sky130_fd_sc_hd__inv_2 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 6 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__inv_2'
+Circuit sky130_fd_sc_hd__inv_2 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 6 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__inv_2'
+Circuit sky130_fd_sc_hd__inv_2 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 6 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 6 nets,    Circuit 2 contains 6 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dfxtp_1'
+Circuit sky130_fd_sc_hd__dfxtp_1 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 18 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dfxtp_1'
+Circuit sky130_fd_sc_hd__dfxtp_1 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 18 nets.
+
+Circuit 1 contains 24 devices, Circuit 2 contains 24 devices.
+Circuit 1 contains 18 nets,    Circuit 2 contains 18 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__or2_1'
+Circuit sky130_fd_sc_hd__or2_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 9 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__or2_1'
+Circuit sky130_fd_sc_hd__or2_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 9 nets.
+
+Circuit 1 contains 6 devices, Circuit 2 contains 6 devices.
+Circuit 1 contains 9 nets,    Circuit 2 contains 9 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_8'
+Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  10
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  10
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_8'
+Circuit sky130_fd_sc_hd__clkbuf_8 contains 20 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  10
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  10
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_8'
+Circuit sky130_fd_sc_hd__clkbuf_8 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_8'
+Circuit sky130_fd_sc_hd__clkbuf_8 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand4_1'
+Circuit sky130_fd_sc_hd__nand4_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 12 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand4_1'
+Circuit sky130_fd_sc_hd__nand4_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 12 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4_2'
+Circuit sky130_fd_sc_hd__and4_2 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 13 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4_2'
+Circuit sky130_fd_sc_hd__and4_2 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 13 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4_2'
+Circuit sky130_fd_sc_hd__and4_2 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4_2'
+Circuit sky130_fd_sc_hd__and4_2 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+
+Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
+Circuit 1 contains 13 nets,    Circuit 2 contains 13 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4b_2'
+Circuit sky130_fd_sc_hd__and4b_2 contains 14 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   7
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   7
+Circuit contains 14 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4b_2'
+Circuit sky130_fd_sc_hd__and4b_2 contains 14 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   7
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   7
+Circuit contains 14 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and4b_2'
+Circuit sky130_fd_sc_hd__and4b_2 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 14 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and4b_2'
+Circuit sky130_fd_sc_hd__and4b_2 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 14 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 14 nets,    Circuit 2 contains 14 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21a_1'
+Circuit sky130_fd_sc_hd__o21a_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21a_1'
+Circuit sky130_fd_sc_hd__o21a_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o2111a_1'
+Circuit sky130_fd_sc_hd__o2111a_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 15 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o2111a_1'
+Circuit sky130_fd_sc_hd__o2111a_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 15 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 15 nets,    Circuit 2 contains 15 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3b_1'
+Circuit sky130_fd_sc_hd__and3b_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 12 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3b_1'
+Circuit sky130_fd_sc_hd__and3b_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 12 nets.
+
+Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
+Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o211a_1'
+Circuit sky130_fd_sc_hd__o211a_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o211a_1'
+Circuit sky130_fd_sc_hd__o211a_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+
+Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
+Circuit 1 contains 13 nets,    Circuit 2 contains 13 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3_2'
+Circuit sky130_fd_sc_hd__and3_2 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3_2'
+Circuit sky130_fd_sc_hd__and3_2 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 11 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and3_2'
+Circuit sky130_fd_sc_hd__and3_2 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and3_2'
+Circuit sky130_fd_sc_hd__and3_2 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand3_1'
+Circuit sky130_fd_sc_hd__nand3_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 10 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand3_1'
+Circuit sky130_fd_sc_hd__nand3_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 10 nets.
+
+Circuit 1 contains 6 devices, Circuit 2 contains 6 devices.
+Circuit 1 contains 10 nets,    Circuit 2 contains 10 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__xor2_1'
+Circuit sky130_fd_sc_hd__xor2_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__xor2_1'
+Circuit sky130_fd_sc_hd__xor2_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 11 nets.
+
+Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21o_1'
+Circuit sky130_fd_sc_hd__a21o_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21o_1'
+Circuit sky130_fd_sc_hd__a21o_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a22o_1'
+Circuit sky130_fd_sc_hd__a22o_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a22o_1'
+Circuit sky130_fd_sc_hd__a22o_1 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 13 nets.
+
+Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
+Circuit 1 contains 13 nets,    Circuit 2 contains 13 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21o_2'
+Circuit sky130_fd_sc_hd__a21o_2 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21o_2'
+Circuit sky130_fd_sc_hd__a21o_2 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 11 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a21o_2'
+Circuit sky130_fd_sc_hd__a21o_2 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a21o_2'
+Circuit sky130_fd_sc_hd__a21o_2 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 11 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2_1'
+Circuit sky130_fd_sc_hd__nand2_1 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 8 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2_1'
+Circuit sky130_fd_sc_hd__nand2_1 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 8 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 8 nets,    Circuit 2 contains 8 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a2bb2o_1'
+Circuit sky130_fd_sc_hd__a2bb2o_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 14 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a2bb2o_1'
+Circuit sky130_fd_sc_hd__a2bb2o_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 14 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 14 nets,    Circuit 2 contains 14 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_8'
+Circuit sky130_fd_sc_hd__buf_8 contains 22 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  11
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  11
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_8'
+Circuit sky130_fd_sc_hd__buf_8 contains 22 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  11
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  11
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_8'
+Circuit sky130_fd_sc_hd__buf_8 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_8'
+Circuit sky130_fd_sc_hd__buf_8 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__dlymetal6s2s_1'
+Circuit sky130_fd_sc_hd__dlymetal6s2s_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 11 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__dlymetal6s2s_1'
+Circuit sky130_fd_sc_hd__dlymetal6s2s_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 11 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 11 nets,    Circuit 2 contains 11 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_6'
+Circuit sky130_fd_sc_hd__buf_6 contains 16 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   8
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   8
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_6'
+Circuit sky130_fd_sc_hd__buf_6 contains 16 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   8
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   8
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_6'
+Circuit sky130_fd_sc_hd__buf_6 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_6'
+Circuit sky130_fd_sc_hd__buf_6 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_2'
+Circuit sky130_fd_sc_hd__clkbuf_2 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_2'
+Circuit sky130_fd_sc_hd__clkbuf_2 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_2'
+Circuit sky130_fd_sc_hd__clkbuf_2 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_2'
+Circuit sky130_fd_sc_hd__clkbuf_2 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_4'
+Circuit sky130_fd_sc_hd__clkbuf_4 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_4'
+Circuit sky130_fd_sc_hd__clkbuf_4 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__clkbuf_4'
+Circuit sky130_fd_sc_hd__clkbuf_4 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__clkbuf_4'
+Circuit sky130_fd_sc_hd__clkbuf_4 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_4'
+Circuit sky130_fd_sc_hd__buf_4 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_4'
+Circuit sky130_fd_sc_hd__buf_4 contains 10 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   5
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   5
+Circuit contains 7 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__buf_4'
+Circuit sky130_fd_sc_hd__buf_4 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__buf_4'
+Circuit sky130_fd_sc_hd__buf_4 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 7 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 7 nets,    Circuit 2 contains 7 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2_8'
+Circuit sky130_fd_sc_hd__nand2_8 contains 32 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  16
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  16
+Circuit contains 8 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2_8'
+Circuit sky130_fd_sc_hd__nand2_8 contains 32 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  16
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  16
+Circuit contains 8 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2_8'
+Circuit sky130_fd_sc_hd__nand2_8 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 8 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2_8'
+Circuit sky130_fd_sc_hd__nand2_8 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 8 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 8 nets,    Circuit 2 contains 8 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor2_4'
+Circuit sky130_fd_sc_hd__nor2_4 contains 16 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   8
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   8
+Circuit contains 8 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor2_4'
+Circuit sky130_fd_sc_hd__nor2_4 contains 16 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   8
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   8
+Circuit contains 8 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nor2_4'
+Circuit sky130_fd_sc_hd__nor2_4 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 8 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nor2_4'
+Circuit sky130_fd_sc_hd__nor2_4 contains 4 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   2
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   2
+Circuit contains 8 nets.
+
+Circuit 1 contains 4 devices, Circuit 2 contains 4 devices.
+Circuit 1 contains 8 nets,    Circuit 2 contains 8 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__and2b_1'
+Circuit sky130_fd_sc_hd__and2b_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 10 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__and2b_1'
+Circuit sky130_fd_sc_hd__and2b_1 contains 8 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   4
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   4
+Circuit contains 10 nets.
+
+Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
+Circuit 1 contains 10 nets,    Circuit 2 contains 10 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__inv_12'
+Circuit sky130_fd_sc_hd__inv_12 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 6 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__inv_12'
+Circuit sky130_fd_sc_hd__inv_12 contains 24 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:  12
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:  12
+Circuit contains 6 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__inv_12'
+Circuit sky130_fd_sc_hd__inv_12 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 6 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__inv_12'
+Circuit sky130_fd_sc_hd__inv_12 contains 2 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   1
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   1
+Circuit contains 6 nets.
+
+Circuit 1 contains 2 devices, Circuit 2 contains 2 devices.
+Circuit 1 contains 6 nets,    Circuit 2 contains 6 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21ai_2'
+Circuit sky130_fd_sc_hd__o21ai_2 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 10 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21ai_2'
+Circuit sky130_fd_sc_hd__o21ai_2 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 10 nets.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__o21ai_2'
+Circuit sky130_fd_sc_hd__o21ai_2 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 10 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__o21ai_2'
+Circuit sky130_fd_sc_hd__o21ai_2 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 10 nets.
+
+Circuit 1 contains 6 devices, Circuit 2 contains 6 devices.
+Circuit 1 contains 10 nets,    Circuit 2 contains 10 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__nand2b_1'
+Circuit sky130_fd_sc_hd__nand2b_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 9 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__nand2b_1'
+Circuit sky130_fd_sc_hd__nand2b_1 contains 6 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   3
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   3
+Circuit contains 9 nets.
+
+Circuit 1 contains 6 devices, Circuit 2 contains 6 devices.
+Circuit 1 contains 9 nets,    Circuit 2 contains 9 nets.
+
+
+Contents of circuit 1:  Circuit: 'sky130_fd_sc_hd__a221o_1'
+Circuit sky130_fd_sc_hd__a221o_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 15 nets.
+Contents of circuit 2:  Circuit: 'sky130_fd_sc_hd__a221o_1'
+Circuit sky130_fd_sc_hd__a221o_1 contains 12 device instances.
+  Class: sky130_fd_pr__nfet_01v8 instances:   6
+  Class: sky130_fd_pr__pfet_01v8_hvt instances:   6
+Circuit contains 15 nets.
+
+Circuit 1 contains 12 devices, Circuit 2 contains 12 devices.
+Circuit 1 contains 15 nets,    Circuit 2 contains 15 nets.
+
+
+Contents of circuit 1:  Circuit: 'user_proj_example'
+Circuit user_proj_example contains 347921 device instances.
+  Class: sky130_fd_sc_hd__a31o_1 instances:  12
+  Class: sky130_fd_sc_hd__a21o_1 instances:   9
+  Class: sky130_fd_sc_hd__a21o_2 instances:   1
+  Class: sky130_fd_sc_hd__clkbuf_16 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_1 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_2 instances:   5
+  Class: sky130_fd_sc_hd__dfxtp_4 instances:  15
+  Class: sky130_fd_sc_hd__nand4_1 instances:   1
+  Class: sky130_fd_sc_hd__buf_1 instances:  34
+  Class: sky130_fd_sc_hd__buf_2 instances: 138
+  Class: sky130_fd_sc_hd__buf_4 instances:   2
+  Class: sky130_fd_sc_hd__buf_6 instances:   6
+  Class: sky130_fd_sc_hd__buf_8 instances:  10
+  Class: sky130_fd_sc_hd__a2bb2o_1 instances:   1
+  Class: sky130_fd_sc_hd__and3b_1 instances:   1
+  Class: sky130_fd_sc_hd__xor2_1 instances:   1
+  Class: sky130_ef_sc_hd__decap_12 instances: 275419
+  Class: sky130_fd_sc_hd__and4_2 instances:   3
+  Class: sky130_fd_sc_hd__inv_2 instances:  20
+  Class: sky130_fd_sc_hd__clkbuf_2 instances:  13
+  Class: sky130_fd_sc_hd__clkbuf_4 instances:  15
+  Class: sky130_fd_sc_hd__clkbuf_8 instances:  11
+  Class: sky130_fd_sc_hd__nand3_1 instances:   4
+  Class: sky130_fd_sc_hd__and2b_1 instances:   1
+  Class: sky130_fd_sc_hd__conb_1 instances: 262
+  Class: sky130_fd_sc_hd__buf_12 instances:  83
+  Class: sky130_fd_sc_hd__and3_1 instances:   7
+  Class: sky130_fd_sc_hd__and3_2 instances:   2
+  Class: sky130_fd_sc_hd__decap_3 instances: 1862
+  Class: sky130_fd_sc_hd__decap_4 instances: 567
+  Class: sky130_fd_sc_hd__decap_6 instances: 67936
+  Class: sky130_fd_sc_hd__decap_8 instances: 484
+  Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 174
+  Class: sky130_fd_sc_hd__or2_1 instances:   4
+  Class: sky130_fd_sc_hd__nand2_1 instances:   7
+  Class: sky130_fd_sc_hd__nand2_8 instances:   2
+  Class: sky130_fd_sc_hd__mux2_1 instances:  17
+  Class: sky130_fd_sc_hd__and2_1 instances:  13
+  Class: sky130_fd_sc_hd__inv_12 instances:   1
+  Class: sky130_fd_sc_hd__o211a_1 instances:   1
+  Class: sky130_fd_sc_hd__nand2b_1 instances:   1
+  Class: sky130_fd_sc_hd__diode_2 instances: 719
+  Class: sky130_fd_sc_hd__a221o_1 instances:   1
+  Class: sky130_fd_sc_hd__o2111a_1 instances:   1
+  Class: sky130_fd_sc_hd__dlymetal6s2s_1 instances:   1
+  Class: sky130_fd_sc_hd__a32o_1 instances:  17
+  Class: sky130_fd_sc_hd__a22o_1 instances:   1
+  Class: sky130_fd_sc_hd__o21a_1 instances:   7
+  Class: sky130_fd_sc_hd__and4b_2 instances:   1
+  Class: sky130_fd_sc_hd__o21ai_2 instances:   1
+  Class: sky130_fd_sc_hd__nor2_4 instances:   1
+Circuit contains 1257 nets, and 286 disconnected pins.
+Contents of circuit 2:  Circuit: 'user_proj_example'
+Circuit user_proj_example contains 347921 device instances.
+  Class: sky130_fd_sc_hd__a31o_1 instances:  12
+  Class: sky130_fd_sc_hd__a21o_1 instances:   9
+  Class: sky130_fd_sc_hd__a21o_2 instances:   1
+  Class: sky130_fd_sc_hd__clkbuf_16 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_1 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_2 instances:   5
+  Class: sky130_fd_sc_hd__dfxtp_4 instances:  15
+  Class: sky130_fd_sc_hd__nand4_1 instances:   1
+  Class: sky130_fd_sc_hd__buf_1 instances:  34
+  Class: sky130_fd_sc_hd__buf_2 instances: 138
+  Class: sky130_fd_sc_hd__buf_4 instances:   2
+  Class: sky130_fd_sc_hd__buf_6 instances:   6
+  Class: sky130_fd_sc_hd__buf_8 instances:  10
+  Class: sky130_fd_sc_hd__a2bb2o_1 instances:   1
+  Class: sky130_fd_sc_hd__and3b_1 instances:   1
+  Class: sky130_fd_sc_hd__xor2_1 instances:   1
+  Class: sky130_ef_sc_hd__decap_12 instances: 275419
+  Class: sky130_fd_sc_hd__and4_2 instances:   3
+  Class: sky130_fd_sc_hd__inv_2 instances:  20
+  Class: sky130_fd_sc_hd__clkbuf_2 instances:  13
+  Class: sky130_fd_sc_hd__clkbuf_4 instances:  15
+  Class: sky130_fd_sc_hd__clkbuf_8 instances:  11
+  Class: sky130_fd_sc_hd__nand3_1 instances:   4
+  Class: sky130_fd_sc_hd__and2b_1 instances:   1
+  Class: sky130_fd_sc_hd__conb_1 instances: 262
+  Class: sky130_fd_sc_hd__buf_12 instances:  83
+  Class: sky130_fd_sc_hd__and3_1 instances:   7
+  Class: sky130_fd_sc_hd__and3_2 instances:   2
+  Class: sky130_fd_sc_hd__decap_3 instances: 1862
+  Class: sky130_fd_sc_hd__decap_4 instances: 567
+  Class: sky130_fd_sc_hd__decap_6 instances: 67936
+  Class: sky130_fd_sc_hd__decap_8 instances: 484
+  Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 174
+  Class: sky130_fd_sc_hd__or2_1 instances:   4
+  Class: sky130_fd_sc_hd__nand2_1 instances:   7
+  Class: sky130_fd_sc_hd__nand2_8 instances:   2
+  Class: sky130_fd_sc_hd__mux2_1 instances:  17
+  Class: sky130_fd_sc_hd__and2_1 instances:  13
+  Class: sky130_fd_sc_hd__inv_12 instances:   1
+  Class: sky130_fd_sc_hd__o211a_1 instances:   1
+  Class: sky130_fd_sc_hd__nand2b_1 instances:   1
+  Class: sky130_fd_sc_hd__diode_2 instances: 719
+  Class: sky130_fd_sc_hd__a221o_1 instances:   1
+  Class: sky130_fd_sc_hd__o2111a_1 instances:   1
+  Class: sky130_fd_sc_hd__dlymetal6s2s_1 instances:   1
+  Class: sky130_fd_sc_hd__a32o_1 instances:  17
+  Class: sky130_fd_sc_hd__a22o_1 instances:   1
+  Class: sky130_fd_sc_hd__o21a_1 instances:   7
+  Class: sky130_fd_sc_hd__and4b_2 instances:   1
+  Class: sky130_fd_sc_hd__o21ai_2 instances:   1
+  Class: sky130_fd_sc_hd__nor2_4 instances:   1
+Circuit contains 1257 nets, and 286 disconnected pins.
+
+Circuit was modified by parallel/series device merging.
+New circuit summary:
+
+Contents of circuit 1:  Circuit: 'user_proj_example'
+Circuit user_proj_example contains 1152 device instances.
+  Class: sky130_fd_sc_hd__a31o_1 instances:  12
+  Class: sky130_fd_sc_hd__a21o_1 instances:   9
+  Class: sky130_fd_sc_hd__a21o_2 instances:   1
+  Class: sky130_fd_sc_hd__clkbuf_16 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_1 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_2 instances:   5
+  Class: sky130_fd_sc_hd__dfxtp_4 instances:  15
+  Class: sky130_fd_sc_hd__nand4_1 instances:   1
+  Class: sky130_fd_sc_hd__buf_1 instances:  34
+  Class: sky130_fd_sc_hd__buf_2 instances: 138
+  Class: sky130_fd_sc_hd__buf_4 instances:   2
+  Class: sky130_fd_sc_hd__buf_6 instances:   6
+  Class: sky130_fd_sc_hd__buf_8 instances:  10
+  Class: sky130_fd_sc_hd__a2bb2o_1 instances:   1
+  Class: sky130_fd_sc_hd__and3b_1 instances:   1
+  Class: sky130_fd_sc_hd__xor2_1 instances:   1
+  Class: sky130_ef_sc_hd__decap_12 instances:   1
+  Class: sky130_fd_sc_hd__and4_2 instances:   3
+  Class: sky130_fd_sc_hd__inv_2 instances:  20
+  Class: sky130_fd_sc_hd__clkbuf_2 instances:  13
+  Class: sky130_fd_sc_hd__clkbuf_4 instances:  15
+  Class: sky130_fd_sc_hd__clkbuf_8 instances:  11
+  Class: sky130_fd_sc_hd__nand3_1 instances:   4
+  Class: sky130_fd_sc_hd__and2b_1 instances:   1
+  Class: sky130_fd_sc_hd__conb_1 instances: 262
+  Class: sky130_fd_sc_hd__buf_12 instances:  83
+  Class: sky130_fd_sc_hd__and3_1 instances:   7
+  Class: sky130_fd_sc_hd__and3_2 instances:   2
+  Class: sky130_fd_sc_hd__decap_3 instances:   1
+  Class: sky130_fd_sc_hd__decap_4 instances:   1
+  Class: sky130_fd_sc_hd__decap_6 instances:   1
+  Class: sky130_fd_sc_hd__decap_8 instances:   1
+  Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 174
+  Class: sky130_fd_sc_hd__or2_1 instances:   4
+  Class: sky130_fd_sc_hd__nand2_1 instances:   7
+  Class: sky130_fd_sc_hd__nand2_8 instances:   2
+  Class: sky130_fd_sc_hd__mux2_1 instances:  17
+  Class: sky130_fd_sc_hd__and2_1 instances:  13
+  Class: sky130_fd_sc_hd__inv_12 instances:   1
+  Class: sky130_fd_sc_hd__o211a_1 instances:   1
+  Class: sky130_fd_sc_hd__nand2b_1 instances:   1
+  Class: sky130_fd_sc_hd__diode_2 instances: 213
+  Class: sky130_fd_sc_hd__a221o_1 instances:   1
+  Class: sky130_fd_sc_hd__o2111a_1 instances:   1
+  Class: sky130_fd_sc_hd__dlymetal6s2s_1 instances:   1
+  Class: sky130_fd_sc_hd__a32o_1 instances:  17
+  Class: sky130_fd_sc_hd__a22o_1 instances:   1
+  Class: sky130_fd_sc_hd__o21a_1 instances:   7
+  Class: sky130_fd_sc_hd__and4b_2 instances:   1
+  Class: sky130_fd_sc_hd__o21ai_2 instances:   1
+  Class: sky130_fd_sc_hd__nor2_4 instances:   1
+Circuit contains 1257 nets, and 286 disconnected pins.
+Contents of circuit 2:  Circuit: 'user_proj_example'
+Circuit user_proj_example contains 1152 device instances.
+  Class: sky130_fd_sc_hd__a31o_1 instances:  12
+  Class: sky130_fd_sc_hd__a21o_1 instances:   9
+  Class: sky130_fd_sc_hd__a21o_2 instances:   1
+  Class: sky130_fd_sc_hd__clkbuf_16 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_1 instances:  13
+  Class: sky130_fd_sc_hd__dfxtp_2 instances:   5
+  Class: sky130_fd_sc_hd__dfxtp_4 instances:  15
+  Class: sky130_fd_sc_hd__nand4_1 instances:   1
+  Class: sky130_fd_sc_hd__buf_1 instances:  34
+  Class: sky130_fd_sc_hd__buf_2 instances: 138
+  Class: sky130_fd_sc_hd__buf_4 instances:   2
+  Class: sky130_fd_sc_hd__buf_6 instances:   6
+  Class: sky130_fd_sc_hd__buf_8 instances:  10
+  Class: sky130_fd_sc_hd__a2bb2o_1 instances:   1
+  Class: sky130_fd_sc_hd__and3b_1 instances:   1
+  Class: sky130_fd_sc_hd__xor2_1 instances:   1
+  Class: sky130_ef_sc_hd__decap_12 instances:   1
+  Class: sky130_fd_sc_hd__and4_2 instances:   3
+  Class: sky130_fd_sc_hd__inv_2 instances:  20
+  Class: sky130_fd_sc_hd__clkbuf_2 instances:  13
+  Class: sky130_fd_sc_hd__clkbuf_4 instances:  15
+  Class: sky130_fd_sc_hd__clkbuf_8 instances:  11
+  Class: sky130_fd_sc_hd__nand3_1 instances:   4
+  Class: sky130_fd_sc_hd__and2b_1 instances:   1
+  Class: sky130_fd_sc_hd__conb_1 instances: 262
+  Class: sky130_fd_sc_hd__buf_12 instances:  83
+  Class: sky130_fd_sc_hd__and3_1 instances:   7
+  Class: sky130_fd_sc_hd__and3_2 instances:   2
+  Class: sky130_fd_sc_hd__decap_3 instances:   1
+  Class: sky130_fd_sc_hd__decap_4 instances:   1
+  Class: sky130_fd_sc_hd__decap_6 instances:   1
+  Class: sky130_fd_sc_hd__decap_8 instances:   1
+  Class: sky130_fd_sc_hd__dlygate4sd3_1 instances: 174
+  Class: sky130_fd_sc_hd__or2_1 instances:   4
+  Class: sky130_fd_sc_hd__nand2_1 instances:   7
+  Class: sky130_fd_sc_hd__nand2_8 instances:   2
+  Class: sky130_fd_sc_hd__mux2_1 instances:  17
+  Class: sky130_fd_sc_hd__and2_1 instances:  13
+  Class: sky130_fd_sc_hd__inv_12 instances:   1
+  Class: sky130_fd_sc_hd__o211a_1 instances:   1
+  Class: sky130_fd_sc_hd__nand2b_1 instances:   1
+  Class: sky130_fd_sc_hd__diode_2 instances: 213
+  Class: sky130_fd_sc_hd__a221o_1 instances:   1
+  Class: sky130_fd_sc_hd__o2111a_1 instances:   1
+  Class: sky130_fd_sc_hd__dlymetal6s2s_1 instances:   1
+  Class: sky130_fd_sc_hd__a32o_1 instances:  17
+  Class: sky130_fd_sc_hd__a22o_1 instances:   1
+  Class: sky130_fd_sc_hd__o21a_1 instances:   7
+  Class: sky130_fd_sc_hd__and4b_2 instances:   1
+  Class: sky130_fd_sc_hd__o21ai_2 instances:   1
+  Class: sky130_fd_sc_hd__nor2_4 instances:   1
+Circuit contains 1257 nets, and 286 disconnected pins.
+
+Circuit 1 contains 1152 devices, Circuit 2 contains 1152 devices.
+Circuit 1 contains 1257 nets,    Circuit 2 contains 1257 nets.
+
+
+Final result: 
+Circuits match uniquely.
+.
+Logging to file "/home/karim/work/caravel_user_project/openlane/user_proj_example/runs/23_08_27_13_11/47-netgen-lvs/lvs.rpt" disabled
+LVS Done.