RISE RP005 QEMU weekly report 2024-10-09

Work completed since last report

WP2
- Compacted loop of the first Embecosm patch to 8 byte per iteration.
- Complete SiFive library function set.
  - Complete
  - full results not available, due to some vector instructions triggering SIGILL with VLEN=1024 and LMUL=m8 (under investigation).
- Continue to work on the separation of the large load/store patch.
  - Stopped
- Single instruction benchmarking relevant to SiFive library functions.
  - waiting on solving the SIGILL problem.
- Continue to work on AArch64 comparison.
  - No further progress
- Analysed the glibc memcpy benchmark results presented last week by Max.
  - Embecosm's patches weren't completely included or used optimally in the presented configuration.
Actions:
- Max: share patches applied to our benchmarking scripts. Complete
- Max: run SPECCPU 2017 results again with VLEN=128 and LMUL=1 and enabled OpenMP. Still awaited

Work planned for the coming week

WP2
- Measure impact of 8 bytes per iteration patch (see above).
- Single instruction benchmarking relevant to SiFive library functions.
- Continue to work on AArch64 comparison.
- Measure the glibc bencmark with VLEN=128/LMUL=1.
- Work on new optimizations for vector loads/stores.
  - Identify optimizations for those of the 14 SiFve string/memory functions where the current patch shows no improvement.

Planned absences

Jeremy Bennett will be on vacation 12-19 October
Jeremy Bennett will be at the RISC-V NA Summit 21-24 October
Paolo Savini will be at the LLVM Developers' Meeting 22-24 October