From 405296b7fd99764af21fffd94afa5075c22affa8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 31 Aug 2023 19:34:55 +0200 Subject: [PATCH] interconnect/axi/axi_full: Fix missing switch to LiteXModule. --- litex/soc/interconnect/axi/axi_full.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py index bc887ac34e..e073ef3567 100644 --- a/litex/soc/interconnect/axi/axi_full.py +++ b/litex/soc/interconnect/axi/axi_full.py @@ -602,12 +602,12 @@ def get_check_parameters(ports): return data_width -class AXIInterconnectPointToPoint(Module): +class AXIInterconnectPointToPoint(LiteXModule): """AXI point to point interconnect""" def __init__(self, master, slave): self.comb += master.connect(slave) -class AXIInterconnectShared(Module): +class AXIInterconnectShared(LiteXModule): """AXI shared interconnect""" def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): data_width = get_check_parameters(ports=masters + [s for _, s in slaves])