UART Core using add_uart in soc.py, Rare Transmission Error on first byte of sequence

[Haron123]

Hello

How i found the Issue

Target File (Snippet)

# Uart
self.add_uart("serial0", "uart0", baudrate=9600)

C++ Driver (Snippet)

UserSerial::UserSerial()
{
	serial0_ev_pending_write(serial0_ev_pending_read());
	serial0_ev_enable_write(UART_EV_TX | UART_EV_RX);
}

void UserSerial::write(uint8_t byte)
{
	/* Wait for UART tx buffer to be free */
	while(serial0_txfull_read());
	serial0_rxtx_write(byte);
	serial0_ev_pending_write(UART_EV_TX);
}

Test Code (Snippet)

serial.write('0');
serial.write('0');
serial.write('0');

Expected Result

"000" on the Serial Console, 0x30, 0x30, 0x30 on Logic Analyzer

Actual Result

"00" on the Serial Console, 0x00, 0x30, 0x30 on Logic Analyzer

When does it Occur

It seems to occur on the first Byte after restarting the SoC, sometimes i get the issue even after slight Delays. It is as far as i saw always the first Byte of a sequence which gets turned to 0x00.

What did i try to fix it

i tried to use add_auto_tx_flush to the uart, though that gave me errors with Yosys. Incase someone has an example usage of this and thinks it might fix it, id love if you can share it.