From c955cebb9b2850978bca9b4caa4cba5e2068f6c5 Mon Sep 17 00:00:00 2001 From: Patrick Roy Date: Tue, 12 Sep 2023 08:43:24 +0100 Subject: [PATCH] chore: Update MSR baselines for T2CL on kernel 5.10 Now that our kernel 5.10 AMIs have the KVM patch to enable GDS_NO when the required microcode is installed on the host, updates MSR baselines. Signed-off-by: Patrick Roy --- .../msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv | 2 +- .../msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv | 2 +- .../data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv | 2 +- .../data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv index def1808bd85..e0ce02b2e28 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_4.14guest.csv @@ -18,7 +18,7 @@ MSR_ADDR,VALUE 0xcd,0x3 0xce,0x80000000 0xfe,0x508 -0x10a,0xaa0eb +0x10a,0x40aa0eb 0x11e,0xbe702111 0x122,0x3 0x140,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv index 8da25b2ab8f..388b7a7f566 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv @@ -18,7 +18,7 @@ MSR_ADDR,VALUE 0xcd,0x3 0xce,0x80000000 0xfe,0x508 -0x10a,0xaa0eb +0x10a,0x40aa0eb 0x11e,0xbe702111 0x122,0x3 0x140,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv index 42f0ca3d49d..7d11ac9340a 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_4.14guest.csv @@ -18,7 +18,7 @@ MSR_ADDR,VALUE 0xcd,0x3 0xce,0x80000000 0xfe,0x508 -0x10a,0x2a0eb +0x10a,0x402a0eb 0x11e,0xbe702111 0x122,0x3 0x140,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv index a13de5cdc70..0686e45889f 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv @@ -18,7 +18,7 @@ MSR_ADDR,VALUE 0xcd,0x3 0xce,0x80000000 0xfe,0x508 -0x10a,0x2a0eb +0x10a,0x402a0eb 0x11e,0xbe702111 0x122,0x3 0x140,0x0