From 9550c4aa4128d8c0affe3f72ad7e6d8389c6b575 Mon Sep 17 00:00:00 2001 From: "CCR\\huqiuhua" Date: Fri, 4 Aug 2023 13:59:03 +0800 Subject: [PATCH 01/22] pcm-accel: return value 0 to avoid the confuse to user if overflow happen. --- src/cpucounters.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/cpucounters.h b/src/cpucounters.h index 0da43604..2c0c6cb1 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -4356,6 +4356,12 @@ inline double getLocalMemoryRequestRatio(const CounterStateType & before, const template inline uint64 getNumberOfEvents(const CounterType & before, const CounterType & after) { + // prevent overflows due to counter dissynchronisation + if (after.data < before.data) + { + return 0; + } + return after.data - before.data; } //! \brief Returns average last level cache read+prefetch miss latency in ns From ff011f78b7fc13e5acf95649f3f64053f93382c4 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 4 Aug 2023 11:45:53 +0200 Subject: [PATCH 02/22] add UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES test Change-Id: Iad2bc336a296f801f72e6848befe27a9c70857db --- tests/test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/test.sh b/tests/test.sh index 60f22ec6..e5124075 100755 --- a/tests/test.sh +++ b/tests/test.sh @@ -319,6 +319,7 @@ UNC_UPI_TxL0P_POWER_CYCLES UNC_UPI_RxL0P_POWER_CYCLES UNC_UPI_RxL_FLITS.ALL_DATA UNC_UPI_RxL_FLITS.NON_DATA +UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES MSR_EVENT:msr=0x10:type=FREERUN:scope=thread MSR_EVENT:msr=0x10:type=static:scope=thread pcicfg/config=0x2021,config1=4,config2=0,width=32 From 6f04f38bfbba355e4c1017fc1e44616145a04bc2 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 4 Aug 2023 12:53:38 +0200 Subject: [PATCH 03/22] add pcu in GenuineIntel-6-55-4.json Change-Id: I29b1e15ca76deb1d45c7502d89ad514aaaad03dd --- src/PMURegisterDeclarations/GenuineIntel-6-55-4.json | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-55-4.json b/src/PMURegisterDeclarations/GenuineIntel-6-55-4.json index 6a8626e2..2d39fd49 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-55-4.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-55-4.json @@ -100,6 +100,13 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} } }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, "irp" : { "programmable" : { "EventCode": {"Config": 0, "Position": 0, "Width": 8}, From c3effcf5ad34e512242cb91c9b1168d1c2105fda Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Fri, 4 Aug 2023 13:43:43 +0200 Subject: [PATCH 04/22] add pcu in GenuineIntel-6-55-{7,B}.json Change-Id: I42f2c398678770aae4b579e00ca41cf6f614c782 --- src/PMURegisterDeclarations/GenuineIntel-6-55-7.json | 7 +++++++ src/PMURegisterDeclarations/GenuineIntel-6-55-B.json | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-55-7.json b/src/PMURegisterDeclarations/GenuineIntel-6-55-7.json index 6a8626e2..2d39fd49 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-55-7.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-55-7.json @@ -100,6 +100,13 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} } }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, "irp" : { "programmable" : { "EventCode": {"Config": 0, "Position": 0, "Width": 8}, diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-55-B.json b/src/PMURegisterDeclarations/GenuineIntel-6-55-B.json index 6a8626e2..2d39fd49 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-55-B.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-55-B.json @@ -100,6 +100,13 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} } }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, "irp" : { "programmable" : { "EventCode": {"Config": 0, "Position": 0, "Width": 8}, From 7b1a9c1e4db48b57e0478633778ee7e0209e6bb7 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Tue, 12 Sep 2023 16:01:19 +0200 Subject: [PATCH 05/22] add MMIOEventPosition Change-Id: If426b41f04c97e490115f594146d5e5aea8ebff5 --- src/cpucounters.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/cpucounters.h b/src/cpucounters.h index 2c0c6cb1..0b9573c6 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1323,6 +1323,18 @@ class PCM_API PCM && a[PCICFGEventPosition::width] == b[PCICFGEventPosition::width]; } }; + struct MMIOEventPosition + { + enum constants + { + deviceID = PCICFGEventPosition::deviceID, + offset = PCICFGEventPosition::offset, + type = PCICFGEventPosition::type, + membar_bits1 = 3, + membar_bits2 = 4, + width = PCICFGEventPosition::width + }; + }; private: std::unordered_map, PCICFGRegisterEncodingHash, PCICFGRegisterEncodingCmp> PCICFGRegisterLocations{}; public: From 9e6ab5527e0322015928b6265a7b64b595e7b1ce Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 13 Sep 2023 11:48:23 +0200 Subject: [PATCH 06/22] add more MMIO reg functions Change-Id: Ia03f53b21dbb9a26912e92bcd77e3d257d275adf --- src/cpucounters.h | 46 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/src/cpucounters.h b/src/cpucounters.h index 0b9573c6..77d86c57 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -1015,6 +1015,7 @@ class PCM_API PCM void readMSRs(std::shared_ptr msr, const RawPMUConfig & msrConfig, CounterStateType & result); void readQPICounters(SystemCounterState & counterState); void readPCICFGRegisters(SystemCounterState& result); + void readMMIORegisters(SystemCounterState& result); void reportQPISpeed() const; void readCoreCounterConfig(const bool complainAboutMSR = false); void readCPUMicrocodeLevel(); @@ -1335,8 +1336,28 @@ class PCM_API PCM width = PCICFGEventPosition::width }; }; + typedef std::pair, uint32> MMIORegisterEncoding; // MMIORange shared ptr, offset + struct MMIORegisterEncodingHash : public PCICFGRegisterEncodingHash + { + std::size_t operator()(const RawEventEncoding& e) const + { + std::size_t h4 = std::hash{}(e[MMIOEventPosition::membar_bits1]); + std::size_t h5 = std::hash{}(e[MMIOEventPosition::membar_bits2]); + return PCICFGRegisterEncodingHash::operator()(e) ^ (h4 << 3ULL) ^ (h5 << 4ULL); + } + }; + struct MMIORegisterEncodingCmp : public PCICFGRegisterEncodingCmp + { + bool operator ()(const RawEventEncoding& a, const RawEventEncoding& b) const + { + return PCICFGRegisterEncodingCmp::operator()(a,b) + && a[MMIOEventPosition::membar_bits1] == b[MMIOEventPosition::membar_bits1] + && a[MMIOEventPosition::membar_bits2] == b[MMIOEventPosition::membar_bits2]; + } + }; private: std::unordered_map, PCICFGRegisterEncodingHash, PCICFGRegisterEncodingCmp> PCICFGRegisterLocations{}; + std::unordered_map, MMIORegisterEncodingHash, MMIORegisterEncodingCmp> MMIORegisterLocations{}; public: TopologyEntry::CoreType getCoreType(const unsigned coreID) const @@ -1601,7 +1622,7 @@ class PCM_API PCM } return false; } - RawPMUConfig threadMSRConfig{}, packageMSRConfig{}, pcicfgConfig{}; + RawPMUConfig threadMSRConfig{}, packageMSRConfig{}, pcicfgConfig{}, mmioConfig{}; public: //! \brief Reads CPU model id @@ -3310,12 +3331,14 @@ class SystemCounterState : public SocketCounterState { friend class PCM; friend std::vector getPCICFGEvent(const PCM::RawEventEncoding& eventEnc, const SystemCounterState& before, const SystemCounterState& after); + friend std::vector getMMIOEvent(const PCM::RawEventEncoding& eventEnc, const SystemCounterState& before, const SystemCounterState& after); std::vector > incomingQPIPackets; // each 64 byte std::vector > outgoingQPIFlits; // idle or data/non-data flits depending on the architecture std::vector > TxL0Cycles; uint64 uncoreTSC; std::unordered_map , PCM::PCICFGRegisterEncodingHash, PCM::PCICFGRegisterEncodingCmp> PCICFGValues{}; + std::unordered_map, PCM::MMIORegisterEncodingHash, PCM::MMIORegisterEncodingCmp> MMIOValues{}; protected: void readAndAggregate(std::shared_ptr handle) @@ -4452,13 +4475,14 @@ inline double getRetiring(const CounterStateType & before, const CounterStateTyp return 0.; } -inline std::vector getPCICFGEvent(const PCM::RawEventEncoding & eventEnc, const SystemCounterState& before, const SystemCounterState& after) +template +inline std::vector getRegisterEvent(const PCM::RawEventEncoding& eventEnc, const ValuesType& beforeValues, const ValuesType& afterValues) { std::vector result{}; - auto beforeIter = before.PCICFGValues.find(eventEnc); - auto afterIter = after.PCICFGValues.find(eventEnc); - if (beforeIter != before.PCICFGValues.end() && - afterIter != after.PCICFGValues.end()) + auto beforeIter = beforeValues.find(eventEnc); + auto afterIter = afterValues.find(eventEnc); + if (beforeIter != beforeValues.end() && + afterIter != afterValues.end()) { const auto& beforeValues = beforeIter->second; const auto& afterValues = afterIter->second; @@ -4480,6 +4504,16 @@ inline std::vector getPCICFGEvent(const PCM::RawEventEncoding & eventEnc return result; } +inline std::vector getPCICFGEvent(const PCM::RawEventEncoding & eventEnc, const SystemCounterState& before, const SystemCounterState& after) +{ + return getRegisterEvent(eventEnc, before.PCICFGValues, after.PCICFGValues); +} + +inline std::vector getMMIOEvent(const PCM::RawEventEncoding& eventEnc, const SystemCounterState& before, const SystemCounterState& after) +{ + return getRegisterEvent(eventEnc, before.MMIOValues, after.MMIOValues); +} + template uint64 getMSREvent(const uint64& index, const PCM::MSRType& type, const CounterStateType& before, const CounterStateType& after) { From 2c7adc4a6eef7c442326508b50b805e5e275bc18 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 13 Sep 2023 12:31:25 +0200 Subject: [PATCH 07/22] populate MMIORegisterLocations Change-Id: I5fa846f3c1be33504e02630679f37854f1fed215 --- src/cpucounters.cpp | 49 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 850ef297..49e15387 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -5435,6 +5435,7 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile threadMSRConfig = RawPMUConfig{}; packageMSRConfig = RawPMUConfig{}; pcicfgConfig = RawPMUConfig{}; + mmioConfig = RawPMUConfig{}; RawPMUConfigs curPMUConfigs = curPMUConfigs_; constexpr auto globalRegPos = 0ULL; PCM::ExtendedCustomCoreEventDescription conf; @@ -5649,6 +5650,54 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile addLocations(pcicfgConfig.programmable); addLocations(pcicfgConfig.fixed); } + else if (type == "mmio") + { + mmioConfig = pmuConfig.second; + auto addLocations = [this](const std::vector& configs) { + for (const auto& c : configs) + { + if (MMIORegisterLocations.find(c.first) == MMIORegisterLocations.end()) + { + // add locations + std::vector locations; + const auto deviceID = c.first[MMIOEventPosition::deviceID]; + forAllIntelDevices([&locations, &deviceID, &c](const uint32 group, const uint32 bus, const uint32 device, const uint32 function, const uint32 device_id) + { + if (deviceID == device_id && PciHandleType::exists(group, bus, device, function)) + { + PciHandleType pciHandle(group, bus, device, function); + auto computeBarOffset = [&pciHandle](uint64 membarBits) -> size_t + { + if (membarBits) + { + const auto destPos = extract_bits(membarBits, 32, 39); + const auto numBits = extract_bits(membarBits, 24, 31); + const auto srcPos = extract_bits(membarBits, 16, 23); + const auto pcicfgOffset = extract_bits(membarBits, 0, 15); + uint32 memBarOffset = 0; + pciHandle.read32(pcicfgOffset, &memBarOffset); + return size_t(extract_bits_ui(memBarOffset, srcPos, srcPos + numBits - 1)) << destPos; + } + return 0; + }; + + size_t memBar = computeBarOffset(c.first[MMIOEventPosition::membar_bits1]) + | computeBarOffset(c.first[MMIOEventPosition::membar_bits2]); + + assert(memBar); + + const size_t addr = memBar + c.first[MMIOEventPosition::offset]; + // MMIORange shared ptr (handle), offset + locations.push_back(MMIORegisterEncoding{ std::make_shared(addr & ~4095ULL, 4096), (uint32) (addr & 4095ULL) }); + } + }); + MMIORegisterLocations[c.first] = locations; + } + } + }; + addLocations(mmioConfig.programmable); + addLocations(mmioConfig.fixed); + } else if (type == "cxlcm") { programCXLCM(events64); From b1ed56286ae484ba4d0a2ea33cb82365d9a08df2 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 13 Sep 2023 13:39:11 +0200 Subject: [PATCH 08/22] add readMMIORegisters Change-Id: Id979370acc64d083e060e6f4846479f681301e15 --- src/cpucounters.cpp | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 49e15387..bf4ec833 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -6119,6 +6119,50 @@ void PCM::readPCICFGRegisters(SystemCounterState& systemState) } } +void PCM::readMMIORegisters(SystemCounterState& systemState) +{ + auto read = [this, &systemState](const RawEventConfig& cfg) { + const RawEventEncoding& reEnc = cfg.first; + systemState.MMIOValues[reEnc].clear(); + for (auto& reg : MMIORegisterLocations[reEnc]) + { + const auto width = reEnc[MMIOEventPosition::width]; + auto& h = reg.first; + const auto& offset = reg.second; + if (h.get()) + { + uint64 value = ~0ULL; + uint32 value32 = 0; + switch (width) + { + case 16: + value32 = h->read32(offset); + value = (uint64)extract_bits_ui(value32, 0, 15); + break; + case 32: + value32 = h->read32(offset); + value = (uint64)value32; + break; + case 64: + value = h->read64(offset); + break; + default: + std::cerr << "ERROR: Unsupported width " << width << " for mmio register " << cfg.second << "\n"; + } + systemState.MMIOValues[reEnc].push_back(value); + } + } + }; + for (const auto& cfg : mmioConfig.programmable) + { + read(cfg); + } + for (const auto& cfg : mmioConfig.fixed) + { + read(cfg); + } +} + void PCM::readQPICounters(SystemCounterState & result) { // read QPI counters @@ -6323,6 +6367,7 @@ void PCM::getAllCounterStates(SystemCounterState & systemState, std::vector Date: Wed, 13 Sep 2023 14:09:47 +0200 Subject: [PATCH 09/22] pcm-raw: add support of mmio register reads Change-Id: I9eeeb5a418106b9635d5b1877312cd39a98cb2b9 --- src/pcm-raw.cpp | 108 +++++++++++++++++++++++++++++++----------------- 1 file changed, 70 insertions(+), 38 deletions(-) diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index d8ba2493..dbe7275d 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -1179,6 +1179,22 @@ std::string getPCICFGEventString(const PCM::RawEventEncoding & eventEnc, const s return c.str(); } +std::string getMMIOEventString(const PCM::RawEventEncoding& eventEnc, const std::string& type) +{ + std::stringstream c; + c << type << ":0x" << std::hex << + eventEnc[PCM::MMIOEventPosition::deviceID] << + ":0x" << eventEnc[PCM::MMIOEventPosition::offset] << + ":0x" << eventEnc[PCM::MMIOEventPosition::membar_bits1] << + ":0x" << eventEnc[PCM::MMIOEventPosition::membar_bits2] << + ":0x" << eventEnc[PCM::MMIOEventPosition::width] << + ":" << getTypeString(eventEnc[PCM::MMIOEventPosition::type]); + return c.str(); +} + +typedef std::string(*getEventStringFunc)(const PCM::RawEventEncoding& eventEnc, const std::string& type); +typedef std::vector(getEventFunc)(const PCM::RawEventEncoding& eventEnc, const SystemCounterState& before, const SystemCounterState& after); + enum MSRScope { Thread, @@ -1462,28 +1478,12 @@ void printTransposed(const PCM::RawPMUConfigs& curPMUConfigs, is_header_printed = true; } }; - if (type == "core") - { - printCores(pcm::TopologyEntry::Core); - } - else if (type == "atom") - { - printCores(pcm::TopologyEntry::Atom); - } - else if (type == "thread_msr") - { - printMSRRows(MSRScope::Thread); - } - else if (type == "package_msr") - { - printMSRRows(MSRScope::Package); - } - else if (type == "pcicfg") + auto printRegisterRows = [&](getEventStringFunc getEventString, getEventFunc getEvent) { auto printRegister = [&](const PCM::RawEventConfig& event) -> bool { - const std::string name = (event.second.empty()) ? getPCICFGEventString(event.first, type) : event.second; - const auto values = getPCICFGEvent(event.first, SysBeforeState, SysAfterState); + const std::string name = (event.second.empty()) ? getEventString(event.first, type) : event.second; + const auto values = getEvent(event.first, SysBeforeState, SysAfterState); if (is_header && is_header_printed) return false; @@ -1541,6 +1541,30 @@ void printTransposed(const PCM::RawPMUConfigs& curPMUConfigs, break; } } + }; + if (type == "core") + { + printCores(pcm::TopologyEntry::Core); + } + else if (type == "atom") + { + printCores(pcm::TopologyEntry::Atom); + } + else if (type == "thread_msr") + { + printMSRRows(MSRScope::Thread); + } + else if (type == "package_msr") + { + printMSRRows(MSRScope::Package); + } + else if (type == "pcicfg") + { + printRegisterRows(getPCICFGEventString, getPCICFGEvent); + } + else if (type == "mmio") + { + printRegisterRows(getMMIOEventString, getMMIOEvent); } else if (type == "m3upi") { @@ -1738,6 +1762,28 @@ void print(const PCM::RawPMUConfigs& curPMUConfigs, } } }; + auto printRegisters = [&](getEventStringFunc getEventString, getEventFunc getEvent) + { + auto printOneRegister = [&](const PCM::RawEventConfig& event) + { + const auto values = getEvent(event.first, SysBeforeState, SysAfterState); + for (size_t r = 0; r < values.size(); ++r) + { + choose(outputType, + [&r]() { cout << "SYSTEM_" << r << separator; }, + [&]() { if (event.second.empty()) cout << getEventString(event.first, type) << separator; else cout << event.second << separator; }, + [&]() { cout << values[r] << separator; }); + } + }; + for (const auto& event : events) + { + printOneRegister(event); + } + for (const auto& event : fixedEvents) + { + printOneRegister(event); + } + }; if (type == "core") { printCores(pcm::TopologyEntry::Core); @@ -1888,25 +1934,11 @@ void print(const PCM::RawPMUConfigs& curPMUConfigs, } else if (type == "pcicfg") { - auto printPCICFG = [&](const PCM::RawEventConfig& event) - { - const auto values = getPCICFGEvent(event.first, SysBeforeState, SysAfterState); - for (size_t r = 0; r < values.size(); ++r) - { - choose(outputType, - [&r]() { cout << "SYSTEM_" << r << separator; }, - [&]() { if (event.second.empty()) cout << getPCICFGEventString(event.first, type) << separator; else cout << event.second << separator; }, - [&]() { cout << values[r] << separator; }); - } - }; - for (const auto& event : events) - { - printPCICFG(event); - } - for (const auto& event : fixedEvents) - { - printPCICFG(event); - } + printRegisters(getPCICFGEventString, getPCICFGEvent); + } + else if (type == "mmio") + { + printRegisters(getMMIOEventString, getMMIOEvent); } else if (type == "ubox") { From 878b6b1ae2d9e5147502e3d3c6a09d824657f55f Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Thu, 14 Sep 2023 10:52:04 +0200 Subject: [PATCH 10/22] document MMIO register access --- doc/PCM_RAW_README.md | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/doc/PCM_RAW_README.md b/doc/PCM_RAW_README.md index 95ce5947..4fae6275 100644 --- a/doc/PCM_RAW_README.md +++ b/doc/PCM_RAW_README.md @@ -77,6 +77,35 @@ pcicfg32/config=0xe20,config1=0x180,config2=0x0,name=CHANERR_INT ``` From: https://www.intel.la/content/dam/www/public/us/en/documents/datasheets/xeon-e7-v2-datasheet-vol-2.pdf +MMIO Registers: + +``` +mmio/config=,config1=,config2=,config3=[,config4=],width=[,name=] +``` + +The MEMBAR is computed by logically ORing the result of membar_bits1 and membar_bits1 computation described below (PCICFG read + bit extraction and shift). The final MMIO register address = MEMBAR + offset. + +* width: register width in bits (16,32,64) +* dev_id: Intel PCI device id where the membar address registers are located +* membar_bits1: mmioBase register bits to compute membar (base address) + - bits 0-15 : PCICFG register offset to read membar1 bits + - bits 16-23: source position of membar bits in the PCICFG register + - bits 24-31: number of bits + - bits 32-39: destination bit position in the membar +* membar_bits2: mmioBase register bits to compute membar (base address), can be zero if only membar_bits1 is sufficient for locating the register. + - bits 0-15 : PCICFG register offset to read membar2 bits + - bits 16-23: source position of membar bits in the PCICFG register + - bits 24-31: number of bits + - bits 32-39: destination bit position in the membar +* offset: offset of the MMIO register relative to the membar +* static_or_freerun: same syntax as for MSR registers + +Example (Icelake server iMC PMON MMIO register read): + +``` +mmio/config=0x3451,config1=0x22808,config2=1,config3=0x171D0000D0,config4=0x0c0b0000d8,width=64 +``` + -------------------------------------------------------------------------------- Collecting Events By Names From Event Lists (https://github.com/intel/perfmon/) -------------------------------------------------------------------------------- From 76eb36d4b04db1c03517809a3b29a5828f534bef Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Mon, 18 Sep 2023 10:35:53 +0200 Subject: [PATCH 11/22] pcm-raw: add support of opc field for BDX --- src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json | 3 ++- src/pcm-raw.cpp | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json index e660ba7a..541399c8 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json @@ -64,7 +64,8 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, "Filter0": {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0}, "TID": {"Config": 1, "Position": 0, "Width": 6, "DefaultValue": 0}, - "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59} + "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59}, + "OPC": {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0} } }, "imc" : { diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index dbe7275d..323ed340 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -822,6 +822,10 @@ AddEventStatus addEventFromDB(PCM::RawPMUConfigs& curPMUConfigs, string fullEven { setField("Filter1", read_number(assignment[1].c_str())); } + else if (assignment.size() == 2 && assignment[0] == "opc") + { + setField("OPC", read_number(assignment[1].c_str())); + } else if (assignment.size() == 2 && assignment[0] == "t") { setField("Threshold", read_number(assignment[1].c_str())); From 4ef546571cfad81827f237e147d1f00cfdb4156b Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Mon, 18 Sep 2023 10:57:45 +0200 Subject: [PATCH 12/22] pcm-raw: add support of state field for BDX --- src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json | 1 + src/pcm-raw.cpp | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json index 541399c8..44be66fb 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json @@ -64,6 +64,7 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0}, "Filter0": {"Config": 1, "Position": 0, "Width": 64, "DefaultValue": 0}, "TID": {"Config": 1, "Position": 0, "Width": 6, "DefaultValue": 0}, + "State": {"Config": 1, "Position": 17, "Width": 7, "DefaultValue": 0}, "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59}, "OPC": {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0} } diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index 323ed340..49097756 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -826,6 +826,10 @@ AddEventStatus addEventFromDB(PCM::RawPMUConfigs& curPMUConfigs, string fullEven { setField("OPC", read_number(assignment[1].c_str())); } + else if (assignment.size() == 2 && assignment[0] == "state") + { + setField("State", read_number(assignment[1].c_str())); + } else if (assignment.size() == 2 && assignment[0] == "t") { setField("Threshold", read_number(assignment[1].c_str())); From 0aa31fd9ea5863b60efccee18db74d96baad79aa Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Mon, 18 Sep 2023 11:39:18 +0200 Subject: [PATCH 13/22] pcm-raw: add support of nc and isoc field for BDX Change-Id: I69eecd47bf1e54ced67f27fd7d6d0d101adc30f9 --- src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json | 4 +++- src/pcm-raw.cpp | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json index 44be66fb..7e696668 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json @@ -66,7 +66,9 @@ "TID": {"Config": 1, "Position": 0, "Width": 6, "DefaultValue": 0}, "State": {"Config": 1, "Position": 17, "Width": 7, "DefaultValue": 0}, "Filter1": {"Config": 2, "Position": 0, "Width": 64, "DefaultValue": 59}, - "OPC": {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0} + "OPC": {"Config": 2, "Position": 20, "Width": 9, "DefaultValue": 0}, + "NC": {"Config": 2, "Position": 30, "Width": 1, "DefaultValue": 0}, + "ISOC": {"Config": 2, "Position": 31, "Width": 1, "DefaultValue": 0} } }, "imc" : { diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index 49097756..c5aa31d6 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -826,6 +826,14 @@ AddEventStatus addEventFromDB(PCM::RawPMUConfigs& curPMUConfigs, string fullEven { setField("OPC", read_number(assignment[1].c_str())); } + else if (assignment.size() == 2 && assignment[0] == "nc") + { + setField("NC", read_number(assignment[1].c_str())); + } + else if (assignment.size() == 2 && assignment[0] == "isoc") + { + setField("ISOC", read_number(assignment[1].c_str())); + } else if (assignment.size() == 2 && assignment[0] == "state") { setField("State", read_number(assignment[1].c_str())); From 018fc001721eb06d18f098d737990341cba8d733 Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Mon, 18 Sep 2023 11:53:22 +0200 Subject: [PATCH 14/22] pcm-raw: added invert and anythread modifiers --- src/pcm-raw.cpp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index c5aa31d6..012f085f 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -756,6 +756,8 @@ AddEventStatus addEventFromDB(PCM::RawPMUConfigs& curPMUConfigs, string fullEven std::regex CounterMaskRegex("c(0x[0-9a-fA-F]+|[[:digit:]]+)"); std::regex UmaskRegex("u(0x[0-9a-fA-F]+|[[:digit:]]+)"); std::regex EdgeDetectRegex("e(0x[0-9a-fA-F]+|[[:digit:]]+)"); + std::regex AnyThreadRegex("amt(0x[0-9a-fA-F]+|[[:digit:]]+)"); + std::regex InvertRegex("i(0x[0-9a-fA-F]+|[[:digit:]]+)"); while (mod != EventTokens.end()) { const auto assignment = split(*mod, '='); @@ -798,6 +800,18 @@ AddEventStatus addEventFromDB(PCM::RawPMUConfigs& curPMUConfigs, string fullEven const std::string Str{ mod->begin() + 1, mod->end() }; setField("EdgeDetect", read_number(Str.c_str())); } + else if (std::regex_match(mod->c_str(), AnyThreadRegex)) + { + // AnyThread modifier + const std::string Str{ mod->begin() + 1, mod->end() }; + setField("AnyThread", read_number(Str.c_str())); + } + else if (std::regex_match(mod->c_str(), InvertRegex)) + { + // Invert modifier + const std::string Str{ mod->begin() + 1, mod->end() }; + setField("Invert", read_number(Str.c_str())); + } else if (std::regex_match(mod->c_str(), UmaskRegex)) { // UMask modifier From 8e3c66d4a29455ea3bfd35d15d24accabb4e495e Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Mon, 18 Sep 2023 12:31:52 +0200 Subject: [PATCH 15/22] pcm-raw: support ha pmu Change-Id: I9227028d12838425e5466e66ca68b1be4e0c8c88 --- .../GenuineIntel-6-4F-1.json | 8 ++++++ src/cpucounters.cpp | 15 +++++++++++ src/cpucounters.h | 19 ++++++++++++++ src/pcm-raw.cpp | 26 +++++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json index 7e696668..c4b4ae66 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json @@ -79,6 +79,14 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} } }, + "ha" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0}, + "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} + } + }, "xpi" : { "__comment" : "this is for UPI LL and QPI LL uncore PMUs", "programmable" : { diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index bf4ec833..627eebfd 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -5574,6 +5574,13 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile uncore->programIMC(events32); } } + else if (type == "ha") + { + for (auto& uncore : serverUncorePMUs) + { + uncore->programHA(events32); + } + } else if (type == "m2m") { for (auto& uncore : serverUncorePMUs) @@ -6532,6 +6539,9 @@ ServerUncoreCounterState PCM::getServerUncoreCounterState(uint32 socket) assert(controller < result.M2MCounter.size()); for (uint32 cnt = 0; cnt < ServerUncoreCounterState::maxCounters; ++cnt) result.M2MCounter[controller][cnt] = serverUncorePMUs[socket]->getM2MCounter(controller, cnt); + assert(controller < result.HACounter.size()); + for (uint32 cnt = 0; cnt < ServerUncoreCounterState::maxCounters; ++cnt) + result.HACounter[controller][cnt] = serverUncorePMUs[socket]->getHACounter(controller, cnt); } serverUncorePMUs[socket]->unfreezeCounters(); } @@ -8583,6 +8593,11 @@ uint64 ServerUncorePMUs::getPMUCounter(std::vector & pmu, const uint3 return result; } +uint64 ServerUncorePMUs::getHACounter(uint32 id, uint32 counter) +{ + return getPMUCounter(haPMUs, id, counter); +} + uint64 ServerUncorePMUs::getMCCounter(uint32 channel, uint32 counter) { return getPMUCounter(imcPMUs, channel, counter); diff --git a/src/cpucounters.h b/src/cpucounters.h index 77d86c57..9d89a356 100644 --- a/src/cpucounters.h +++ b/src/cpucounters.h @@ -510,6 +510,10 @@ class ServerUncorePMUs //! \param box box ID/number //! \param counter counter number uint64 getM2MCounter(uint32 box, uint32 counter); + //! \brief Direct read of HA counter + //! \param box box ID/number + //! \param counter counter number + uint64 getHACounter(uint32 box, uint32 counter); //! \brief Freezes event counting void freezeCounters(); @@ -2877,6 +2881,17 @@ uint64 getM2MCounter(uint32 controller, uint32 counter, const CounterStateType & return after.M2MCounter[controller][counter] - before.M2MCounter[controller][counter]; } +/*! \brief Direct read of HA controller PMU counter (counter meaning depends on the programming: power/performance/etc) + \param counter counter number + \param controller controller number + \param before CPU counter state before the experiment + \param after CPU counter state after the experiment +*/ +template +uint64 getHACounter(uint32 controller, uint32 counter, const CounterStateType & before, const CounterStateType & after) +{ + return after.HACounter[controller][counter] - before.HACounter[controller][counter]; +} /*! \brief Direct read of embedded DRAM memory controller counter (counter meaning depends on the programming: power/performance/etc) \param counter counter number @@ -3168,6 +3183,7 @@ class ServerUncoreCounterState : public UncoreCounterState std::array HBMClocks; std::array, maxChannels> MCCounter; // channel X counter std::array, maxControllers> M2MCounter; // M2M/iMC boxes x counter + std::array, maxControllers> HACounter; // HA boxes x counter std::array, maxChannels> EDCCounter; // EDC controller X counter std::array PCUCounter; std::unordered_map freeRunningCounter; @@ -3201,6 +3217,8 @@ class ServerUncoreCounterState : public UncoreCounterState template friend uint64 getM2MCounter(uint32 controller, uint32 counter, const CounterStateType & before, const CounterStateType & after); template + friend uint64 getHACounter(uint32 controller, uint32 counter, const CounterStateType & before, const CounterStateType & after); + template friend uint64 getEDCCounter(uint32 channel, uint32 counter, const CounterStateType & before, const CounterStateType & after); template friend uint64 getPCUCounter(uint32 counter, const CounterStateType & before, const CounterStateType & after); @@ -3232,6 +3250,7 @@ class ServerUncoreCounterState : public UncoreCounterState HBMClocks{{}}, MCCounter{{}}, M2MCounter{{}}, + HACounter{{}}, EDCCounter{{}}, PCUCounter{{}}, PackageThermalHeadroom(0), diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index 012f085f..87505906 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -1629,6 +1629,14 @@ void printTransposed(const PCM::RawPMUConfigs& curPMUConfigs, [&]() { printUncoreRows([](const uint32 u, const uint32 i, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getM2MCounter(u, i, before, after); }, (uint32)m->getMCPerSocket(), "MC"); }); } + else if (type == "ha") + { + choose(outputType, + [&]() { printUncoreRows(nullptr, (uint32) m->getMCPerSocket(), "HA"); }, + [&]() { printUncoreRows(nullptr, (uint32) m->getMCPerSocket(), type); }, + [&]() { printUncoreRows([](const uint32 u, const uint32 i, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getHACounter(u, i, before, after); }, (uint32)m->getMCPerSocket(), "HA"); + }); + } else if (type == "pcu") { choose(outputType, @@ -1901,6 +1909,24 @@ void print(const PCM::RawPMUConfigs& curPMUConfigs, } } } + else if (type == "ha") + { + for (uint32 s = 0; s < m->getNumSockets(); ++s) + { + for (uint32 mc = 0; mc < m->getMCPerSocket(); ++mc) + { + int i = 0; + for (auto& event : events) + { + choose(outputType, + [s, mc]() { cout << "SKT" << s << "HA" << mc << separator; }, + [&event, &i]() { if (event.second.empty()) cout << "HAEvent" << i << separator; else cout << event.second << separator; }, + [&]() { cout << getHACounter(mc, i, BeforeUncoreState[s], AfterUncoreState[s]) << separator; }); + ++i; + } + } + } + } else if (type == "pcu") { for (uint32 s = 0; s < m->getNumSockets(); ++s) From 00c6490f679f8277827bae307d7f257d8d572476 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Mon, 18 Sep 2023 14:17:00 +0200 Subject: [PATCH 16/22] pcm-raw: allow imc fixed event name change Change-Id: Ia502c28295e74864bc79456545abe08713b27aaa --- src/pcm-raw.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index 87505906..9df95418 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -1614,11 +1614,12 @@ void printTransposed(const PCM::RawPMUConfigs& curPMUConfigs, } else if (type == "imc") { + const std::string fixedEventName = (fixedEvents.empty() == false && fixedEvents[0].second.empty() == false) ? fixedEvents[0].second : "DRAMClocks"; choose(outputType, [&]() { printUncoreRows(nullptr, (uint32) m->getMCChannelsPerSocket(), "CHAN"); }, [&]() { printUncoreRows(nullptr, (uint32) m->getMCChannelsPerSocket(), type); }, [&]() { printUncoreRows([](const uint32 u, const uint32 i, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getMCCounter(u, i, before, after); }, (uint32)m->getMCChannelsPerSocket(), - "DRAMClocks", [](const uint32 u, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getDRAMClocks(u, before, after); }); + fixedEventName, [](const uint32 u, const ServerUncoreCounterState& before, const ServerUncoreCounterState& after) { return getDRAMClocks(u, before, after); }); }); } else if (type == "m2m") From 38d50446cf7f5721dbac43416a52efb55eb9601b Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Tue, 19 Sep 2023 09:16:56 +0200 Subject: [PATCH 17/22] pcm-raw: remove the max number of event restrictions for register events --- src/cpucounters.cpp | 4 ++-- src/pcm-raw.cpp | 4 ++++ src/utils.cpp | 12 ++++++++++++ src/utils.h | 2 +- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 627eebfd..282c031d 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -5541,9 +5541,9 @@ PCM::ErrorCode PCM::program(const RawPMUConfigs& curPMUConfigs_, const bool sile { continue; } - if (events.programmable.size() > ServerUncoreCounterState::maxCounters) + if (events.programmable.size() > ServerUncoreCounterState::maxCounters && isRegisterEvent(type) == false) { - std::cerr << "ERROR: trying to program " << events.programmable.size() << " core PMU counters, which exceeds the max num possible (" << ServerUncoreCounterState::maxCounters << ")."; + std::cerr << "ERROR: trying to program " << events.programmable.size() << " uncore PMU counters, which exceeds the max num possible (" << ServerUncoreCounterState::maxCounters << ")."; return PCM::UnknownError; } uint32 events32[ServerUncoreCounterState::maxCounters] = { 0,0,0,0,0,0,0,0 }; diff --git a/src/pcm-raw.cpp b/src/pcm-raw.cpp index 9df95418..e47fe39a 100644 --- a/src/pcm-raw.cpp +++ b/src/pcm-raw.cpp @@ -132,6 +132,10 @@ enum AddEventStatus bool tooManyEvents(const std::string & pmuName, const int event_pos, const std::string& fullEventStr) { + if (isRegisterEvent(pmuName)) + { + return false; + } PCM* m = PCM::getInstance(); assert(m); const int maxCounters = (pmuName == "core" || pmuName == "atom") ? m->getMaxCustomCoreEvents() : ServerUncoreCounterState::maxCounters; diff --git a/src/utils.cpp b/src/utils.cpp index b8418c18..5bfe3318 100644 --- a/src/utils.cpp +++ b/src/utils.cpp @@ -838,6 +838,18 @@ std::string dos2unix(std::string in) return in; } +bool isRegisterEvent(const std::string & pmu) +{ + if (pmu == "mmio" + || pmu == "pcicfg" + || pmu == "package_msr" + || pmu == "thread_msr") + { + return true; + } + return false; +} + std::string a_title(const std::string &init, const std::string &name) { char begin = init[0]; std::string row = init; diff --git a/src/utils.h b/src/utils.h index 5c810dbc..229f1304 100644 --- a/src/utils.h +++ b/src/utils.h @@ -574,7 +574,7 @@ typedef enum{ }evt_cb_type; std::string dos2unix(std::string in); - +bool isRegisterEvent(const std::string & pmu); std::string a_title (const std::string &init, const std::string &name); std::string a_data (std::string init, struct data d); std::string a_header_footer(std::string init, std::string name); From 1b9d4111a712dad03b08cd818cbcfd2c5377a45f Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Tue, 19 Sep 2023 11:04:09 +0200 Subject: [PATCH 18/22] implement PCM_NO_MAIN_EXCEPTION_HANDLER variable Change-Id: I81a6c19e651480bb00cc3278c86c4470e783e370 --- src/utils.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/utils.h b/src/utils.h index 229f1304..e4779467 100644 --- a/src/utils.h +++ b/src/utils.h @@ -29,10 +29,16 @@ #include #include + +namespace pcm { + std::string safe_getenv(const char* env); +} + #define PCM_MAIN_NOTHROW \ int mainThrows(int argc, char * argv[]); \ int main(int argc, char * argv[]) \ { \ + if (pcm::safe_getenv("PCM_NO_MAIN_EXCEPTION_HANDLER") == std::string("1")) return mainThrows(argc, argv); \ try { \ return mainThrows(argc, argv); \ } catch(const std::runtime_error & e) \ @@ -521,8 +527,6 @@ inline uint64 extract_bits(uint64 myin, uint32 beg, uint32 end) return myll; } -std::string safe_getenv(const char* env); - #ifdef _MSC_VER inline HANDLE openMSRDriver() { From 594ee51d5ac961cf8ad6e57bdefb5dcd09447565 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Tue, 19 Sep 2023 11:11:22 +0200 Subject: [PATCH 19/22] document PCM_NO_MAIN_EXCEPTION_HANDLER Change-Id: I8e6ca96acf31bee1609d8be263b99764c1da308a --- doc/ENVVAR_README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/ENVVAR_README.md b/doc/ENVVAR_README.md index af285553..58acfa7a 100644 --- a/doc/ENVVAR_README.md +++ b/doc/ENVVAR_README.md @@ -9,3 +9,5 @@ `PCM_PRINT_TOPOLOGY=1` : print detailed CPU topology `PCM_KEEP_NMI_WATCHDOG=1` : don't disable NMI watchdog (reducing the core metrics set) + +`PCM_NO_MAIN_EXCEPTION_HANDLER=1` : don't catch exceptions in the main function of pcm tools (a debugging option) From 6613d578c64e90cf2bcfbb464b5a50214a9648be Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 20 Sep 2023 12:07:08 +0200 Subject: [PATCH 20/22] add PCU PMU declaration for BDX Change-Id: I4e130c2a054ce258c57a480e1ebcd3cb8ccc4108 --- src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json index c4b4ae66..6901131a 100644 --- a/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json +++ b/src/PMURegisterDeclarations/GenuineIntel-6-4F-1.json @@ -87,6 +87,13 @@ "Threshold": {"Config": 0, "Position": 24, "Width": 8, "DefaultValue": 0} } }, + "pcu" : { + "programmable" : { + "EventCode": {"Config": 0, "Position": 0, "Width": 8}, + "UMask": {"Config": 0, "Position": 8, "Width": 8}, + "EdgeDetect": {"Config": 0, "Position": 18, "Width": 1, "DefaultValue": 0} + } + }, "xpi" : { "__comment" : "this is for UPI LL and QPI LL uncore PMUs", "programmable" : { From c583d3319a4bdca1866865fbc2e12e8882c2793f Mon Sep 17 00:00:00 2001 From: Roman Dementiev Date: Wed, 20 Sep 2023 13:07:10 +0200 Subject: [PATCH 21/22] throw exception with a message in pcihandle class --- src/pci.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/pci.cpp b/src/pci.cpp index b65fac1f..3afcbbfd 100644 --- a/src/pci.cpp +++ b/src/pci.cpp @@ -580,8 +580,10 @@ void PciHandleMM::readMCFG() if (read_bytes == 0) { ::close(mcfg_handle); - std::cerr << "PCM Error: Cannot read MCFG-table\n"; - throw std::exception(); + const auto msg = "PCM Error: Cannot read MCFG-table"; + std::cerr << msg; + std::cerr << "\n"; + throw std::runtime_error(msg); } const unsigned segments = mcfgHeader.nrecords(); @@ -597,8 +599,10 @@ void PciHandleMM::readMCFG() if (read_bytes == 0) { ::close(mcfg_handle); - std::cerr << "PCM Error: Cannot read MCFG-table (2)\n"; - throw std::exception(); + const auto msg = "PCM Error: Cannot read MCFG-table (2)"; + std::cerr << msg; + std::cerr << "\n"; + throw std::runtime_error(msg); } #ifdef PCM_DEBUG std::cout << "PCM Debug: segment " << std::dec << i << " "; From 2aa27842e2059b3f1a861310bbcb1a2d9463b6a4 Mon Sep 17 00:00:00 2001 From: "Dementiev, Roman" Date: Wed, 20 Sep 2023 13:16:41 +0200 Subject: [PATCH 22/22] catch exception in getMaxNumOfCBoxes to allow the fall-back perf API method to be called Change-Id: I9ae1a831c16576ebae9606991ebb1650b5e39cd8 --- src/cpucounters.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/cpucounters.cpp b/src/cpucounters.cpp index 282c031d..0999998d 100644 --- a/src/cpucounters.cpp +++ b/src/cpucounters.cpp @@ -9016,7 +9016,7 @@ uint32 PCM::getMaxNumOfCBoxes() const switch (cpu_model) { case SPR: - { + try { PciHandleType * h = getDeviceHandle(PCM_INTEL_PCI_VENDOR_ID, 0x325b); if (h) { @@ -9028,6 +9028,10 @@ uint32 PCM::getMaxNumOfCBoxes() const delete h; } } + catch (std::exception& e) + { + std::cerr << "Warning: reading the number of CHA from PCICFG register has failed: " << e.what() << "\n"; + } break; case KNL: case SKX: