.gitlab-ci.yml

# Copyright 2022 Thales Silicon Security
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Yannick Casamatta (yannick.casamatta@thalesgroup.com)

# Please refer to .gitlab-ci/README.md to add jobs

# Project maintainers must define following variables to adapt this CI to their runtime environment (Settings > CI/CD > Variables)
# - SETUP_CI_CVV_BRANCH: master (the main branch of CVA6 repository)

# A git repository named "setup-ci" must be created in the same namespace as cva6 and must contain the following file:
# - 'cva6/core-v-verif-cva6.yml'
#
# This file must at least contain the variables necessary for the execution of
# this pipeline.
# Other elements such as new jobs can be added to overload the associated
# downstream pipeline included in this repository.
# Example can be found in ".gitlab-ci/setup-ci-example/"

include:
  - project: '$CI_PROJECT_NAMESPACE/setup-ci'
    ref: '$SETUP_CI_CVV_BRANCH'
    file: 'cva6/core-v-verif-cva6.yml'

workflow:
  rules:
    - if: $CI_PIPELINE_SOURCE == "schedule"
      variables:
        CI_KIND: verif
    - if: $CI_COMMIT_BRANCH == "master"
      variables:
        CI_KIND: regress
    - if: $CI_COMMIT_BRANCH =~ /.*_PR_.*/
      variables:
        CI_KIND: dev
    - if: $CI_COMMIT_BRANCH =~ /^dev.*/
      variables:
        CI_KIND: dev
    - variables:
        CI_KIND: none

variables:
  GIT_SUBMODULE_STRATEGY: recursive
  DASHBOARD: cva6
  DV_TARGET: cv32a6_embedded

default:
  tags: [$TAGS_RUNNER]
  artifacts:
    when: always
    paths:
      - artifacts/

stages:
  - setup
  - light tests
  - heavy tests
  - backend tests
  - find failures
  - report

.setup_job:
  stage: setup
  variables:
    GIT_SUBMODULE_STRATEGY: none
  rules: &on_dev
    - if: $CI_KIND == "regress"
    - if: $CI_KIND == "verif"
    - if: $CI_KIND == "dev"
    - when: manual
      allow_failure: true

check_env:
  extends:
    - .setup_job
  variables:
    GIT_STRATEGY: none
  script:
    - env
  artifacts:
    paths: []

build_tools:
  extends:
    - .setup_job
  script:
    - git submodule update --init verif/core-v-verif
    - source $SYN_VCS_BASHRC
    # ROOT_PROJECT is used by Spike installer and designates the toplevel of core-v-verif tree.
    - 'export ROOT_PROJECT=$(pwd)'
    # If a local build of Spike is requested, clean up build and installation directories.
    - '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf vendor/riscv/riscv-isa-sim/build'
    - '[ -n "$SPIKE_INSTALL_DIR" -a "$SPIKE_INSTALL_DIR" = "__local__" ] && rm -rf tools/spike'
    # Create default directory corresponding to the artifact path.
    - mkdir -p tools/spike
    # Set up Spike, whether locally built or pre-installed.
    # If initially set to "__local__", SPIKE_INSTALL_DIR will be resolved
    # to an absolute path by the installation script.
    - source verif/regress/install-spike.sh
    # Strip locally built binaries and libraries to reduce artifact size.
    - '[ -f $(pwd)/tools/spike/bin/spike ] && strip $(pwd)/tools/spike/bin/spike* $(pwd)/tools/spike/lib/lib*.*'
    - mkdir -p artifacts/tools/
    - mv tools/spike artifacts/tools/

.fe_smoke_test:
  stage: light tests
  rules: *on_dev
  before_script:
    - git -C verif/core-v-verif fetch --unshallow
    - mkdir -p tools
    - mv artifacts/tools/spike tools
    - rm -rf artifacts/
    - mkdir -p artifacts/{reports,logs}
    - python3 .gitlab-ci/scripts/report_fail.py
    - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC

.simu_after_script: &simu_after_script
  - for i in $(find verif/sim/*/v*_sim -type f \( -name "*.csv" -o -name "*.iss" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
  - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
  - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log

smoke:
  extends:
    - .fe_smoke_test
  variables:
    DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS"
    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations"
    DASHBOARD_SORT_INDEX: 0
    DASHBOARD_JOB_CATEGORY: "Basic"
    SPIKE_TANDEM: 1
  parallel:
    matrix:
      - DV_SIMULATORS:
        - "veri-testharness,spike"
        - "vcs-testharness,spike"
        - "vcs-uvm,spike"
  script:
    - bash verif/regress/smoke-tests.sh
    - !reference [.simu_after_script]

gen_smoke:
  extends:
    - .fe_smoke_test
  variables:
    DASHBOARD_JOB_TITLE: "Smoke Generated test $DV_SIMULATORS"
    DASHBOARD_JOB_DESCRIPTION: "Short generated tests to challenge the CVA6-DV on STEP1 configuration"
    DASHBOARD_SORT_INDEX: 0
    DASHBOARD_JOB_CATEGORY: "Basic"
    DV_SIMULATORS: "vcs-uvm,spike"
  script:
    - bash verif/regress/smoke-gen_tests.sh
    - !reference [.simu_after_script]

coremark:
  extends:
    - .fe_smoke_test
  variables:
    DASHBOARD_JOB_TITLE: "CoreMark"
    DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
    DASHBOARD_SORT_INDEX: 5
    DASHBOARD_JOB_CATEGORY: "Performance"
  script:
    - bash verif/regress/coremark.sh --no-print
    - python3 .gitlab-ci/scripts/report_benchmark.py --coremark verif/sim/out_*/veri-testharness_sim/core_main.*.log

hwconfig:
  extends:
    - .fe_smoke_test
  variables:
    DASHBOARD_JOB_TITLE: "HW config $DV_SIMULATORS $DV_HWCONFIG_OPTS"
    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge target configurations"
    DASHBOARD_SORT_INDEX: 1
    DASHBOARD_JOB_CATEGORY: "Basic"
    DV_SIMULATORS: "veri-testharness,spike"
    DV_HWCONFIG_OPTS: "--default_config=cv32a60x --isa=rv32imac"
  script:
    - source verif/regress/hwconfig_tests.sh
    - python3 .gitlab-ci/scripts/report_pass.py

.synthesis_test:
  stage: heavy tests
  timeout: 2 hours
  before_script:
    - !reference [.fe_smoke_test, before_script]
  rules: &on_dev_rtl
    - if: $CI_KIND == "regress"
    - if: $CI_KIND == "verif"
    - if: $CI_KIND == "dev"
      changes:
        paths:
          - core/**/*
          - corev_apu/**/*
        compare_to: master
    - when: manual
      allow_failure: true

asic-synthesis:
  extends:
    - .synthesis_test
  variables:
    DASHBOARD_JOB_TITLE: "ASIC Synthesis $DV_TARGET"
    DASHBOARD_JOB_DESCRIPTION: "Synthesis indicator with specific Techno"
    DASHBOARD_SORT_INDEX: 5
    DASHBOARD_JOB_CATEGORY: "Synthesis"
    INPUT_DELAY: "0.46"
    OUTPUT_DELAY: "0.11"
    PERIOD: "0.85"
  parallel:
    matrix:
      - DV_TARGET:
        - "cv32a6_embedded"
        - "cv32a65x"
  script:
    - echo $SYNTH_PERIOD
    - echo $INPUT_DELAY
    - echo $OUTPUT_DELAY
    - echo $NAND2_AREA
    - echo $FOUNDRY_PATH
    - echo $PERIOD
    - echo $TECH_NAME
    - echo $DV_TARGET
    - source ./verif/sim/setup-env.sh
    - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
    - make -C pd/synth cva6_synth TARGET="$DV_TARGET"
    - mv pd/synth/cva6_${DV_TARGET}_synth_modified.v artifacts/cva6_${DV_TARGET}_synth_modified.v
    - python3 .gitlab-ci/scripts/report_synth.py pd/synth/cva6_${DV_TARGET}/reports/$PERIOD/cva6_$(echo $TECH_NAME)_synth_area.rpt pd/synth/synthesis_batch.log

fpga-build:
  extends:
    - .synthesis_test
  variables:
    DASHBOARD_JOB_TITLE: "FPGA Build $TARGET"
    DASHBOARD_JOB_DESCRIPTION: "Test of FPGA build flow"
    DASHBOARD_SORT_INDEX: 9
    DASHBOARD_JOB_CATEGORY: "Synthesis"
    TARGET: cv32a60x
  script:
    - source $VIVADO_SETUP
    - source ./verif/sim/setup-env.sh
    - mkdir -p artifacts/logs
    - make fpga target=$TARGET &> artifacts/logs/logfile.log
    - tail -20 artifacts/logs/logfile.log > artifacts/logs/logfile.log.tail
    - rm -f artifacts/logs/logfile.log
    - mkdir -p artifacts/reports
    - mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit
    - python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt artifacts/logs/logfile.log.tail

.regress_test:
  stage: heavy tests
  before_script:
    - !reference [.fe_smoke_test, before_script]
  rules: &on_regress
    - if: $CI_KIND == "regress"
    - if: $CI_KIND == "verif"
    - when: manual
      allow_failure: true

dhrystone:
  extends:
    - .regress_test
  variables:
    DASHBOARD_JOB_TITLE: "Dhrystone"
    DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
    DASHBOARD_SORT_INDEX: 5
    DASHBOARD_JOB_CATEGORY: "Performance"
  script:
    - bash verif/regress/dhrystone.sh
    - python3 .gitlab-ci/scripts/report_benchmark.py --dhrystone verif/sim/out_*/veri-testharness_sim/dhrystone_main.*.log

riscv_arch_test:
  extends:
    - .regress_test
  variables:
    DASHBOARD_JOB_TITLE: "arch_test $DV_TARGET"
    DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
    DASHBOARD_SORT_INDEX: 0
    DASHBOARD_JOB_CATEGORY: "Test suites"
    DV_SIMULATORS: "veri-testharness,spike"
  script: source verif/regress/dv-riscv-arch-test.sh
  after_script: *simu_after_script

compliance:
  extends:
    - .regress_test
  variables:
    DASHBOARD_JOB_TITLE: "Compliance $DV_TARGET"
    DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
    DASHBOARD_SORT_INDEX: 2
    DASHBOARD_JOB_CATEGORY: "Test suites"
    DV_SIMULATORS: "veri-testharness,spike"
  script: source verif/regress/dv-riscv-compliance.sh
  after_script: *simu_after_script

riscv-tests-v:
  extends:
    - .regress_test
  variables:
    DASHBOARD_JOB_TITLE: "Riscv-test $DV_TARGET (virtual)"
    DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)"
    DASHBOARD_SORT_INDEX: 3
    DASHBOARD_JOB_CATEGORY: "Test suites"
    DV_SIMULATORS: "veri-testharness,spike"
    DV_TARGET: cv64a6_imafdc_sv39
    DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
  script: source verif/regress/dv-riscv-tests.sh
  after_script: *simu_after_script

riscv-tests-p:
  extends:
    - .regress_test
  variables:
    DASHBOARD_JOB_TITLE: "Riscv-test $DV_TARGET (physical)"
    DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (physical)"
    DASHBOARD_SORT_INDEX: 4
    DASHBOARD_JOB_CATEGORY: "Test suites"
    DV_SIMULATORS: "veri-testharness,spike"
    DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml"
  script: source verif/regress/dv-riscv-tests.sh
  after_script: *simu_after_script

.verif_test:
  extends:
    - .regress_test
  rules: &on_verif
    - if: $CI_KIND == "verif"
      allow_failure: true
    - when: manual
      allow_failure: true
  timeout: 4h

mmu_sv32_tests:
  extends:
    - .verif_test
  variables:
    DASHBOARD_JOB_TITLE: "mmu_sv32_tests $DV_TARGET"
    DASHBOARD_JOB_DESCRIPTION: "MMU SV32 regression suite"
    DASHBOARD_SORT_INDEX: 0
    DASHBOARD_JOB_CATEGORY: "Test suites"
    DV_SIMULATORS: "veri-testharness,spike"
    DV_TARGET: cv32a60x
  script: source verif/regress/dv-riscv-mmu-sv32-test.sh
  after_script: *simu_after_script

generated_tests:
  extends:
    - .verif_test
  variables:
    DASHBOARD_SORT_INDEX: 11
    DASHBOARD_JOB_CATEGORY: "Code Coverage"
  parallel:
    matrix:
      - list_num: 1
        DASHBOARD_JOB_TITLE: "Generated Random Arithmetic tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic tests using CVA6-DV"
      - list_num: 2
        DASHBOARD_JOB_TITLE: "Generated Hazard Arithmetic tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Hazard register (RAW) Arithmetic tests using CVA6-DV"
      - list_num: 3
        DASHBOARD_JOB_TITLE: "Generated Illegal instruction tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Random Illegal instruction tests using CVA6-DV"
      - list_num: 4
        DASHBOARD_JOB_TITLE: "Generated MMU tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Random MMU tests using CVA6-DV"
      - list_num: 5
        DASHBOARD_JOB_TITLE: "Generated Random Load_store tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Random Load_store tests using CVA6-DV"
      - list_num: 6
        DASHBOARD_JOB_TITLE: "Generated Jump tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic Jump tests using CVA6-DV"
  script:
    - mkdir -p artifacts/coverage
    - source verif/regress/dv-generated-tests.sh
    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
    - mv verif/sim/seedlist.yaml artifacts/coverage
    - python3 .gitlab-ci/scripts/report_pass.py

generated_xif_tests:
  extends:
    - .verif_test
  variables:
    DASHBOARD_SORT_INDEX: 12
    DASHBOARD_JOB_CATEGORY: "Code Coverage"
  parallel:
    matrix:
      - list_num: 1
        DASHBOARD_JOB_TITLE: "Generated Random xif tests"
        DASHBOARD_JOB_DESCRIPTION: "Generate Random tests for cvxif using CVA6-DV"
  script:
    - mkdir -p artifacts/coverage
    - source verif/regress/dv-generated-xif-tests.sh
    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
    - mv verif/sim/seedlist.yaml artifacts/coverage
    - python3 .gitlab-ci/scripts/report_pass.py

directed_isacov-tests:
  extends:
    - .verif_test
  variables:
    DASHBOARD_SORT_INDEX: 13
    DASHBOARD_JOB_CATEGORY: "Functional Coverage"
  parallel:
    matrix:
      - list_num: 0
        DASHBOARD_JOB_TITLE: "Directed tests"
        DASHBOARD_JOB_DESCRIPTION: "Execute directed tests to improve functional coverage of ISA"
  script:
    - mkdir -p artifacts/coverage
    - source verif/regress/dv-generated-tests.sh
    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
    - python3 .gitlab-ci/scripts/report_pass.py

csr_embedded_tests:
  extends:
    - .verif_test
  variables:
    DASHBOARD_JOB_TITLE: "csr_embedded test $DV_TARGET"
    DASHBOARD_JOB_DESCRIPTION: "CSR Test generated using UVM-REG"
    DASHBOARD_SORT_INDEX: 15
    DASHBOARD_JOB_CATEGORY: "CSR tests"
    DV_SIMULATORS: "vcs-uvm"
  script:
    - mkdir -p artifacts/coverage
    - source verif/regress/dv-csr-embedded-tests.sh
    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
    - python3 .gitlab-ci/scripts/report_pass.py

directed_xif-tests:
  extends:
    - .verif_test
  variables:
    DASHBOARD_SORT_INDEX: 16
    DASHBOARD_JOB_CATEGORY: "Functional Coverage"
  parallel:
    matrix:
      - list_num: 0
        DASHBOARD_JOB_TITLE: "Directed tests"
        DASHBOARD_JOB_DESCRIPTION: "Execute directed tests to improve functional coverage of cvxif"
  script:
    - mkdir -p artifacts/coverage
    - source verif/regress/dv-generated-xif-tests.sh
    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
    - python3 .gitlab-ci/scripts/report_pass.py

.backend_test:
  stage: backend tests
  before_script:
    - mkdir -p artifacts/{reports,logs}
    - python3 .gitlab-ci/scripts/report_fail.py

smoke-gate:
  extends:
    - .backend_test
  needs:
    - build_tools
    - asic-synthesis
  variables:
    DASHBOARD_JOB_TITLE: "Smoke Gate $DV_TARGET"
    DASHBOARD_JOB_DESCRIPTION: "Simple test to check netlist from ASIC synthesis"
    DASHBOARD_SORT_INDEX: 6
    DASHBOARD_JOB_CATEGORY: "Post Synthesis"
  script:
    - git -C verif/core-v-verif fetch --unshallow
    - mkdir -p tools
    - mv artifacts/tools/spike tools
    - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
    - echo $LIB_VERILOG
    - echo $FOUNDRY_PATH
    - echo $PERIOD
    - echo $TECH_NAME
    - source ./verif/sim/setup-env.sh
    - source verif/regress/install-riscv-tests.sh
    - mv artifacts/cva6_${DV_TARGET}_synth_modified.v pd/synth/cva6_${DV_TARGET}_synth_modified.v
    - cd verif/sim
    - make vcs_clean_all
    - python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-lw --iss_yaml cva6.yaml --target $DV_TARGET --iss=spike,vcs-gate $DV_OPTS
  after_script: *simu_after_script

fpga-boot:
  extends:
    - .backend_test
  tags: [fpga,shell]
  needs:
    - build_tools
    - fpga-build
  variables:
    DASHBOARD_JOB_TITLE: "FPGA Linux32 Boot "
    DASHBOARD_JOB_DESCRIPTION: "Test of Linux 32 bits boot on FPGA Genesys2"
    DASHBOARD_SORT_INDEX: 10
    DASHBOARD_JOB_CATEGORY: "Synthesis"
  script:
    - source ./verif/sim/setup-env.sh
    - source $VIVADO2022_SETUP
    - mkdir -p corev_apu/fpga/work-fpga
    - mv artifacts/ariane_xilinx_cv32a60x.bit corev_apu/fpga/work-fpga/ariane_xilinx.bit
    - cd corev_apu/fpga/scripts
    - source check_fpga_boot.sh
    - cd -
    - python3 .gitlab-ci/scripts/report_fpga_boot.py corev_apu/fpga/scripts/fpga_boot.rpt

code_coverage-report:
  extends:
    - .backend_test
  needs:
    - generated_tests
    - directed_isacov-tests
    - generated_xif_tests
    - directed_xif-tests
    - csr_embedded_tests
  variables:
    DASHBOARD_JOB_TITLE: "Report merge coverage"
    DASHBOARD_JOB_DESCRIPTION: "Report merge coverage of generated tests"
    DASHBOARD_SORT_INDEX: 14
    DASHBOARD_JOB_CATEGORY: "Code Coverage"
  script:
    - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
    - mkdir -p artifacts/cov_reports/
    - mkdir -p verif/sim/vcs_results/default/vcs.d
    - mv artifacts/coverage/simv.vdb verif/sim/vcs_results/default/vcs.d/
    - mv artifacts/coverage/seedlist.yaml verif/sim/seedlist.yaml
    - make -C verif/sim generate_cov_dash
    - mv verif/sim/urgReport artifacts/cov_reports/
    - python3 .gitlab-ci/scripts/report_coverage.py artifacts/cov_reports/urgReport/hierarchy.txt

check gitlab jobs status:
  stage: find failures
  rules:
    - if: $DASHBOARD_URL && $CI_KIND != "none"
      when: on_failure
  variables:
    DASHBOARD_JOB_TITLE: "Environment check"
    DASHBOARD_JOB_DESCRIPTION: "Detect environment issues"
    DASHBOARD_SORT_INDEX: 0
    DASHBOARD_JOB_CATEGORY: "Environment"
    GIT_SUBMODULE_STRATEGY: none
  script:
    - rm -rf artifacts/
    - mkdir -p artifacts/reports
    - python3 .gitlab-ci/scripts/report_envfail.py

merge reports:
  stage: report
  variables:
    GIT_SUBMODULE_STRATEGY: none
  rules:
    - if: $DASHBOARD_URL && $CI_KIND != "none"
      when: always
  script:
    - mkdir -p artifacts/reports
    - ls -al artifacts/reports
    - python3 .gitlab-ci/scripts/merge_job_reports.py artifacts/reports pipeline_report_$CI_PIPELINE_ID.yml
  artifacts:
    when: always
    paths:
      - "artifacts/reports/pipeline_report_$CI_PIPELINE_ID.yml"