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basys2.ucf
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basys2.ucf
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NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK
# Pin assignment for LEDs
NET "Led<7>" LOC = "G1" ; # Bank = 3, Signal name = LD7
NET "Led<6>" LOC = "P4" ; # Bank = 2, Signal name = LD6
NET "Led<5>" LOC = "N4" ; # Bank = 2, Signal name = LD5
NET "Led<4>" LOC = "N5" ; # Bank = 2, Signal name = LD4
NET "Led<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3
NET "Led<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2
NET "Led<1>" LOC = "M11" ; # Bank = 2, Signal name = LD1
NET "Led<0>" LOC = "M5" ; # Bank = 2, Signal name = LD0
# Pin assignment for 7-segment display
NET "seg<0>" LOC = "L14"; # Bank = 1, Signal name = CA
NET "seg<1>" LOC = "H12"; # Bank = 1, Signal name = CB
NET "seg<2>" LOC = "N14"; # Bank = 1, Signal name = CC
NET "seg<3>" LOC = "N11"; # Bank = 2, Signal name = CD
NET "seg<4>" LOC = "P12"; # Bank = 2, Signal name = CE
NET "seg<5>" LOC = "L13"; # Bank = 1, Signal name = CF
NET "seg<6>" LOC = "M12"; # Bank = 1, Signal name = CG
NET "seg<7>" LOC = "N13"; # Bank = 1, Signal name = DP
NET "an<0>" LOC = "F12"; # Bank = 1, Signal name = AN0
NET "an<1>" LOC = "J12"; # Bank = 1, Signal name = AN1
NET "an<2>" LOC = "M13"; # Bank = 1, Signal name = AN2
NET "an<3>" LOC = "K14"; # Bank = 1, Signal name = AN3
# Pin assignment for SWs
#NET "sw<7>" LOC = "N3"; # Bank = 2, Signal name = SW7 # This one is currently unused
NET "sw<6>" LOC = "E2"; # Bank = 3, Signal name = SW6
NET "sw<5>" LOC = "F3"; # Bank = 3, Signal name = SW5
NET "sw<4>" LOC = "G3"; # Bank = 3, Signal name = SW4
NET "sw<3>" LOC = "B4"; # Bank = 3, Signal name = SW3
NET "sw<2>" LOC = "K3"; # Bank = 3, Signal name = SW2
NET "sw<1>" LOC = "L3"; # Bank = 3, Signal name = SW1
NET "sw<0>" LOC = "P11"; # Bank = 2, Signal name = SW0
NET "btn<3>" LOC = "A7"; # Bank = 1, Signal name = BTN3
NET "btn<2>" LOC = "M4"; # Bank = 0, Signal name = BTN2
NET "btn<1>" LOC = "C11"; # Bank = 2, Signal name = BTN1
NET "btn<0>" LOC = "G12"; # Bank = 0, Signal name = BTN0
# Pin assignment for VGA
NET "HSYNC" LOC = "J14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = HSYNC
NET "VSYNC" LOC = "K13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = VSYNC
NET "VOut<7>" LOC = "F13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = RED2
NET "VOut<6>" LOC = "D13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = RED1
NET "VOut<5>" LOC = "C14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = RED0
NET "VOut<4>" LOC = "G14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = GRN2
NET "VOut<3>" LOC = "G13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = GRN1
NET "VOut<2>" LOC = "F14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = GRN0
NET "VOut<1>" LOC = "J13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = BLU2
NET "VOut<0>" LOC = "H13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = BLU1
# Pin assignments for oscilloscope inputs
NET "red" LOC = "C6";
NET "green" LOC = "B6";
NET "blue" LOC = "C5";
#Created by Constraints Editor (xc3s100e-cp132-5) - 2011/04/25
NET "uclk" TNM_NET = uclk;
TIMESPEC TS_uclk = PERIOD "uclk" 32 MHz HIGH 50%;