From 58d4c0911c8309d4540482705d4915b5e854cb1e Mon Sep 17 00:00:00 2001 From: Marcin Osowski Date: Wed, 8 Jun 2011 14:47:53 +0200 Subject: [PATCH] First version of an FPGA binary oscilloscope --- .gitignore | 5 + Makefile | 13 + README | 6 + bit/oscilloscope.bit | Bin 0 -> 72782 bytes ipcore_dir/blk_mem_gen_ds512.pdf | Bin 0 -> 41717 bytes ipcore_dir/blk_mem_gen_readme.txt | 209 + ipcore_dir/char_rom_memory.asy | 17 + ipcore_dir/char_rom_memory.gise | 32 + ipcore_dir/char_rom_memory.mif | 16384 +++++++++++++++++ ipcore_dir/char_rom_memory.ncf | 0 ipcore_dir/char_rom_memory.ngc | 3 + ipcore_dir/char_rom_memory.vhd | 134 + ipcore_dir/char_rom_memory.vho | 64 + ipcore_dir/char_rom_memory.xco | 101 + ipcore_dir/char_rom_memory.xise | 72 + ipcore_dir/char_rom_memory_flist.txt | 14 + ipcore_dir/char_rom_memory_xmdf.tcl | 80 + ipcore_dir/clock_108mhz.vhd | 90 + ipcore_dir/clock_108mhz.xaw | 3 + ipcore_dir/clock_108mhz_arwz.ucf | 17 + ipcore_dir/clock_108mhz_flist.txt | 2 + ipcore_dir/coregen.cgc | 325 + ipcore_dir/coregen.cgp | 9 + ipcore_dir/edit_char_rom_memory.tcl | 37 + ipcore_dir/trace_memory.asy | 37 + ipcore_dir/trace_memory.gise | 32 + ipcore_dir/trace_memory.ncf | 0 ipcore_dir/trace_memory.ngc | 3 + ipcore_dir/trace_memory.vhd | 149 + ipcore_dir/trace_memory.vho | 74 + ipcore_dir/trace_memory.xco | 101 + ipcore_dir/trace_memory.xise | 72 + ipcore_dir/trace_memory_flist.txt | 13 + ipcore_dir/trace_memory_xmdf.tcl | 76 + oscilloscope.xise | 511 + project/oscilloscope.svg | 1766 ++ project/oscilloscope.vpp | Bin 0 -> 309240 bytes project/reading_resolutions.ods | Bin 0 -> 13088 bytes project/reading_resolutions.pdf | Bin 0 -> 15660 bytes project/screen-utilization-plan.png | Bin 0 -> 13466 bytes project/screen-utilization-plan.xcf | Bin 0 -> 197098 bytes src/basys2.ucf | 58 + src/bits_aggregator.vhd | 110 + src/char_rom_mux.vhd | 55 + src/clock_divider.vhd | 38 + src/debouncer.vhd | 38 + src/display.vhd | 224 + src/main.vhd | 281 + src/n_cycles_delayer.vhd | 47 + src/one_cycle_delayer.vhd | 36 + src/pixgen_mux.vhd | 42 + src/reader.vhd | 150 + src/rom_data/8x16_font_ASCII_DOS_437.coe | 16386 ++++++++++++++++++ src/rom_data/8x16_font_ASCII_DOS_437.gif | Bin 0 -> 1426 bytes src/rom_data/img2coe.py | 20 + src/screen_position_gen.vhd | 125 + src/settings.vhd | 82 + src/settings_pixgen.vhd | 240 + src/single_debouncer.vhd | 45 + src/tests/test_bits_aggregator.vhd | 171 + src/tests/test_char_rom_mux.vhd | 160 + src/tests/test_clock_divider.vhd | 97 + src/tests/test_compiler_error.vhd | 28 + src/tests/test_debouncer.vhd | 132 + src/tests/test_n_cycles_delayer.vhd | 114 + src/tests/test_oscilloscope_display.vhd | 141 + src/tests/test_reader.vhd | 178 + src/tests/test_screen_position_gen.vhd | 152 + src/tests/test_single_debouncer.vhd | 126 + src/tests/test_trace_memory.vhd | 130 + src/tests/test_trace_pixgen.vhd | 185 + src/tests/test_trigger.vhd | 184 + src/tests/test_types.vhd | 31 + src/tests/test_vga_controller_1280_1024.vhd | 101 + src/time_base_pixgen.vhd | 75 + src/trace_pixgen.vhd | 162 + src/trigger.vhd | 106 + src/types.vhd | 70 + src/vga_controller_1280_1024.vhd | 162 + 79 files changed, 40933 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 README create mode 100644 bit/oscilloscope.bit create mode 100644 ipcore_dir/blk_mem_gen_ds512.pdf create mode 100644 ipcore_dir/blk_mem_gen_readme.txt create mode 100644 ipcore_dir/char_rom_memory.asy create mode 100644 ipcore_dir/char_rom_memory.gise create mode 100644 ipcore_dir/char_rom_memory.mif create mode 100644 ipcore_dir/char_rom_memory.ncf create mode 100644 ipcore_dir/char_rom_memory.ngc create mode 100644 ipcore_dir/char_rom_memory.vhd create mode 100644 ipcore_dir/char_rom_memory.vho create mode 100644 ipcore_dir/char_rom_memory.xco create mode 100644 ipcore_dir/char_rom_memory.xise create mode 100644 ipcore_dir/char_rom_memory_flist.txt create mode 100644 ipcore_dir/char_rom_memory_xmdf.tcl create mode 100644 ipcore_dir/clock_108mhz.vhd create mode 100644 ipcore_dir/clock_108mhz.xaw create mode 100644 ipcore_dir/clock_108mhz_arwz.ucf create mode 100644 ipcore_dir/clock_108mhz_flist.txt create mode 100644 ipcore_dir/coregen.cgc create mode 100644 ipcore_dir/coregen.cgp create mode 100644 ipcore_dir/edit_char_rom_memory.tcl create mode 100644 ipcore_dir/trace_memory.asy create mode 100644 ipcore_dir/trace_memory.gise create mode 100644 ipcore_dir/trace_memory.ncf create mode 100644 ipcore_dir/trace_memory.ngc create mode 100644 ipcore_dir/trace_memory.vhd create mode 100644 ipcore_dir/trace_memory.vho create mode 100644 ipcore_dir/trace_memory.xco create mode 100644 ipcore_dir/trace_memory.xise create mode 100644 ipcore_dir/trace_memory_flist.txt create mode 100644 ipcore_dir/trace_memory_xmdf.tcl create mode 100644 oscilloscope.xise create mode 100644 project/oscilloscope.svg create mode 100644 project/oscilloscope.vpp create mode 100644 project/reading_resolutions.ods create mode 100644 project/reading_resolutions.pdf create mode 100644 project/screen-utilization-plan.png create mode 100644 project/screen-utilization-plan.xcf create mode 100644 src/basys2.ucf create mode 100644 src/bits_aggregator.vhd create mode 100644 src/char_rom_mux.vhd create mode 100644 src/clock_divider.vhd create mode 100644 src/debouncer.vhd create mode 100644 src/display.vhd create mode 100644 src/main.vhd create mode 100644 src/n_cycles_delayer.vhd create mode 100644 src/one_cycle_delayer.vhd create mode 100644 src/pixgen_mux.vhd create mode 100644 src/reader.vhd create mode 100644 src/rom_data/8x16_font_ASCII_DOS_437.coe create mode 100644 src/rom_data/8x16_font_ASCII_DOS_437.gif create mode 100755 src/rom_data/img2coe.py create mode 100644 src/screen_position_gen.vhd create mode 100644 src/settings.vhd create mode 100644 src/settings_pixgen.vhd create mode 100644 src/single_debouncer.vhd create mode 100644 src/tests/test_bits_aggregator.vhd create mode 100644 src/tests/test_char_rom_mux.vhd create mode 100644 src/tests/test_clock_divider.vhd create mode 100644 src/tests/test_compiler_error.vhd create mode 100644 src/tests/test_debouncer.vhd create mode 100644 src/tests/test_n_cycles_delayer.vhd create mode 100644 src/tests/test_oscilloscope_display.vhd create mode 100644 src/tests/test_reader.vhd create mode 100644 src/tests/test_screen_position_gen.vhd create mode 100644 src/tests/test_single_debouncer.vhd create mode 100644 src/tests/test_trace_memory.vhd create mode 100644 src/tests/test_trace_pixgen.vhd create mode 100644 src/tests/test_trigger.vhd create mode 100644 src/tests/test_types.vhd create mode 100644 src/tests/test_vga_controller_1280_1024.vhd create mode 100644 src/time_base_pixgen.vhd create mode 100644 src/trace_pixgen.vhd create mode 100644 src/trigger.vhd create mode 100644 src/types.vhd create mode 100644 src/vga_controller_1280_1024.vhd diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..177910f --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +*~ +.*.swp +work/ +_xmsgs/ +iseconfig/ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..b518662 --- /dev/null +++ b/Makefile @@ -0,0 +1,13 @@ +# Device 0: XC3S100E - FPGA (Device ID: f5045093) +# Device 1: XCF02S - PROM (Device ID: 11c10093) +DEVICE_NUM=0 + +bit/oscilloscope.bit: + cp work/oscilloscope.bit bit/ + +up: bit/oscilloscope.bit + djtgcfg prog \ + -d Basys2 \ + -i $(DEVICE_NUM) \ + --file bit/oscilloscope.bit + diff --git a/README b/README new file mode 100644 index 0000000..93e6ae6 --- /dev/null +++ b/README @@ -0,0 +1,6 @@ +An FPGA-based binary oscilloscope for 1280x1024 @ 60hz VGA monitor. + +Target device: Basys2, Spartan3E 100K + +In order to upload programming file to Basys2 device: + o make up diff --git a/bit/oscilloscope.bit b/bit/oscilloscope.bit new file mode 100644 index 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+-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2011 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file char_rom_memory.vhd when simulating +-- the core, char_rom_memory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY char_rom_memory IS + PORT ( + clka : IN STD_LOGIC; + addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END char_rom_memory; + +ARCHITECTURE char_rom_memory_a OF char_rom_memory IS +-- synthesis translate_off +COMPONENT wrapped_char_rom_memory + PORT ( + clka : IN STD_LOGIC; + addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_char_rom_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral) + GENERIC MAP ( + c_addra_width => 14, + c_addrb_width => 14, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_family => "spartan3", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "char_rom_memory.mif", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 1, + c_mem_type => 3, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 16384, + c_read_depth_b => 16384, + c_read_width_a => 1, + c_read_width_b => 1, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 16384, + c_write_depth_b => 16384, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 1, + c_write_width_b => 1, + c_xdevicefamily => "spartan3e" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_char_rom_memory + PORT MAP ( + clka => clka, + addra => addra, + douta => douta + ); +-- synthesis translate_on + +END char_rom_memory_a; diff --git a/ipcore_dir/char_rom_memory.vho b/ipcore_dir/char_rom_memory.vho new file mode 100644 index 0000000..782da7a --- /dev/null +++ b/ipcore_dir/char_rom_memory.vho @@ -0,0 +1,64 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2011 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- + +-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + +-- Interfaces: +-- AXI4_SLAVE_S_AXI +-- AXILite_SLAVE_S_AXI + +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT char_rom_memory + PORT ( + clka : IN STD_LOGIC; + addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : char_rom_memory + PORT MAP ( + clka => clka, + addra => addra, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file char_rom_memory.vhd when simulating +-- the core, char_rom_memory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/ipcore_dir/char_rom_memory.xco b/ipcore_dir/char_rom_memory.xco new file mode 100644 index 0000000..6b147ee --- /dev/null +++ b/ipcore_dir/char_rom_memory.xco @@ -0,0 +1,101 @@ +############################################################## +# +# Xilinx Core Generator version 13.1 +# Date: Sat May 28 17:08:51 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s100e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = cp132 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=/home/xiadz/prog/fpga/oscilloscope/rom_data/8x16_font_ASCII_DOS_437.coe +CSET collision_warnings=ALL +CSET component_name=char_rom_memory +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=true +CSET memory_type=Single_Port_ROM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=0 +CSET port_b_clock=0 +CSET port_b_enable_rate=0 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=1 +CSET read_width_b=1 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=16384 +CSET write_width_a=1 +CSET write_width_b=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-02-03T22:20:43.000Z +# END Extra information +GENERATE +# CRC: 6cb9954b diff --git a/ipcore_dir/char_rom_memory.xise b/ipcore_dir/char_rom_memory.xise new file mode 100644 index 0000000..eafc770 --- /dev/null +++ b/ipcore_dir/char_rom_memory.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/char_rom_memory_flist.txt b/ipcore_dir/char_rom_memory_flist.txt new file mode 100644 index 0000000..823a691 --- /dev/null +++ b/ipcore_dir/char_rom_memory_flist.txt @@ -0,0 +1,14 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +blk_mem_gen_ds512.pdf +blk_mem_gen_readme.txt +char_rom_memory.asy +char_rom_memory.gise +char_rom_memory.mif +char_rom_memory.ngc +char_rom_memory.vhd +char_rom_memory.vho +char_rom_memory.xco +char_rom_memory.xise +char_rom_memory_flist.txt +char_rom_memory_xmdf.tcl diff --git a/ipcore_dir/char_rom_memory_xmdf.tcl b/ipcore_dir/char_rom_memory_xmdf.tcl new file mode 100644 index 0000000..0dcb7c0 --- /dev/null +++ b/ipcore_dir/char_rom_memory_xmdf.tcl @@ -0,0 +1,80 @@ +# The package naming convention is _xmdf +package provide char_rom_memory_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::char_rom_memory_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::char_rom_memory_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name char_rom_memory +} +# ::char_rom_memory_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::char_rom_memory_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory.mif +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path char_rom_memory_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module char_rom_memory +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/ipcore_dir/clock_108mhz.vhd b/ipcore_dir/clock_108mhz.vhd new file mode 100644 index 0000000..60bcea7 --- /dev/null +++ b/ipcore_dir/clock_108mhz.vhd @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : clock_108mhz.vhd +-- /___/ /\ Timestamp : 04/20/2011 20:13:56 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /home/xiadz/prog/fpga/oscilloscope/ipcore_dir/./clock_108mhz.xaw /home/xiadz/prog/fpga/oscilloscope/ipcore_dir/./clock_108mhz +--Design Name: clock_108mhz +--Device: xc3s100e-5cp132 +-- +-- Module clock_108mhz +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.11 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.01 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity clock_108mhz is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end clock_108mhz; + +architecture BEHAVIORAL of clock_108mhz is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 13, + CLKFX_MULTIPLY => 28, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + diff --git a/ipcore_dir/clock_108mhz.xaw b/ipcore_dir/clock_108mhz.xaw new file mode 100644 index 0000000..d015cb3 --- /dev/null +++ b/ipcore_dir/clock_108mhz.xaw @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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4b=;h1v;j50;3x915=>j1/:h4:3:p74<72;q68>4=f:?06?343ty>m7>51z?77?3>3-4}r1a>5<6s49268=4$7g916=z{:?1<7?t=20925=#>l0=<6s|3`83>5}#>l0=<6srn3694?7|ug8>6=4>{|l12?6=9rwe>:4?:0y~j7>=83;pqc<6:182xh5i3:1=vsr}|BCG~552?;9iho?6|BCF~6zHIZpqMN \ No newline at end of file diff --git a/ipcore_dir/clock_108mhz_arwz.ucf b/ipcore_dir/clock_108mhz_arwz.ucf new file mode 100644 index 0000000..b1a302c --- /dev/null +++ b/ipcore_dir/clock_108mhz_arwz.ucf @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 13; +INST DCM_SP_INST CLKFX_MULTIPLY = 28; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 20.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; diff --git a/ipcore_dir/clock_108mhz_flist.txt b/ipcore_dir/clock_108mhz_flist.txt new file mode 100644 index 0000000..25da5f9 --- /dev/null +++ b/ipcore_dir/clock_108mhz_flist.txt @@ -0,0 +1,2 @@ +# Output products list for +clock_108mhz_flist.txt diff --git a/ipcore_dir/coregen.cgc b/ipcore_dir/coregen.cgc new file mode 100644 index 0000000..5a63fea --- /dev/null +++ b/ipcore_dir/coregen.cgc @@ -0,0 +1,325 @@ + + + xilinx.com + project + coregen + 1.0 + + + char_rom_memory + + + char_rom_memory + Native + AXI4_Full + Memory_Slave + false + 4 + Single_Port_ROM + No_ECC + false + false + false + Single_Bit_Error_Injection + false + 9 + Minimum_Area + 8kx2 + false + 1 + 16384 + 1 + WRITE_FIRST + Always_Enabled + 1 + 1 + WRITE_FIRST + Always_Enabled + false + false + false + false + false + false + false + false + 0 + true + /home/xiadz/prog/fpga/oscilloscope/rom_data/8x16_font_ASCII_DOS_437.coe + false + 0 + false + false + CE + 0 + false + false + CE + 0 + SYNC + false + 100 + 0 + 0 + 0 + 100 + 0 + ALL + false + false + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc3s100e + spartan3e + cp132 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2011-02-03T22:20:43.000Z + + + + + + trace_memory + + + trace_memory + Native + AXI4_Full + Memory_Slave + false + 4 + Simple_Dual_Port_RAM + No_ECC + false + false + false + Single_Bit_Error_Injection + false + 9 + Minimum_Area + 8kx2 + true + 9 + 5974 + 9 + WRITE_FIRST + Always_Enabled + 9 + 9 + WRITE_FIRST + Always_Enabled + false + false + false + false + false + false + false + false + 0 + false + no_coe_file_loaded + true + 0 + false + false + CE + 0 + true + false + CE + 0 + SYNC + false + 100 + 50 + 100 + 0 + 100 + 100 + ALL + false + false + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc3s100e + spartan3e + cp132 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + 2011-02-03T22:20:43.000Z + + + + + + clock_100mhz + + + clock_100mhz + /home/xiadz/prog/fpga/oscilloscope/ipcore_dir/clock_100mhz.xaw + + + + + 0 + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc3s100e + spartan3e + cp132 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + + + clock_108mhz + + + clock_108mhz + /home/xiadz/prog/fpga/oscilloscope/ipcore_dir/clock_108mhz.xaw + + + + + 0 + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc3s100e + spartan3e + cp132 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + + + + + + coregen + ./ + ./tmp/ + ./tmp/_cg + + + xc3s100e + spartan3e + cp132 + -5 + + + BusFormatAngleBracketNotRipped + VHDL + true + Other + false + false + false + Ngc + false + + + Behavioral + VHDL + false + + + + diff --git a/ipcore_dir/coregen.cgp b/ipcore_dir/coregen.cgp new file mode 100644 index 0000000..2f62ff1 --- /dev/null +++ b/ipcore_dir/coregen.cgp @@ -0,0 +1,9 @@ +SET busformat = BusFormatAngleBracketNotRipped +SET designentry = VHDL +SET device = xc3s100e +SET devicefamily = spartan3e +SET flowvendor = Other +SET package = cp132 +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true diff --git a/ipcore_dir/edit_char_rom_memory.tcl b/ipcore_dir/edit_char_rom_memory.tcl new file mode 100644 index 0000000..f0c3d89 --- /dev/null +++ b/ipcore_dir/edit_char_rom_memory.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "char_rom_memory" xc3s100e-5cp132 VHDL_and_Verilog ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/ipcore_dir/trace_memory.asy b/ipcore_dir/trace_memory.asy new file mode 100644 index 0000000..633a714 --- /dev/null +++ b/ipcore_dir/trace_memory.asy @@ -0,0 +1,37 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 trace_memory +RECTANGLE Normal 32 32 544 1376 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[12:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[8:0] +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[0:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName addrb[12:0] +PINATTR Polarity IN +LINE Normal 0 592 32 592 +PIN 0 592 LEFT 36 +PINATTR PinName rstb +PINATTR Polarity IN +LINE Normal 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName clkb +PINATTR Polarity IN +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName doutb[8:0] +PINATTR Polarity OUT + diff --git a/ipcore_dir/trace_memory.gise b/ipcore_dir/trace_memory.gise new file mode 100644 index 0000000..591878a --- /dev/null +++ b/ipcore_dir/trace_memory.gise @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + diff --git a/ipcore_dir/trace_memory.ncf b/ipcore_dir/trace_memory.ncf new file mode 100644 index 0000000..e69de29 diff --git a/ipcore_dir/trace_memory.ngc b/ipcore_dir/trace_memory.ngc new file mode 100644 index 0000000..587a1f7 --- /dev/null +++ b/ipcore_dir/trace_memory.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/ipcore_dir/trace_memory.vhd b/ipcore_dir/trace_memory.vhd new file mode 100644 index 0000000..9356347 --- /dev/null +++ b/ipcore_dir/trace_memory.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2011 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file trace_memory.vhd when simulating +-- the core, trace_memory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY trace_memory IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + clkb : IN STD_LOGIC; + rstb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) + ); +END trace_memory; + +ARCHITECTURE trace_memory_a OF trace_memory IS +-- synthesis translate_off +COMPONENT wrapped_trace_memory + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + clkb : IN STD_LOGIC; + rstb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_trace_memory USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral) + GENERIC MAP ( + c_addra_width => 13, + c_addrb_width => 13, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 1, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_family => "spartan3", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 1, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 5974, + c_read_depth_b => 5974, + c_read_width_a => 9, + c_read_width_b => 9, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 1, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 5974, + c_write_depth_b => 5974, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 9, + c_write_width_b => 9, + c_xdevicefamily => "spartan3e" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_trace_memory + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + rstb => rstb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END trace_memory_a; diff --git a/ipcore_dir/trace_memory.vho b/ipcore_dir/trace_memory.vho new file mode 100644 index 0000000..ec1f1d3 --- /dev/null +++ b/ipcore_dir/trace_memory.vho @@ -0,0 +1,74 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2011 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- + +-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. + +-- Interfaces: +-- AXI4_SLAVE_S_AXI +-- AXILite_SLAVE_S_AXI + +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT trace_memory + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + clkb : IN STD_LOGIC; + rstb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : trace_memory + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + rstb => rstb, + addrb => addrb, + doutb => doutb + ); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file trace_memory.vhd when simulating +-- the core, trace_memory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/ipcore_dir/trace_memory.xco b/ipcore_dir/trace_memory.xco new file mode 100644 index 0000000..a4354a7 --- /dev/null +++ b/ipcore_dir/trace_memory.xco @@ -0,0 +1,101 @@ +############################################################## +# +# Xilinx Core Generator version 13.1 +# Date: Tue May 10 18:53:57 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc3s100e +SET devicefamily = spartan3e +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = cp132 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=trace_memory +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=true +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=9 +CSET read_width_b=9 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=true +CSET write_depth_a=5974 +CSET write_width_a=9 +CSET write_width_b=9 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-02-03T22:20:43.000Z +# END Extra information +GENERATE +# CRC: 11dcdb2a diff --git a/ipcore_dir/trace_memory.xise b/ipcore_dir/trace_memory.xise new file mode 100644 index 0000000..c8ad50e --- /dev/null +++ b/ipcore_dir/trace_memory.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ipcore_dir/trace_memory_flist.txt b/ipcore_dir/trace_memory_flist.txt new file mode 100644 index 0000000..1cbb4bb --- /dev/null +++ b/ipcore_dir/trace_memory_flist.txt @@ -0,0 +1,13 @@ +# Output products list for +_xmsgs/pn_parser.xmsgs +blk_mem_gen_ds512.pdf +blk_mem_gen_readme.txt +trace_memory.asy +trace_memory.gise +trace_memory.ngc +trace_memory.vhd +trace_memory.vho +trace_memory.xco +trace_memory.xise +trace_memory_flist.txt +trace_memory_xmdf.tcl diff --git a/ipcore_dir/trace_memory_xmdf.tcl b/ipcore_dir/trace_memory_xmdf.tcl new file mode 100644 index 0000000..3e42dbd --- /dev/null +++ b/ipcore_dir/trace_memory_xmdf.tcl @@ -0,0 +1,76 @@ +# The package naming convention is _xmdf +package provide trace_memory_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::trace_memory_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::trace_memory_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name trace_memory +} +# ::trace_memory_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::trace_memory_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type text +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path trace_memory.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path trace_memory.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path trace_memory.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path trace_memory.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path trace_memory.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path trace_memory_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module trace_memory +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/oscilloscope.xise b/oscilloscope.xise new file mode 100644 index 0000000..037fff1 --- /dev/null +++ b/oscilloscope.xise @@ -0,0 +1,511 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/project/oscilloscope.svg b/project/oscilloscope.svg new file mode 100644 index 0000000..91a8d56 --- /dev/null +++ b/project/oscilloscope.svg @@ -0,0 +1,1766 @@ + + +board_inputssettings (S)reader (S)mem_interface(S)oscilloscope_displayboard_outputsD flip-flop (S)input_signals_3_delayer (triple D flip-flop) (S^3)btn_sw_3_delayer (triple D flip-flop) (S)trigger (S)D flip-flop (S)bits_aggregator (S)btn_sw_debouncers (S)vga_controller_1280_1024 (S)screen_position_gen (S)trace_pixgen (S^2)time_base_pixgen (S^2)settings_pixgen (S^2)char_rom_muxchar_rom_memory (S)pixgen_mux (S)Double D flip-flop (S^2)D flip-flop (S)Quadruple D flip-flop (S^4)A project of three input oscilloscope for 1280x1024@60hz VGA monitor. (C) 2011 Osowski Marcin FPGA @ MIMUWTarget device: Basys2, Spartan3E-100 FPGA Note: (S) in entity title indicates that this entity introduces a one clock cycle delay, (S^2) - two clock cycles etc. Screen utilization plan:  o Screen consists of 16 segments, numbered from 0 to 15   o Each segment is 64 pixels high and 1280 pixels wide   o There are 14 segments for showing trace and 2 segments for settings+-----------------+ |                 | Segment 0 (first trace segment) +-----------------+ |                 | Segment 1 +-----------------+    .............. +-----------------+ |                 | Segment 13 (last trace segment) +-----------------+ |                 | Segment 14 (first settings segment) +-----------------+ |                 | Segment 15 (second settings segment) +-----------------+   o Each segment consists of 4 subsegments   o Each trace segment has:      x three subsegments for trace printing - for red, green and blue signals      x one subsegment for time base indication   o Settings segment has one line of text in each subsegment.       So it has 8 lines of text availableUsed I/Os:   o C6 - red signal   o B6 - green signal   o C5 - blue signal   o SW7 - UNUSED   o SW6 - red enable switch   o SW5 - green enable switch   o SW4 - blue enable switch   o SW3, SW2, SW1, SW0 - time resolution switches   o BTN3 - start/stop button   o BTN2 - trigger event choose button   o BTN1 - behaviour after complete reading   o BTN0 - resetscreen_segment,screen_columnactive_pixgen_sourcetrigger_btnbtn_debounced,sw_debounceddoutbportBaddrbdoutwea, addra,dinaflush_and_return_to_zerowrite_enableoverflow_indicatorQis_reading_activered_after_trigger,green_after_trigger,blue_after_triggertrigger_event, red_enable,green_enable,blue_enable,continue_after_readingtime_resolutionQhsync, vsyncbtn_3_delayed,sw_3_delayedred_3_delayed,green_3_delayed,blue_3_delayedQQvoutvoutvoutvoutvoutQaddrchar_pixelchar_pixelchar_pixelcharcharsegment, segment_change, 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z;6s3~0=5I5P|*`}0H*;i1q=Y*4)_${JAnID^kgSsK41mlRe(1DJ^=U%;AeoxRkU+9 zU@71dKtJF{z$XB=1MXANt_V;EJR5Ko;B|oa1HKISDd15RJv9rk1n?rjYXENrd>rsC zz`ZKktpLXX&IMcv*bI0d;7foX10GhPWzRz!Ctqan$nwmjPY{cn#oMz*fLJ0UrQ-9PkCe*8z6|eg?P~@F3tR z=(Q<;*?{8!ivVW=E(BZxxDv1iuo3V^z>R?S0dA!(Y;+8(^P3Im;l@;*g4S(J*D2^* zc`DQp-hh0FEHoRU8AMOgR){Q!EQrq_K9YEhq6tM4iY63ID4I|-p=d(UgrW&W6N)Aj zO(>dBG@)oh(S)K2MH7l96iq0auslsT3p@4#2P_S6=w}OnM_2I2lZ-rSsQ+%k?-rdh OCmC1R^a5P#O#gqLhWC{K literal 0 HcmV?d00001 diff --git a/src/basys2.ucf b/src/basys2.ucf new file mode 100644 index 0000000..b3427c5 --- /dev/null +++ b/src/basys2.ucf @@ -0,0 +1,58 @@ +NET "uclk" LOC = "M6"; # Bank = 2, Signal name = UCLK + +# Pin assignment for LEDs +NET "Led<7>" LOC = "G1" ; # Bank = 3, Signal name = LD7 +NET "Led<6>" LOC = "P4" ; # Bank = 2, Signal name = LD6 +NET "Led<5>" LOC = "N4" ; # Bank = 2, Signal name = LD5 +NET "Led<4>" LOC = "N5" ; # Bank = 2, Signal name = LD4 +NET "Led<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3 +NET "Led<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2 +NET "Led<1>" LOC = "M11" ; # Bank = 2, Signal name = LD1 +NET "Led<0>" LOC = "M5" ; # Bank = 2, Signal name = LD0 + +# Pin assignment for 7-segment display +NET "seg<0>" LOC = "L14"; # Bank = 1, Signal name = CA +NET "seg<1>" LOC = "H12"; # Bank = 1, Signal name = CB +NET "seg<2>" LOC = "N14"; # Bank = 1, Signal name = CC +NET "seg<3>" LOC = "N11"; # Bank = 2, Signal name = CD +NET "seg<4>" LOC = "P12"; # Bank = 2, Signal name = CE +NET "seg<5>" LOC = "L13"; # Bank = 1, Signal name = CF +NET "seg<6>" LOC = "M12"; # Bank = 1, Signal name = CG +NET "seg<7>" LOC = "N13"; # Bank = 1, Signal name = DP +NET "an<0>" LOC = "F12"; # Bank = 1, Signal name = AN0 +NET "an<1>" LOC = "J12"; # Bank = 1, Signal name = AN1 +NET "an<2>" LOC = "M13"; # Bank = 1, Signal name = AN2 +NET "an<3>" LOC = "K14"; # Bank = 1, Signal name = AN3 + +# Pin assignment for SWs +#NET "sw<7>" LOC = "N3"; # Bank = 2, Signal name = SW7 # This one is currently unused +NET "sw<6>" LOC = "E2"; # Bank = 3, Signal name = SW6 +NET "sw<5>" LOC = "F3"; # Bank = 3, Signal name = SW5 +NET "sw<4>" LOC = "G3"; # Bank = 3, Signal name = SW4 +NET "sw<3>" LOC = "B4"; # Bank = 3, Signal name = SW3 +NET "sw<2>" LOC = "K3"; # Bank = 3, Signal name = SW2 +NET "sw<1>" LOC = "L3"; # Bank = 3, Signal name = SW1 +NET "sw<0>" LOC = "P11"; # Bank = 2, Signal name = SW0 +NET "btn<3>" LOC = "A7"; # Bank = 1, Signal name = BTN3 +NET "btn<2>" LOC = "M4"; # Bank = 0, Signal name = BTN2 +NET "btn<1>" LOC = "C11"; # Bank = 2, Signal name = BTN1 +NET "btn<0>" LOC = "G12"; # Bank = 0, Signal name = BTN0 +# Pin assignment for VGA +NET "HSYNC" LOC = "J14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = HSYNC +NET "VSYNC" LOC = "K13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = VSYNC +NET "VOut<7>" LOC = "F13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = RED2 +NET "VOut<6>" LOC = "D13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = RED1 +NET "VOut<5>" LOC = "C14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = RED0 +NET "VOut<4>" LOC = "G14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = GRN2 +NET "VOut<3>" LOC = "G13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = GRN1 +NET "VOut<2>" LOC = "F14";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = GRN0 +NET "VOut<1>" LOC = "J13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = BLU2 +NET "VOut<0>" LOC = "H13";# |DRIVE = 2 |PULLUP ; # Bank = 1, Signal name = BLU1 +# Pin assignments for oscilloscope inputs +NET "red" LOC = "C6"; +NET "green" LOC = "B6"; +NET "blue" LOC = "C5"; + +#Created by Constraints Editor (xc3s100e-cp132-5) - 2011/04/25 +NET "uclk" TNM_NET = uclk; +TIMESPEC TS_uclk = PERIOD "uclk" 32 MHz HIGH 50%; diff --git a/src/bits_aggregator.vhd b/src/bits_aggregator.vhd new file mode 100644 index 0000000..b78b781 --- /dev/null +++ b/src/bits_aggregator.vhd @@ -0,0 +1,110 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 19:43:33 05/27/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity bits_aggregator is + port ( + -- Inputs + nrst : in std_logic; + clk108 : in std_logic; + flush_and_return_to_zero : in std_logic; + write_enable : in std_logic; + red_value : in std_logic; + green_value : in std_logic; + blue_value : in std_logic; + + -- Outputs + wea : out std_logic; + addra : out std_logic_vector (12 downto 0); + dina : out std_logic_vector (8 downto 0) + ); +end bits_aggregator; + +architecture behavioral of bits_aggregator is + signal mod3 : integer range 0 to 2 := 0; + signal next_mod3 : integer range 0 to 2; + signal mod3_overflow : std_logic := '0'; + + signal address : std_logic_vector (12 downto 0) := (others => '0'); + signal next_address : std_logic_vector (12 downto 0); + + signal row_buffer : std_logic_vector (5 downto 0) := (others => '0'); + signal next_row : std_logic_vector (8 downto 0) := (others => '0'); +begin + + -- Process calculates next_mod3, mod3_overflow, next_address + process (mod3, address) is + begin + if mod3 = 2 then + next_mod3 <= 0; + mod3_overflow <= '1'; + next_address <= address + 1; + else + next_mod3 <= mod3 + 1; + mod3_overflow <= '0'; + next_address <= address; + end if; + end process; + + -- Process calculates next_row + process (mod3, row_buffer, red_value, green_value, blue_value) is + begin + if mod3 = 0 then + next_row (0) <= red_value; + next_row (1) <= green_value; + next_row (2) <= blue_value; + next_row (8 downto 3) <= (others => '0'); + elsif mod3 = 1 then + next_row (2 downto 0) <= row_buffer (2 downto 0); + next_row (3) <= red_value; + next_row (4) <= green_value; + next_row (5) <= blue_value; + next_row (8 downto 6) <= (others => '0'); + else + next_row (5 downto 0) <= row_buffer (5 downto 0); + next_row (6) <= red_value; + next_row (7) <= green_value; + next_row (8) <= blue_value; + end if; + end process; + + process (nrst, clk108) is + begin + if nrst = '0' then + mod3 <= 0; + address <= (others => '0'); + wea <= '0'; + addra <= (others => '0'); + dina <= (others => '0'); + elsif rising_edge (clk108) then + if flush_and_return_to_zero = '1' then + mod3 <= 0; + address <= (others => '0'); + row_buffer <= (others => '0'); + addra <= address; + dina <= next_row; + wea <= '1'; + elsif write_enable = '1' then + mod3 <= next_mod3; + address <= next_address; + row_buffer <= next_row (5 downto 0); + if mod3_overflow = '1' then + addra <= address; + dina <= next_row; + wea <= '1'; + else + wea <= '0'; + end if; + else + wea <= '0'; + end if; + end if; + end process; + + +end behavioral; + diff --git a/src/char_rom_mux.vhd b/src/char_rom_mux.vhd new file mode 100644 index 0000000..ee95a81 --- /dev/null +++ b/src/char_rom_mux.vhd @@ -0,0 +1,55 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 17:46:36 05/28/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + +entity char_rom_mux is + port ( + -- Inputs + nrst : in std_logic; + clk108 : in std_logic; + active_pixgen_source : in PIXGEN_SOURCE_T; + char_pos_x : in integer range 0 to 7; + char_pos_y : in integer range 0 to 15; + time_base_char : in short_character; + settings_char : in short_character; + + char_pixel : out std_logic + ); +end char_rom_mux; + +architecture behavioral of char_rom_mux is + signal addra : std_logic_vector (13 downto 0); + signal douta : std_logic; + signal char_int : integer range 0 to 127; + signal char_lv : std_logic_vector (6 downto 0); + signal pos_x_lv : std_logic_vector (2 downto 0); + signal pos_y_lv : std_logic_vector (3 downto 0); +begin + char_rom_memory: entity work.char_rom_memory + port map ( + clka => clk108, + addra => addra, + douta(0) => douta + ); + + char_pixel <= '0' when nrst = '0' else douta; + + with active_pixgen_source select + char_int <= + short_character'pos (time_base_char) when TIME_BASE_PIXGEN_T, + short_character'pos (settings_char) when SETTINGS_PIXGEN_T, + 0 when others; + char_lv <= std_logic_vector (to_unsigned (char_int, 7)); + pos_x_lv <= std_logic_vector (to_unsigned (char_pos_x, 3)); + pos_y_lv <= std_logic_vector (to_unsigned (char_pos_y, 4)); + + + addra <= char_lv (6 downto 4) & pos_y_lv & char_lv (3 downto 0) & pos_x_lv; + +end behavioral; + diff --git a/src/clock_divider.vhd b/src/clock_divider.vhd new file mode 100644 index 0000000..9183b65 --- /dev/null +++ b/src/clock_divider.vhd @@ -0,0 +1,38 @@ +-- A simple frequency divider + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity divider is + -- 1 + -- f_out = f_in ----- + -- 2 * n + generic (n: natural range 1 to 2147483647); + port ( + clk_in : in std_logic; + nrst : in std_logic; + clk_out : out std_logic + ); +end entity divider; + +architecture counter of divider is + signal cnt : integer range 0 to n - 1; + signal internal_clk_out : std_logic := '0'; +begin + clk_out <= internal_clk_out; + process (clk_in, nrst) + begin + if nrst = '0' then + cnt <= 0; + internal_clk_out <= '0'; + elsif rising_edge (clk_in) then + if cnt = n - 1 then + cnt <= 0; + internal_clk_out <= not internal_clk_out; + else + cnt <= cnt + 1; + end if; + end if; + end process; +end architecture counter; diff --git a/src/debouncer.vhd b/src/debouncer.vhd new file mode 100644 index 0000000..c3649e5 --- /dev/null +++ b/src/debouncer.vhd @@ -0,0 +1,38 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 15:03:57 05/24/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + + +entity debouncer is + generic ( + n : natural := 5000; + signal_width : natural := 8 + ); + port ( + nrst : in std_logic; + clk : in std_logic; + input : in std_logic_vector (signal_width - 1 downto 0); + output : out std_logic_vector (signal_width - 1 downto 0) + ); +end debouncer; + +architecture behavioral of debouncer is +begin + debouncers: for i in 0 to signal_width - 1 generate + one_debouncer: entity work.single_debouncer + generic map ( + n => n + ) + port map( + nrst => nrst, + clk => clk, + input => input (i), + output => output (i) + ); + end generate debouncers; + +end behavioral; + diff --git a/src/display.vhd b/src/display.vhd new file mode 100644 index 0000000..c14bdaf --- /dev/null +++ b/src/display.vhd @@ -0,0 +1,224 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 15:58:36 05/22/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + + +entity oscilloscope_display is + port ( + nrst : in std_logic; + clk108 : in std_logic; + is_reading_active : in std_logic; + trigger_event : in TRIGGER_EVENT_T; + red_enable : in std_logic; + green_enable : in std_logic; + blue_enable : in std_logic; + continue_after_reading : in std_logic; + time_resolution : in integer range 0 to 15; + currently_read_screen_segment : in natural range 0 to 13; + currently_read_screen_column : in natural range 0 to 1279; + addrb : out std_logic_vector (12 downto 0); + doutb : in std_logic_vector (8 downto 0); + vout : out std_logic_vector (7 downto 0); + vsync : out std_logic; + hsync : out std_logic + ); +end oscilloscope_display; + +architecture behavioral of oscilloscope_display is + signal vga_cntl_line_change : std_logic; + signal vga_cntl_page_change : std_logic; + signal vga_cntl_column : integer range 0 to 1279; + signal vga_cntl_column_change : std_logic; + signal vga_cntl_vblank : std_logic; + signal vga_cntl_hsync : std_logic; + signal vga_cntl_vsync : std_logic; + + signal scr_pos_segment : integer range 0 to 15; + signal scr_pos_segment_change : std_logic; + signal scr_pos_subsegment : integer range 0 to 3; + signal scr_pos_subsegment_change : std_logic; + signal scr_pos_line : integer range 0 to 15; + signal scr_pos_out_line_change : std_logic; + signal scr_pos_out_column : integer range 0 to 1279; + signal scr_pos_out_column_mod_8 : integer range 0 to 7; + signal scr_pos_out_column_div_8 : integer range 0 to 159; + signal scr_pos_column_change : std_logic; + signal scr_pos_out_page_change : std_logic; + signal scr_pos_active_pixgen_source : PIXGEN_SOURCE_T; + + + signal scr_pos_out_column_mod_8_delayed : integer range 0 to 7; + signal scr_pos_line_delayed : integer range 0 to 15; + + signal scr_pos_active_pixgen_source_delayed_1 : PIXGEN_SOURCE_T; + signal scr_pos_active_pixgen_source_delayed_2 : PIXGEN_SOURCE_T; + + signal time_base_char : short_character; + signal settings_char : short_character; + signal char_rom_mux_char_pixel : std_logic; + + signal trace_vout : std_logic_vector (7 downto 0); + signal time_base_vout : std_logic_vector (7 downto 0); + signal settings_vout : std_logic_vector (7 downto 0); + +begin + + vga_controller_1280_1024: entity work.vga_controller_1280_1024 + port map ( + nrst => nrst, + clk108 => clk108, + hsync => vga_cntl_hsync, + vsync => vga_cntl_vsync, + vblank => vga_cntl_vblank, + line_change => vga_cntl_line_change, + page_change => vga_cntl_page_change, + column => vga_cntl_column, + column_change => vga_cntl_column_change + ); + + + + screen_position_gen: entity work.screen_position_gen + port map ( + nrst => nrst, + clk108 => clk108, + vblank => vga_cntl_vblank, + in_line_change => vga_cntl_line_change, + in_page_change => vga_cntl_page_change, + in_column => vga_cntl_column, + in_column_change => vga_cntl_column_change, + + segment => scr_pos_segment, + segment_change => scr_pos_segment_change, + subsegment => scr_pos_subsegment, + subsegment_change => scr_pos_subsegment_change, + line => scr_pos_line, + out_line_change => scr_pos_out_line_change, + out_column => scr_pos_out_column, + out_column_mod_8 => scr_pos_out_column_mod_8, + out_column_div_8 => scr_pos_out_column_div_8, + out_column_change => scr_pos_column_change, + out_page_change => scr_pos_out_page_change, + active_pixgen_source => scr_pos_active_pixgen_source + ); + + trace_pixgen: entity work.trace_pixgen + port map ( + nrst => nrst, + clk108 => clk108, + segment => scr_pos_segment, + segment_change => scr_pos_segment_change, + subsegment => scr_pos_subsegment, + subsegment_change => scr_pos_subsegment_change, + line => scr_pos_line, + line_change => scr_pos_out_line_change, + column => scr_pos_out_column, + column_change => scr_pos_column_change, + page_change => scr_pos_out_page_change, + active_pixgen_source => scr_pos_active_pixgen_source, + currently_read_screen_segment => currently_read_screen_segment, + currently_read_screen_column => currently_read_screen_column, + time_resolution => time_resolution, + is_reading_active => is_reading_active, + doutb => doutb, + addrb => addrb, + vout => trace_vout + ); + + scr_pos_out_column_mod_8_delayed <= scr_pos_out_column_mod_8 when rising_edge (clk108); + scr_pos_line_delayed <= scr_pos_line when rising_edge (clk108); + scr_pos_active_pixgen_source_delayed_1 <= scr_pos_active_pixgen_source when rising_edge (clk108); + scr_pos_active_pixgen_source_delayed_2 <= scr_pos_active_pixgen_source_delayed_1 when rising_edge (clk108); + + char_rom_mux: entity work.char_rom_mux + port map ( + nrst => nrst, + clk108 => clk108, + active_pixgen_source => scr_pos_active_pixgen_source_delayed_1, + char_pos_x => scr_pos_out_column_mod_8_delayed, + char_pos_y => scr_pos_line_delayed, + time_base_char => time_base_char, + settings_char => settings_char, + char_pixel => char_rom_mux_char_pixel + ); + + time_base_pixgen: entity work.time_base_pixgen + port map ( + nrst => nrst, + clk108 => clk108, + segment => scr_pos_segment, + segment_change => scr_pos_segment_change, + subsegment => scr_pos_subsegment, + subsegment_change => scr_pos_subsegment_change, + line => scr_pos_line, + line_change => scr_pos_out_line_change, + column => scr_pos_out_column, + column_change => scr_pos_column_change, + page_change => scr_pos_out_page_change, + active_pixgen_source => scr_pos_active_pixgen_source, + char => time_base_char, + char_pixel => char_rom_mux_char_pixel, + vout => time_base_vout + ); + + settings_pixgen: entity work.settings_pixgen + port map ( + nrst => nrst, + clk108 => clk108, + segment => scr_pos_segment, + segment_change => scr_pos_segment_change, + subsegment => scr_pos_subsegment, + subsegment_change => scr_pos_subsegment_change, + line => scr_pos_line, + line_change => scr_pos_out_line_change, + column => scr_pos_out_column, + column_div_8 => scr_pos_out_column_div_8, + column_mod_8 => scr_pos_out_column_mod_8, + column_change => scr_pos_column_change, + page_change => scr_pos_out_page_change, + active_pixgen_source => scr_pos_active_pixgen_source, + is_reading_active => is_reading_active, + trigger_event => trigger_event, + red_enable => red_enable, + green_enable => green_enable, + blue_enable => blue_enable, + continue_after_reading => continue_after_reading, + time_resolution => time_resolution, + char => settings_char, + char_pixel => char_rom_mux_char_pixel, + vout => settings_vout + ); + + + pixgen_mux: entity work.pixgen_mux + port map ( + nrst => nrst, + clk108 => clk108, + trace_vout => trace_vout, + time_base_vout => time_base_vout, + settings_vout => settings_vout, + active_pixgen_source => scr_pos_active_pixgen_source_delayed_2, + vout => vout + ); + + vga_sync_signals_4_delay: entity work.n_cycles_delayer + generic map ( + n => 4, + signal_width => 2 + ) + port map ( + nrst => nrst, + clk => clk108, + input(0) => vga_cntl_hsync, + input(1) => vga_cntl_vsync, + output(0) => hsync, + output(1) => vsync + ); + +end behavioral; + diff --git a/src/main.vhd b/src/main.vhd new file mode 100644 index 0000000..4a99598 --- /dev/null +++ b/src/main.vhd @@ -0,0 +1,281 @@ +---------------------------------------------------------------------------------- +-- Author: Marcin Osowski +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use work.types.all; + +entity oscilloscope is + port( + uclk : in std_logic; -- 32 MHz stable + sw : in std_logic_vector (6 downto 0); + btn : in std_logic_vector (3 downto 0); + red : in std_logic; + green : in std_logic; + blue : in std_logic; + + -- Project does not use any of the below + -- pins. They are here just to give them + -- constant value. + led : out std_logic_vector (7 downto 0); + seg : out std_logic_vector (7 downto 0); + an : out std_logic_vector (3 downto 0); + + hsync : out std_logic; + vsync : out std_logic; + vout : out std_logic_vector (7 downto 0) + ); +end entity oscilloscope; + +architecture structural of oscilloscope is + signal rst : std_logic; + signal nrst : std_logic; + signal clk108 : std_logic; + signal clk108_ok : std_logic; + signal clk10khz : std_logic; + + signal sw_3_delayed : std_logic_vector (6 downto 0); + signal btn_3_delayed : std_logic_vector (2 downto 0); + signal sw_debounced : std_logic_vector (6 downto 0); + signal btn_debounced : std_logic_vector (2 downto 0); + + signal red_3_delayed : std_logic; + signal green_3_delayed : std_logic; + signal blue_3_delayed : std_logic; + + signal trigger_btn : std_logic; + signal trigger_event : TRIGGER_EVENT_T; + signal red_enable : std_logic; + signal green_enable : std_logic; + signal blue_enable : std_logic; + signal continue_after_reading : std_logic; + signal time_resolution : integer range 0 to 15; + signal time_resolution_delayed : integer range 0 to 15; + + signal overflow_indicator : std_logic; + signal red_after_trigger : std_logic; + signal green_after_trigger : std_logic; + signal blue_after_trigger : std_logic; + signal is_reading_active : std_logic; + + signal flush_and_return_to_zero : std_logic; + signal write_enable : std_logic; + signal reader_red_value : std_logic; + signal reader_green_value : std_logic; + signal reader_blue_value : std_logic; + signal reader_screen_segment : natural range 0 to 13; + signal reader_screen_column : natural range 0 to 1279; + + + signal pre_hsync : std_logic; + signal pre_vsync : std_logic; + signal pre_vout : std_logic_vector (7 downto 0); + + signal wea : std_logic; + signal addra : std_logic_vector (12 downto 0); + signal dina : std_logic_vector (8 downto 0); + signal addrb : std_logic_vector (12 downto 0); + signal doutb : std_logic_vector (8 downto 0); + + + +begin + led <= (others => '0'); + seg <= (others => '1'); + an <= (others => '1'); + + display_clock_108mhz: entity work.clock_108mhz + port map ( + CLKIN_IN => uclk, + RST_IN => btn (3), + CLKFX_OUT => clk108, + CLKIN_IBUFG_OUT => open, + LOCKED_OUT => clk108_ok + ); + + + rst <= btn (3) and clk108_ok; + nrst <= not rst; + + divider_10khz: entity work.divider + generic map ( + n => 5400 + ) + port map ( + clk_in => clk108, + nrst => nrst, + clk_out => clk10khz + ); + + btn_sw_3_delayer : entity work.n_cycles_delayer + generic map ( + n => 3, + signal_width => 10 + ) + port map ( + nrst => nrst, + clk => clk10khz, + input (9 downto 7) => btn (2 downto 0), + input (6 downto 0) => sw (6 downto 0), + + output (9 downto 7) => btn_3_delayed (2 downto 0), + output (6 downto 0) => sw_3_delayed (6 downto 0) + ); + + input_signals_3_delayer : entity work.n_cycles_delayer + generic map ( + n => 3, + signal_width => 3 + ) + port map ( + nrst => nrst, + clk => clk108, + input (2) => red, + input (1) => green, + input (0) => blue, + + output (2) => red_3_delayed, + output (1) => green_3_delayed, + output (0) => blue_3_delayed + ); + + btn_sw_debouncers: entity work.debouncer + generic map ( + n => 50, + signal_width => 10 + ) + port map ( + nrst => nrst, + clk => clk10khz, + input (9 downto 7) => btn_3_delayed, + input (6 downto 0) => sw_3_delayed, + + output (9 downto 7) => btn_debounced, + output (6 downto 0) => sw_debounced + ); + + settings: entity work.settings + port map ( + nrst => nrst, + clk108 => clk108, + sw => sw_debounced, + btn => btn_debounced, + trigger_btn => trigger_btn, + trigger_event => trigger_event, + red_enable => red_enable, + green_enable => green_enable, + blue_enable => blue_enable, + continue_after_reading => continue_after_reading, + time_resolution => time_resolution + ); + + trigger: entity work.trigger + port map ( + nrst => nrst, + clk108 => clk108, + trigger_btn => trigger_btn, + trigger_event => trigger_event, + red_enable => red_enable, + green_enable => green_enable, + blue_enable => blue_enable, + continue_after_reading => continue_after_reading, + red_input => red_3_delayed, + green_input => green_3_delayed, + blue_input => blue_3_delayed, + overflow_indicator => overflow_indicator, + red_output => red_after_trigger, + green_output => green_after_trigger, + blue_output => blue_after_trigger, + is_reading_active => is_reading_active + ); + + time_resolution_delayed <= time_resolution when rising_edge (clk108); + + reader: entity work.reader + port map ( + nrst => nrst, + clk108 => clk108, + input_red => red_after_trigger, + input_green => green_after_trigger, + input_blue => blue_after_trigger, + is_reading_active => is_reading_active, + time_resolution => time_resolution_delayed, + overflow_indicator => overflow_indicator, + screen_segment => reader_screen_segment, + screen_column => reader_screen_column, + flush_and_return_to_zero => flush_and_return_to_zero, + write_enable => write_enable, + red_value => reader_red_value, + green_value => reader_green_value, + blue_value => reader_blue_value + ); + + bits_aggregator: entity work.bits_aggregator + port map ( + nrst => nrst, + clk108 => clk108, + flush_and_return_to_zero => flush_and_return_to_zero, + write_enable => write_enable, + red_value => reader_red_value, + green_value => reader_green_value, + blue_value => reader_blue_value, + wea => wea, + addra => addra, + dina => dina + ); + + + + oscilloscope_display: entity work.oscilloscope_display + port map ( + nrst => nrst, + clk108 => clk108, + is_reading_active => is_reading_active, + trigger_event => trigger_event, + red_enable => red_enable, + green_enable => green_enable, + blue_enable => blue_enable, + continue_after_reading => continue_after_reading, + time_resolution => time_resolution, + currently_read_screen_segment => reader_screen_segment, + currently_read_screen_column => reader_screen_column, + addrb => addrb, + doutb => doutb, + vout => pre_vout, + vsync => pre_vsync, + hsync => pre_hsync + ); + + vga_signal_formatter: entity work.one_cycle_delayer + generic map ( + signal_width => 10 + ) + port map ( + nrst => nrst, + clk => clk108, + input (9 downto 2) => pre_vout, + input (1) => pre_vsync, + input (0) => pre_hsync, + output (9 downto 2) => vout, + output (1) => vsync, + output (0) => hsync + ); + + + trace_memory: entity work.trace_memory + port map ( + clka => clk108, + wea(0) => wea, + addra => addra, + dina => dina, + clkb => clk108, + rstb => rst, + addrb => addrb, + doutb => doutb + ); + + +end architecture structural; diff --git a/src/n_cycles_delayer.vhd b/src/n_cycles_delayer.vhd new file mode 100644 index 0000000..7721cff --- /dev/null +++ b/src/n_cycles_delayer.vhd @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 17:31:43 05/22/2011 +-- +-- Description: This entity delays given signal of width signal_width by n clock cycles. +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + + +entity n_cycles_delayer is + generic ( + n : integer range 2 to 1024; + signal_width : integer range 1 to 1024 + ); + + port ( + nrst : in std_logic; + clk : in std_logic; + input : in std_logic_vector (signal_width - 1 downto 0); + output : out std_logic_vector (signal_width - 1 downto 0) + ); +end n_cycles_delayer; + +architecture behavioral of n_cycles_delayer is + type delay_array_t is array (n - 1 downto 0) of std_logic_vector (signal_width - 1 downto 0); + signal delay_array: delay_array_t ;--:= (others => (others => '0')); + +begin + output <= delay_array (n - 1); + process (clk, nrst) is + variable i : integer range 0 to n - 2; + begin + if nrst = '0' then + for i in 0 to n - 1 loop + delay_array (i) <= (others => '0'); + end loop; + elsif rising_edge (clk) then + delay_array (0) <= input; + for i in 0 to (n - 2) loop + delay_array (i + 1) <= delay_array (i); + end loop; + end if; + end process; + +end architecture behavioral; + diff --git a/src/one_cycle_delayer.vhd b/src/one_cycle_delayer.vhd new file mode 100644 index 0000000..53b0f53 --- /dev/null +++ b/src/one_cycle_delayer.vhd @@ -0,0 +1,36 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 16:19:05 05/24/2011 +-- +-- Description: This entity delays given signal of width signal_width by n clock cycles. +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + + +entity one_cycle_delayer is + generic ( + signal_width : integer range 1 to 1024 + ); + + port ( + nrst : in std_logic; + clk : in std_logic; + input : in std_logic_vector (signal_width - 1 downto 0); + output : out std_logic_vector (signal_width - 1 downto 0) + ); +end one_cycle_delayer; + +architecture behavioral of one_cycle_delayer is + +begin + process (clk, nrst) is + begin + if nrst = '0' then + output <= (others => '0'); + elsif rising_edge (clk) then + output <= input; + end if; + end process; +end behavioral; + diff --git a/src/pixgen_mux.vhd b/src/pixgen_mux.vhd new file mode 100644 index 0000000..5d2626c --- /dev/null +++ b/src/pixgen_mux.vhd @@ -0,0 +1,42 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 21:10:21 05/22/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use work.types.all; + + +entity pixgen_mux is + port ( + nrst : in std_logic; + clk108 : in std_logic; + trace_vout : in std_logic_vector (7 downto 0); + time_base_vout : in std_logic_vector (7 downto 0); + settings_vout : in std_logic_vector (7 downto 0); + active_pixgen_source : in PIXGEN_SOURCE_T; + vout : out std_logic_vector (7 downto 0) + ); +end pixgen_mux; + +architecture behavioral of pixgen_mux is + +begin + process (nrst, clk108) is + begin + if nrst = '0' then + vout <= "00000000"; + elsif rising_edge (clk108) then + if active_pixgen_source = TRACE_PIXGEN_T then + vout <= trace_vout; + elsif active_pixgen_source = TIME_BASE_PIXGEN_T then + vout <= time_base_vout; + elsif active_pixgen_source = SETTINGS_PIXGEN_T then + vout <= settings_vout; + else + vout <= "00000000"; + end if; + end if; + end process; + +end behavioral; diff --git a/src/reader.vhd b/src/reader.vhd new file mode 100644 index 0000000..14d08f5 --- /dev/null +++ b/src/reader.vhd @@ -0,0 +1,150 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 14:48:55 05/24/2011 +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity reader is + port ( + nrst : in std_logic; + clk108 : in std_logic; + input_red : in std_logic; + input_green : in std_logic; + input_blue : in std_logic; + is_reading_active : in std_logic; + time_resolution : in integer range 0 to 15; + + -- This is an asynchronous output. It indicates that during next + -- clock cycle entity will generate flush_and_return_to_zero. + overflow_indicator : out std_logic; + + screen_segment : out natural range 0 to 13; + screen_column : out natural range 0 to 1279; + flush_and_return_to_zero : out std_logic; + write_enable : out std_logic; + red_value : out std_logic; + green_value : out std_logic; + blue_value : out std_logic + ); + + constant max_time_resolution : natural := 432000; + + type res_array is array (0 to 15) of natural range 2 to max_time_resolution; + + -- Real time resolution will be given by equation: + -- time_between_probes = time_resolutions (time_resolution) / (108 Mhz) + -- No 1 (ones) here please! + constant time_resolutions : res_array := ( + 2, 5, 10, 20, 108, 216, 432, 1080, 2160, 4320, + 10800, 21600, 43200, 108000, 216000, 432000 + ); + + +end reader; + + +architecture behavioral of reader is + signal time_position : natural range 0 to max_time_resolution + 1 := 0; + signal next_time_position : natural range 0 to max_time_resolution + 1; + signal time_overflow : std_logic; + + signal memory_position : natural range 0 to (14 * 1280) := 0; + signal next_memory_position : natural range 0 to (14 * 1280); + + signal internal_screen_segment : natural range 0 to 13:= 0; + signal internal_screen_column : natural range 0 to 1279 := 0; + signal next_screen_segment : natural range 0 to 14; + signal next_screen_column : natural range 0 to 1280; + + + signal internal_overflow_indicator : std_logic; +begin + overflow_indicator <= internal_overflow_indicator; + screen_segment <= internal_screen_segment; + screen_column <= internal_screen_column; + + -- Process computes next_time_position and time_overflow + process (time_position) is + begin + if time_position + 1 >= time_resolutions (time_resolution) then + next_time_position <= 0; + time_overflow <= '1'; + else + next_time_position <= time_position + 1; + time_overflow <= '0'; + end if; + end process; + + -- Process computes next_memory_position and internal_overflow_indicator + process (memory_position, internal_screen_segment, internal_screen_column, time_overflow) is + begin + if time_overflow = '1' then + if memory_position + 1 >= (14 * 1280) then + next_memory_position <= 0; + next_screen_segment <= 0; + next_screen_column <= 0; + internal_overflow_indicator <= '1'; + else + next_memory_position <= memory_position + 1; + if internal_screen_column + 1 >= 1280 then + next_screen_column <= 0; + next_screen_segment <= internal_screen_segment + 1; + else + next_screen_column <= internal_screen_column + 1; + next_screen_segment <= internal_screen_segment; + end if; + internal_overflow_indicator <= '0'; + end if; + else + next_memory_position <= memory_position; + next_screen_column <= internal_screen_column; + next_screen_segment <= internal_screen_segment; + internal_overflow_indicator <= '0'; + end if; + end process; + + + process (nrst, clk108) is + begin + if nrst = '0' then + time_position <= 0; + memory_position <= 0; + flush_and_return_to_zero <= '0'; + write_enable <= '0'; + red_value <= '0'; + green_value <= '0'; + blue_value <= '0'; + elsif rising_edge (clk108) then + memory_position <= next_memory_position; + internal_screen_column <= next_screen_column; + internal_screen_segment <= next_screen_segment; + if is_reading_active = '1' or time_position /= 0 then + time_position <= next_time_position; + if time_overflow = '1' then + red_value <= input_red; + green_value <= input_green; + blue_value <= input_blue; + write_enable <= '1'; + flush_and_return_to_zero <= internal_overflow_indicator; + else + red_value <= '0'; + green_value <= '0'; + blue_value <= '0'; + write_enable <= '0'; + flush_and_return_to_zero <= '0'; + end if; + else + red_value <= '0'; + green_value <= '0'; + blue_value <= '0'; + write_enable <= '0'; + flush_and_return_to_zero <= '0'; + end if; + end if; + end process; + +end behavioral; diff --git a/src/rom_data/8x16_font_ASCII_DOS_437.coe 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+ for x in xrange(128): + if x + y > 0: + print ',' + pixel = i.getpixel((x,y)) + assert pixel in [0,255] + if pixel == 255: + print 0, + else: + print 1, +print ';' diff --git a/src/screen_position_gen.vhd b/src/screen_position_gen.vhd new file mode 100644 index 0000000..2771cb0 --- /dev/null +++ b/src/screen_position_gen.vhd @@ -0,0 +1,125 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + +entity screen_position_gen is + port ( + -- inputs + nrst : in std_logic; + clk108 : in std_logic; + vblank : in std_logic; + in_line_change : in std_logic; + in_page_change : in std_logic; + in_column : in integer range 0 to 1279; + in_column_change : in std_logic; + + -- outputs + segment : out integer range 0 to 15; + segment_change : out std_logic; + subsegment : out integer range 0 to 3; + subsegment_change : out std_logic; + line : out integer range 0 to 15; + out_line_change : out std_logic; + out_column : out integer range 0 to 1279; + out_column_mod_8 : out integer range 0 to 7; + out_column_div_8 : out integer range 0 to 159; + out_column_change : out std_logic; + out_page_change : out std_logic; + active_pixgen_source : out PIXGEN_SOURCE_T + ); +end screen_position_gen; + + +architecture behavioral of screen_position_gen is + signal internal_segment : integer range 0 to 15; + signal internal_subsegment : integer range 0 to 3; + signal internal_line : integer range 0 to 15; + + signal next_segment : integer range 0 to 15; + signal next_subsegment : integer range 0 to 3; + signal next_line : integer range 0 to 15; + +begin + segment <= internal_segment; + subsegment <= internal_subsegment; + line <= internal_line; + + -- This process calculates next_line, next_subsegment, next_segment signals + process (in_line_change, in_page_change, internal_segment, internal_subsegment, internal_line) is + begin + if in_page_change = '1' then + next_line <= 0; + next_subsegment <= 0; + next_segment <= 0; + else + if in_line_change = '1' then + if internal_line = 15 then + next_line <= 0; + if internal_subsegment = 3 then + next_subsegment <= 0; + if internal_segment = 15 then + next_segment <= 0; + else + next_segment <= internal_segment + 1; + end if; + else + next_subsegment <= internal_subsegment + 1; + next_segment <= internal_segment; + end if; + else + next_line <= internal_line + 1; + next_subsegment <= internal_subsegment; + next_segment <= internal_segment; + end if; + else + next_line <= internal_line; + next_subsegment <= internal_subsegment; + next_segment <= internal_segment; + end if; + end if; + end process; + + -- This proces generates all output signals + process (clk108, nrst) is + begin + if nrst = '0' then + + elsif rising_edge (clk108) then + internal_line <= next_line; + internal_subsegment <= next_subsegment; + internal_segment <= next_segment; + out_line_change <= in_line_change; + + if internal_subsegment /= next_subsegment then + subsegment_change <= '1'; + else + subsegment_change <= '0'; + end if; + + if internal_segment /= next_segment then + segment_change <= '1'; + else + segment_change <= '0'; + end if; + + out_column <= in_column; + out_column_mod_8 <= in_column mod 8; + out_column_div_8 <= in_column / 8; + out_column_change <= in_column_change; + out_page_change <= in_page_change; + + if vblank = '1' then + active_pixgen_source <= BLANK_PIXGEN_T; + elsif next_segment < 14 then + if next_subsegment /= 3 then + active_pixgen_source <= TRACE_PIXGEN_T; + else + active_pixgen_source <= TIME_BASE_PIXGEN_T; + end if; + else + active_pixgen_source <= SETTINGS_PIXGEN_T; + end if; + end if; + end process; +end architecture behavioral; diff --git a/src/settings.vhd b/src/settings.vhd new file mode 100644 index 0000000..ce1f9fa --- /dev/null +++ b/src/settings.vhd @@ -0,0 +1,82 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 13:36:26 05/24/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + + +entity settings is + port ( + -- Inputs + nrst : in std_logic; + clk108 : in std_logic; + sw : in std_logic_vector (6 downto 0); + btn : in std_logic_vector (2 downto 0); + + -- Outputs + trigger_btn : out std_logic := '0'; + trigger_event : out TRIGGER_EVENT_T; + red_enable : out std_logic := '0'; + green_enable : out std_logic := '0'; + blue_enable : out std_logic := '0'; + continue_after_reading : out std_logic; + time_resolution : out integer range 0 to 15 := 0 + ); +end settings; + +architecture behavioral of settings is + signal prev_btn_1 : std_logic := '0'; + signal prev_btn_2 : std_logic := '0'; + + signal internal_continue_after_reading : std_logic := '0'; + signal internal_trigger_event : TRIGGER_EVENT_T := BUTTON_TRIGGER_T; + +begin + continue_after_reading <= internal_continue_after_reading; + trigger_event <= internal_trigger_event; + + process (nrst, clk108) is + begin + if nrst = '0' then + trigger_btn <= '0'; + internal_trigger_event <= BUTTON_TRIGGER_T; + red_enable <= '0'; + green_enable <= '0'; + blue_enable <= '0'; + internal_continue_after_reading <= '0'; + time_resolution <= 0; + prev_btn_1 <= '0'; + prev_btn_2 <= '0'; + elsif rising_edge (clk108) then + trigger_btn <= btn (0); + + prev_btn_2 <= btn (2); + if btn (2) = '1' and prev_btn_2 = '0' then + -- cycle through available modes + if internal_trigger_event = BUTTON_TRIGGER_T then + internal_trigger_event <= RED_TRIGGER_T; + elsif internal_trigger_event = RED_TRIGGER_T then + internal_trigger_event <= GREEN_TRIGGER_T; + elsif internal_trigger_event = GREEN_TRIGGER_T then + internal_trigger_event <= BLUE_TRIGGER_T; + elsif internal_trigger_event = BLUE_TRIGGER_T then + internal_trigger_event <= BUTTON_TRIGGER_T; + end if; + end if; + + red_enable <= sw (6); + green_enable <= sw (5); + blue_enable <= sw (4); + + prev_btn_1 <= btn (1); + if btn (1) = '1' and prev_btn_1 = '0' then + internal_continue_after_reading <= not internal_continue_after_reading; + end if; + time_resolution <= to_integer (unsigned (sw (3 downto 0))); + end if; + end process; + +end behavioral; \ No newline at end of file diff --git a/src/settings_pixgen.vhd b/src/settings_pixgen.vhd new file mode 100644 index 0000000..e0391d8 --- /dev/null +++ b/src/settings_pixgen.vhd @@ -0,0 +1,240 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 20:16:43 05/22/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +use work.types.all; + +entity settings_pixgen is + port ( + nrst : in std_logic; + clk108 : in std_logic; + segment : in integer range 0 to 15; + segment_change : in std_logic; + subsegment : in integer range 0 to 3; + subsegment_change : in std_logic; + line : in integer range 0 to 15; + line_change : in std_logic; + column : in integer range 0 to 1279; + column_mod_8 : in integer range 0 to 7; + column_div_8 : in integer range 0 to 159; + column_change : in std_logic; + page_change : in std_logic; + active_pixgen_source : in PIXGEN_SOURCE_T; + is_reading_active : in std_logic; + trigger_event : in TRIGGER_EVENT_T; + red_enable : in std_logic; + green_enable : in std_logic; + blue_enable : in std_logic; + continue_after_reading : in std_logic; + time_resolution : in integer range 0 to 15; + char : out short_character; + char_pixel : in std_logic; + vout : out std_logic_vector (7 downto 0) + ); +end settings_pixgen; + +architecture behavioral of settings_pixgen is + constant s_red_sig : short_string := to_short_string (" Red signal (C6): ???abled (SW6)"); + constant s_green_sig : short_string := to_short_string ("Green signal (B6): ???abled (SW5)"); + constant s_blue_sig : short_string := to_short_string (" Blue signal (C5): ???abled (SW4)"); + constant s_enabled : short_string := to_short_string (" en"); + constant s_disabled : short_string := to_short_string ("dis"); + + constant s_resolution : short_string := to_short_string (" Resolution: ???????? (SW3 ~ SW0)"); + constant s_trigger : short_string := to_short_string (" Trigger on: ???????? (BTN2 to change)"); + constant s_after : short_string := to_short_string ("After reading: ???????? (BTN1 to change)"); + + type res_array_t is array (0 to 15) of short_string (7 downto 0); + + constant res_array : res_array_t := ( + to_short_string (" 54 Mhz"), + to_short_string ("21.6 Mhz"), + to_short_string ("10.8 Mhz"), + to_short_string (" 5.4 Mhz"), + to_short_string (" 1 Mhz"), + to_short_string (" 500 khz"), + to_short_string (" 250 khz"), + to_short_string (" 100 khz"), + to_short_string (" 50 khz"), + to_short_string (" 25 khz"), + to_short_string (" 10 khz"), + to_short_string (" 5 khz"), + to_short_string (" 2.5 khz"), + to_short_string (" 1 khz"), + to_short_string (" 500 hz"), + to_short_string (" 250 hz") + ); + + constant s_btn0 : short_string := to_short_string (" BTN0"); + constant s_red : short_string := to_short_string (" red"); + constant s_green : short_string := to_short_string (" green"); + constant s_blue : short_string := to_short_string (" blue"); + + constant s_continue : short_string := to_short_string ("continue"); + constant s_stop : short_string := to_short_string (" stop"); + + constant s_reading_active : short_string := to_short_string (" Running... (press BTN0 to stop)"); + constant s_reading_stopped : short_string := to_short_string ("Stopped. Waiting for trigger event."); + + +begin + process (nrst, clk108) is + begin + if nrst = '0' then + char <= character_conv_table (0); + elsif rising_edge (clk108) then + if segment = 14 then + -- Upper settings segment (segment = 14) + if subsegment = 0 then + -- Red subsegment + if column_div_8 < 19 then + char <= s_red_sig (column_div_8); + elsif column_div_8 < 22 then + if red_enable = '1' then + char <= s_enabled (column_div_8 - 19); + else + char <= s_disabled (column_div_8 - 19); + end if; + elsif column_div_8 < s_red_sig'length then + char <= s_red_sig (column_div_8); + else + char <= to_short_character (' '); + end if; + + + elsif subsegment = 1 then + -- Green subsegment + if column_div_8 < 19 then + char <= s_green_sig (column_div_8); + elsif column_div_8 < 22 then + if green_enable = '1' then + char <= s_enabled (column_div_8 - 19); + else + char <= s_disabled (column_div_8 - 19); + end if; + elsif column_div_8 < s_green_sig'length then + char <= s_green_sig (column_div_8); + else + char <= to_short_character (' '); + end if; + + + elsif subsegment = 2 then + -- Blue subsegment + if column_div_8 < 19 then + char <= s_blue_sig (column_div_8); + elsif column_div_8 < 22 then + if blue_enable = '1' then + char <= s_enabled (column_div_8 - 19); + else + char <= s_disabled (column_div_8 - 19); + end if; + elsif column_div_8 < s_blue_sig'length then + char <= s_blue_sig (column_div_8); + else + char <= to_short_character (' '); + end if; + + + else + -- Empty subsegment + char <= to_short_character (' '); + end if; + + + else + -- Lower settings segment (segment = 15) + if subsegment = 0 then + -- Resolution subsegment + if column_div_8 < 15 then + char <= s_resolution (column_div_8); + elsif column_div_8 < 23 then + char <= res_array (time_resolution) (column_div_8 - 15); + elsif column_div_8 < s_resolution'length then + char <= s_resolution (column_div_8); + else + char <= to_short_character (' '); + end if; + + + elsif subsegment = 1 then + -- Trigger subsegment + if column_div_8 < 15 then + char <= s_trigger (column_div_8); + elsif column_div_8 < 23 then + if trigger_event = RED_TRIGGER_T then + char <= s_red (column_div_8 - 15); + elsif trigger_event = GREEN_TRIGGER_T then + char <= s_green (column_div_8 - 15); + elsif trigger_event = BLUE_TRIGGER_T then + char <= s_blue (column_div_8 - 15); + else + char <= s_btn0 (column_div_8 - 15); + end if; + elsif column_div_8 < s_trigger'length then + char <= s_trigger (column_div_8); + else + char <= to_short_character (' '); + end if; + + + elsif subsegment = 2 then + -- Behaviour after reading subsegment + if column_div_8 < 15 then + char <= s_after (column_div_8); + elsif column_div_8 < 23 then + if continue_after_reading = '1' then + char <= s_continue (column_div_8 - 15); + else + char <= s_stop (column_div_8 - 15); + end if; + elsif column_div_8 < s_after'length then + char <= s_after (column_div_8); + else + char <= to_short_character (' '); + end if; + + + else + -- Status subsegment. + if column_div_8 < 125 then + char <= to_short_character (' '); + else + if is_reading_active = '1' then + char <= s_reading_active (column_div_8 - 125); + else + char <= s_reading_stopped (column_div_8 - 125); + end if; + end if; + end if; + + end if; + end if; + end process; + + process (char_pixel, segment, subsegment) is + begin + if char_pixel = '1' then + if segment = 14 then + if subsegment = 0 then + vout <= "11100000"; + elsif subsegment = 1 then + vout <= "00011100"; + elsif subsegment = 2 then + vout <= "00000011"; + else + vout <= "11111111"; + end if; + else + vout <= "11111111"; + end if; + else + vout <= "00000000"; + end if; + end process; +end behavioral; + diff --git a/src/single_debouncer.vhd b/src/single_debouncer.vhd new file mode 100644 index 0000000..4f8ba59 --- /dev/null +++ b/src/single_debouncer.vhd @@ -0,0 +1,45 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 15:03:57 05/24/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity single_debouncer is + generic ( + n : natural := 5000 + ); + port ( + nrst : in std_logic; + clk : in std_logic; + input : in std_logic; + output : out std_logic + ); +end single_debouncer; + +architecture behavioral of single_debouncer is + signal counter: natural range 0 to n := 0; + signal output2: std_logic := '0'; +begin + output <= output2; + process (clk, nrst) is + begin + if nrst = '0' then + counter <= 0; + output2 <= '0'; + elsif rising_edge (clk) then + if counter >= n then + if output2 /= input then + output2 <= input; + counter <= 0; + end if; + else + counter <= counter + 1; + end if; + end if; + end process; +end behavioral; + + diff --git a/src/tests/test_bits_aggregator.vhd b/src/tests/test_bits_aggregator.vhd new file mode 100644 index 0000000..2c77bfd --- /dev/null +++ b/src/tests/test_bits_aggregator.vhd @@ -0,0 +1,171 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:19:19 05/27/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_bits_aggregator.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: bits_aggregator +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; +USE ieee.numeric_std.ALL; + +ENTITY test_bits_aggregator IS +END test_bits_aggregator; + +ARCHITECTURE behavior OF test_bits_aggregator IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT bits_aggregator + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + flush_and_return_to_zero : IN std_logic; + write_enable : IN std_logic; + red_value : IN std_logic; + green_value : IN std_logic; + blue_value : IN std_logic; + wea : OUT std_logic; + addra : OUT std_logic_vector(12 downto 0); + dina : OUT std_logic_vector(8 downto 0) + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal flush_and_return_to_zero : std_logic := '0'; + signal write_enable : std_logic := '0'; + signal red_value : std_logic := '0'; + signal green_value : std_logic := '0'; + signal blue_value : std_logic := '0'; + + --Outputs + signal wea : std_logic; + signal addra : std_logic_vector(12 downto 0); + signal dina : std_logic_vector(8 downto 0); + + + signal rgb : std_logic_vector (2 downto 0) := (others => '0'); + + -- Clock period definitions + constant clk108_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: bits_aggregator PORT MAP ( + nrst => nrst, + clk108 => clk108, + flush_and_return_to_zero => flush_and_return_to_zero, + write_enable => write_enable, + red_value => red_value, + green_value => green_value, + blue_value => blue_value, + wea => wea, + addra => addra, + dina => dina + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + wait for clk108_period/2; + end process; + + + -- Stimulus process + stim_proc: process + variable mod3 : integer range 0 to 3 := 0; + variable sent_row : std_logic_vector (8 downto 0) := (others => '0'); + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + + wait for clk108_period*10; + + + while true loop + assert mod3 = 0 report "Unit-test internal error"; + for i in 1 to 99 loop + wait for clk108_period; + red_value <= rgb (0); + green_value <= rgb (1); + blue_value <= rgb (2); + sent_row ((mod3 * 3) + 2 downto mod3 * 3) := rgb; + wait for clk108_period; + write_enable <= '1'; + wait for clk108_period; + write_enable <= '0'; + wait for clk108_period; + rgb <= rgb + 1; + + mod3 := mod3 + 1; + if mod3 = 3 then + mod3 := 0; + assert sent_row = dina report "Entity generated improper memory input"; + end if; + end loop; + + assert mod3 = 0 report "Unit-test internal error"; + + -- Testing flush_and_return_to_zero + wait for clk108_period * 10; + write_enable <= '1'; + flush_and_return_to_zero <= '1'; + wait for clk108_period; + write_enable <= '0'; + flush_and_return_to_zero <= '0'; + wait for clk108_period; + assert "000000" & (rgb - 1) = dina report "Entity generated improper memory input after flushing"; + + + -- Now writing 3 bytes. After successbul flush they should be sent to memory row 0 + write_enable <= '1'; + wait for clk108_period; + assert addra /= "0000000000000" report "Address after flushing went to zero too fast"; + wait for clk108_period; + assert addra /= "0000000000000" report "Address after flushing went to zero too fast"; + wait for clk108_period; + write_enable <= '0'; + assert addra = "0000000000000" report "Address after flushing didn't go to zero."; + assert dina = (rgb - 1) & (rgb - 1) & (rgb - 1) report "Improper dina signal after flushing and writing full word."; + + + --assert addra = "0000000000000" report "Address after flushing is not zero"; + + + end loop; + + + wait; + end process; + +END; diff --git a/src/tests/test_char_rom_mux.vhd b/src/tests/test_char_rom_mux.vhd new file mode 100644 index 0000000..393c38d --- /dev/null +++ b/src/tests/test_char_rom_mux.vhd @@ -0,0 +1,160 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:31:59 05/28/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_char_rom_mux.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: char_rom_mux +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + +ENTITY test_char_rom_mux IS +END test_char_rom_mux; + +ARCHITECTURE behavior OF test_char_rom_mux IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT char_rom_mux + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + active_pixgen_source : IN PIXGEN_SOURCE_T; + time_base_char : IN short_character; + time_base_char_pos_x : IN integer range 0 to 7; + time_base_char_pos_y : IN integer range 0 to 15; + settings_char : IN short_character; + settings_char_pos_x : IN integer range 0 to 7; + settings_char_pos_y : IN integer range 0 to 15; + char_pixel : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal active_pixgen_source : PIXGEN_SOURCE_T := BLANK_PIXGEN_T; + signal time_base_char : short_character := short_character'val (0); + signal time_base_char_pos_x : integer range 0 to 7 := 0; + signal time_base_char_pos_y : integer range 0 to 15 := 0; + signal settings_char : short_character := short_character'val (0); + signal settings_char_pos_x : integer range 0 to 7 := 0; + signal settings_char_pos_y : integer range 0 to 15 := 0; + + --Outputs + signal char_pixel : std_logic; + + -- Clock period definitions + constant clk108_period : time := 10 ns; + + type chars_8 is array (0 to 7) of character; + + type letter is array (0 to 15) of chars_8; + constant a_letter : letter := + ( "--------", + "--------", + "---X----", + "--XXX---", + "-XX-XX--", + "XX---XX-", + "XX---XX-", + "XXXXXXX-", + "XX---XX-", + "XX---XX-", + "XX---XX-", + "XX---XX-", + "--------", + "--------", + "--------", + "--------" ); + + + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: char_rom_mux PORT MAP ( + nrst => nrst, + clk108 => clk108, + active_pixgen_source => active_pixgen_source, + time_base_char => time_base_char, + time_base_char_pos_x => time_base_char_pos_x, + time_base_char_pos_y => time_base_char_pos_y, + settings_char => settings_char, + settings_char_pos_x => settings_char_pos_x, + settings_char_pos_y => settings_char_pos_y, + char_pixel => char_pixel + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + wait for clk108_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + wait for clk108_period*10; + + -- Testing memory against some random character: 'A' + active_pixgen_source <= TIME_BASE_PIXGEN_T; + time_base_char <= 'A'; + time_base_char_pos_y <= 0; + for y in 0 to 15 loop + time_base_char_pos_x <= 0; + for x in 0 to 7 loop + wait for clk108_period; + if char_pixel = '1' then + assert a_letter (y)(x) = 'X' report "char_pixel should be '1', but is not"; + else + assert a_letter (y)(x) = '-' report "char_pixel should be '0', but is not"; + end if; + + if time_base_char_pos_x = 7 then + time_base_char_pos_x <= 0; + else + time_base_char_pos_x <= time_base_char_pos_x + 1; + end if; + end loop; + if time_base_char_pos_y = 15 then + time_base_char_pos_y <= 0; + else + time_base_char_pos_y <= time_base_char_pos_y + 1; + end if; + end loop; + wait; + end process; + +END; diff --git a/src/tests/test_clock_divider.vhd b/src/tests/test_clock_divider.vhd new file mode 100644 index 0000000..3ed4e9b --- /dev/null +++ b/src/tests/test_clock_divider.vhd @@ -0,0 +1,97 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:15:48 05/28/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_clock_divider.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: divider +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_clock_divider IS +END test_clock_divider; + +ARCHITECTURE behavior OF test_clock_divider IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT divider + GENERIC (n: natural range 1 to 2147483647 := 5); + PORT( + clk_in : IN std_logic; + nrst : IN std_logic; + clk_out : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk_in : std_logic := '0'; + signal nrst : std_logic := '0'; + + --Output + signal clk_out : std_logic; + + -- Clock period definitions + constant clk_in_period : time := 10 ns; + + constant c : character := character'val(0); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: divider PORT MAP ( + clk_in => clk_in, + nrst => nrst, + clk_out => clk_out + ); + + -- Clock process definitions + clk_in_process :process + begin + clk_in <= '0'; + wait for clk_in_period/2; + clk_in <= '1'; + wait for clk_in_period/2; + end process; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + wait for clk_in_period*10; + + + -- insert stimulus here + + wait; + end process; + +END; diff --git a/src/tests/test_compiler_error.vhd b/src/tests/test_compiler_error.vhd new file mode 100644 index 0000000..bbb85d5 --- /dev/null +++ b/src/tests/test_compiler_error.vhd @@ -0,0 +1,28 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +ENTITY test_compiler_error IS +END test_compiler_error; + +ARCHITECTURE behavior OF test_compiler_error IS + signal output : std_logic_vector(7 downto 0); +BEGIN + stim_proc: process + variable i:integer; + begin + -- Release version : ISE 13.1 lin64 + -- Application Version: O.40d + -- Behavioral simulation + -- + -- Uncomment the below two lines to get an Internal Compiler Error + --for i in 0 to 9 loop + --end loop; + + assert output = (others => '1') report "Should be equal '1', but is not"; + end process; +END; + + +-- Compiler complains: +-- FATAL_ERROR:Simulator:CompilerAssert.h:40:1.65 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 5262 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. diff --git a/src/tests/test_debouncer.vhd b/src/tests/test_debouncer.vhd new file mode 100644 index 0000000..5cc3e6a --- /dev/null +++ b/src/tests/test_debouncer.vhd @@ -0,0 +1,132 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:28:48 05/24/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_debouncer.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: debouncer +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_debouncer IS +END test_debouncer; + +ARCHITECTURE behavior OF test_debouncer IS + + -- Component Declaration for the Unit Under Test (UUT) + constant n : natural := 5; + constant signal_width : natural := 8; + + COMPONENT debouncer + GENERIC ( + n : natural := n; + signal_width : natural := signal_width + ); + PORT( + nrst : IN std_logic; + clk : IN std_logic; + input : IN std_logic_vector(signal_width - 1 downto 0); + output : OUT std_logic_vector(signal_width - 1 downto 0) + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk : std_logic := '0'; + signal input : std_logic_vector(signal_width - 1 downto 0) := (others => '0'); + + --Outputs + signal output : std_logic_vector(signal_width - 1 downto 0); + signal ones : std_logic_vector(signal_width - 1 downto 0) := (others => '1'); + signal zeros : std_logic_vector(signal_width - 1 downto 0) := (others => '0'); + + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: debouncer PORT MAP ( + nrst => nrst, + clk => clk, + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + variable i:integer; + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + + wait for clk_period * 10; + + while true loop + for i in 0 to 9 loop + input <= not input; + wait for clk_period; + assert output = input report "Should be equal, but is not"; + wait for clk_period * (n + 1); + end loop; + + input <= zeros; + wait for clk_period * (n + 1); + input <= ones; + wait for clk_period; + for i in 1 to n loop + input <= zeros; + wait for clk_period / 2; + assert output = ones report "Should be equal '1', but is not"; + input <= ones; + wait for clk_period / 2; + assert output = ones report "Should be equal '1', but is not"; + end loop; + + wait for clk_period * (n + 1); + + end loop; + + wait; + end process; + +END; diff --git a/src/tests/test_n_cycles_delayer.vhd b/src/tests/test_n_cycles_delayer.vhd new file mode 100644 index 0000000..382fc0c --- /dev/null +++ b/src/tests/test_n_cycles_delayer.vhd @@ -0,0 +1,114 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:45:56 05/22/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_n_cycles_delayer.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: n_cycles_delayer +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_n_cycles_delayer IS +END test_n_cycles_delayer; + +ARCHITECTURE behavior OF test_n_cycles_delayer IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT n_cycles_delayer + GENERIC ( + n : integer range 1 to 1024 := 5; + signal_width : integer range 1 to 1024 := 8 + ); + PORT( + nrst : IN std_logic; + clk : IN std_logic; + input : IN std_logic_vector(7 downto 0); + output : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk : std_logic := '0'; + signal input : std_logic_vector(7 downto 0) := (others => '0'); + + --Outputs + signal output : std_logic_vector(7 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: n_cycles_delayer + + PORT MAP ( + nrst => nrst, + clk => clk, + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process is + variable i, j : std_logic_vector (7 downto 0); + begin + -- hold reset state for 105 ns. + nrst <= '0'; + wait for clk_period * 10; + nrst <= '1'; + wait for clk_period * 10; + + i := (others => '0'); + while true loop + i := i + 1; + input <= i; + for j in 0 to 3 loop + wait for clk_period; + assert output /= input report "Should not match"; + end loop; + wait for clk_period * 2; + assert output = input report "Should match"; + end loop; + wait; + end process; + +END; diff --git a/src/tests/test_oscilloscope_display.vhd b/src/tests/test_oscilloscope_display.vhd new file mode 100644 index 0000000..9fa1674 --- /dev/null +++ b/src/tests/test_oscilloscope_display.vhd @@ -0,0 +1,141 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:01:11 05/24/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_oscilloscope_display.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: oscilloscope_display +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.numeric_std.ALL; +USE work.types.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_oscilloscope_display IS +END test_oscilloscope_display; + +ARCHITECTURE behavior OF test_oscilloscope_display IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT oscilloscope_display + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + is_reading_active : in std_logic; + trigger_event : in TRIGGER_EVENT_T; + red_enable : in std_logic; + green_enable : in std_logic; + blue_enable : in std_logic; + continue_after_reading : in std_logic; + time_resolution : in integer range 0 to 15; + addrb : OUT std_logic_vector(12 downto 0); + doutb : IN std_logic_vector(8 downto 0); + vout : OUT std_logic_vector(7 downto 0); + vsync : OUT std_logic; + hsync : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal doutb : std_logic_vector(8 downto 0) := (others => '0'); + + + + signal is_reading_active : std_logic := '0'; + signal trigger_event : TRIGGER_EVENT_T := BUTTON_TRIGGER_T; + signal red_enable : std_logic := '1'; + signal green_enable : std_logic := '1'; + signal blue_enable : std_logic := '1'; + signal continue_after_reading : std_logic := '0'; + signal time_resolution : integer range 0 to 15; + + + --Outputs + signal addrb : std_logic_vector(12 downto 0); + signal vout : std_logic_vector(7 downto 0); + signal vsync : std_logic; + signal hsync : std_logic; + + -- Clock period definitions + constant clk108_period : time := 10 ns; + + -- Locals + signal clock_periods : std_logic_vector (15 downto 0) := (others => '0'); + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: oscilloscope_display PORT MAP ( + nrst => nrst, + clk108 => clk108, + is_reading_active => is_reading_active, + trigger_event => trigger_event, + red_enable => red_enable, + green_enable => green_enable, + blue_enable => blue_enable, + continue_after_reading => continue_after_reading, + time_resolution => time_resolution, + addrb => addrb, + doutb => doutb, + vout => vout, + vsync => vsync, + hsync => hsync + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + if nrst = '1' then + clock_periods <= clock_periods + 1; + end if; + wait for clk108_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for clk108_period * 10; + nrst <= '1'; + + wait for clk108_period * 10; + + -- insert stimulus here + + wait; + end process; + +END; diff --git a/src/tests/test_reader.vhd b/src/tests/test_reader.vhd new file mode 100644 index 0000000..851c3cf --- /dev/null +++ b/src/tests/test_reader.vhd @@ -0,0 +1,178 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:54:34 05/24/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_reader.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: reader +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY test_reader IS +END test_reader; + +ARCHITECTURE behavior OF test_reader IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT reader + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + input_red : IN std_logic; + input_green : IN std_logic; + input_blue : IN std_logic; + is_reading_active : IN std_logic; + time_resolution : IN integer range 0 to 15; + overflow_indicator : OUT std_logic; + flush_and_return_to_zero : OUT std_logic; + write_enable : OUT std_logic; + red_value : OUT std_logic; + green_value : OUT std_logic; + blue_value : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal input_red : std_logic := '0'; + signal input_green : std_logic := '0'; + signal input_blue : std_logic := '0'; + signal is_reading_active : std_logic := '0'; + signal time_resolution : integer range 0 to 15 := 0; + + --Outputs + signal overflow_indicator : std_logic; + signal flush_and_return_to_zero : std_logic; + signal write_enable : std_logic; + signal red_value : std_logic; + signal green_value : std_logic; + signal blue_value : std_logic; + + -- Clock period definitions + constant clk108_period : time := 10 ns; + + signal was_there_an_overflow : std_logic := '0'; + signal please_reset_overflow : std_logic := '0'; + signal currently_doing_nothing : std_logic := '0'; + + signal write_enable_count_between_flushes : natural := 0; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: reader PORT MAP ( + nrst => nrst, + clk108 => clk108, + input_red => input_red, + input_green => input_green, + input_blue => input_blue, + is_reading_active => is_reading_active, + time_resolution => time_resolution, + overflow_indicator => overflow_indicator, + flush_and_return_to_zero => flush_and_return_to_zero, + write_enable => write_enable, + red_value => red_value, + green_value => green_value, + blue_value => blue_value + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + wait for clk108_period/2; + end process; + + simulate_trigger : process (nrst, clk108) is + begin + if nrst = '0' then + is_reading_active <= '1'; + elsif rising_edge (clk108) then + if please_reset_overflow = '1' then + was_there_an_overflow <= '0'; + is_reading_active <= '1'; + time_resolution <= (time_resolution + 1) mod 16; + elsif was_there_an_overflow = '0' then + if overflow_indicator = '1' then + was_there_an_overflow <= '1'; + is_reading_active <= '0'; + end if; + end if; + end if; + end process; + + restart_was_there_an_overflow: process is + begin + while true loop + if was_there_an_overflow = '1' then + wait for clk108_period * 25; + currently_doing_nothing <= '1'; + wait for clk108_period; + currently_doing_nothing <= '0'; + wait for clk108_period * 25; + please_reset_overflow <= '1'; + end if; + wait for clk108_period; + please_reset_overflow <= '0'; + end loop; + end process; + + + write_enable_counter: process (nrst, clk108) is + begin + if nrst = '0' then + write_enable_count_between_flushes <= 0; + elsif rising_edge (clk108) then + if currently_doing_nothing = '1' then + assert write_enable_count_between_flushes = 14 * 1280 report "Improper number of write_enable ones."; + write_enable_count_between_flushes <= 0; + elsif write_enable = '1' then + write_enable_count_between_flushes <= write_enable_count_between_flushes + 1; + end if; + end if; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + + + wait for clk108_period*10; + + -- insert stimulus here + + wait; + end process; + +END; diff --git a/src/tests/test_screen_position_gen.vhd b/src/tests/test_screen_position_gen.vhd new file mode 100644 index 0000000..1977f78 --- /dev/null +++ b/src/tests/test_screen_position_gen.vhd @@ -0,0 +1,152 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:35:03 05/28/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_screen_position_gen.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: screen_position_gen +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE work.types.ALL; + +ENTITY test_screen_position_gen IS +END test_screen_position_gen; + +ARCHITECTURE behavior OF test_screen_position_gen IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT screen_position_gen + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + vblank : IN std_logic; + in_line_change : IN std_logic; + in_page_change : IN std_logic; + in_column : IN integer range 0 to 1279; + in_column_change : IN std_logic; + segment : OUT integer range 0 to 15; + segment_change : OUT std_logic; + subsegment : OUT integer range 0 to 3; + subsegment_change : OUT std_logic; + line : OUT integer range 0 to 15; + out_line_change : OUT std_logic; + out_column : OUT integer range 0 to 1279; + out_column_change : OUT std_logic; + out_page_change : OUT std_logic; + active_pixgen_source : OUT PIXGEN_SOURCE_T + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal vblank : std_logic := '0'; + signal in_line_change : std_logic := '0'; + signal in_page_change : std_logic := '0'; + signal in_column : integer range 0 to 1279 := 0; + signal in_column_change : std_logic := '0'; + + --Outputs + signal segment : integer range 0 to 15; + signal segment_change : std_logic; + signal subsegment : integer range 0 to 3; + signal subsegment_change : std_logic; + signal line : integer range 0 to 15; + signal out_line_change : std_logic; + signal out_column : integer range 0 to 1279; + signal out_column_change : std_logic; + signal out_page_change : std_logic; + signal active_pixgen_source : PIXGEN_SOURCE_T; + + -- Clock period definitions + constant clk108_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: screen_position_gen PORT MAP ( + nrst => nrst, + clk108 => clk108, + vblank => vblank, + in_line_change => in_line_change, + in_page_change => in_page_change, + in_column => in_column, + in_column_change => in_column_change, + segment => segment, + segment_change => segment_change, + subsegment => subsegment, + subsegment_change => subsegment_change, + line => line, + out_line_change => out_line_change, + out_column => out_column, + out_column_change => out_column_change, + out_page_change => out_page_change, + active_pixgen_source => active_pixgen_source + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + wait for clk108_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + wait for clk108_period*10; + + while true loop + in_page_change <= '1'; + for x_line in 0 to 1279 loop + vblank <= '0'; + in_line_change <= '1'; + in_column_change <= '1'; + for x_column in 0 to 1279 loop + in_column <= x_column; + wait for clk108_period; + in_line_change <= '0'; + in_page_change <= '0'; + end loop; + in_column_change <= '0'; + vblank <= '1'; + wait for clk108_period * 1000; + end loop; + + wait for clk108_period * 10000; + end loop; + + wait; + end process; + +END; diff --git a/src/tests/test_single_debouncer.vhd b/src/tests/test_single_debouncer.vhd new file mode 100644 index 0000000..1ceb37a --- /dev/null +++ b/src/tests/test_single_debouncer.vhd @@ -0,0 +1,126 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:08:56 05/24/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_single_debouncer.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: single_debouncer +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_single_debouncer IS +END test_single_debouncer; + +ARCHITECTURE behavior OF test_single_debouncer IS + + -- Component Declaration for the Unit Under Test (UUT) + + constant n : integer := 5; + + COMPONENT single_debouncer + GENERIC (n : natural := n); + PORT( + nrst : IN std_logic; + clk : IN std_logic; + input : IN std_logic; + output : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk : std_logic := '0'; + signal input : std_logic := '0'; + + --Outputs + signal output : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: single_debouncer + PORT MAP ( + nrst => nrst, + clk => clk, + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + variable i:integer; + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + + wait for clk_period * 10; + + while true loop + for i in 0 to 9 loop + input <= not input; + wait for clk_period; + assert output = input report "Should be equal, but is not"; + wait for clk_period * (n + 1); + end loop; + + input <= '0'; + wait for clk_period * (n + 1); + input <= '1'; + wait for clk_period; + for i in 1 to n loop + input <= '0'; + wait for clk_period / 2; + assert output = '1' report "Should be equal '1', but is not"; + input <= '1'; + wait for clk_period / 2; + assert output = '1' report "Should be equal '1', but is not"; + end loop; + + wait for clk_period * (n + 1); + + end loop; + + wait; + end process; + +END; diff --git a/src/tests/test_trace_memory.vhd b/src/tests/test_trace_memory.vhd new file mode 100644 index 0000000..88b31aa --- /dev/null +++ b/src/tests/test_trace_memory.vhd @@ -0,0 +1,130 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:28:51 05/22/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trace_memory.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: trace_memory +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_arith.ALL; + +ENTITY test_trace_memory IS +END test_trace_memory; + +ARCHITECTURE behavior OF test_trace_memory IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT trace_memory + PORT( + clka : IN std_logic; + wea : IN std_logic_vector(0 downto 0); + addra : IN std_logic_vector(12 downto 0); + dina : IN std_logic_vector(8 downto 0); + clkb : IN std_logic; + rstb : IN std_logic; + addrb : IN std_logic_vector(12 downto 0); + doutb : OUT std_logic_vector(8 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clka : std_logic := '0'; + signal wea : std_logic_vector(0 downto 0) := (others => '0'); + signal addra : std_logic_vector(12 downto 0) := (others => '0'); + signal dina : std_logic_vector(8 downto 0) := (others => '0'); + signal clkb : std_logic := '0'; + signal rstb : std_logic := '0'; + signal addrb : std_logic_vector(12 downto 0) := (others => '0'); + + --Outputs + signal doutb : std_logic_vector(8 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: trace_memory PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + rstb => rstb, + addrb => addrb, + doutb => doutb + ); + + clk_process :process + begin + clka <= '0'; + clkb <= '0'; + wait for clk_period/2; + clka <= '1'; + clkb <= '1'; + wait for clk_period/2; + end process; + + + + -- Stimulus process + stim_proc: process + variable i: integer; + begin + -- hold reset state for 100 ns. + rstb <= '1'; + wait for 100 ns; + rstb <= '0'; + wait for clk_period * 10; + + addra <= "0000000000000"; + dina <= "010101101"; + wea <= "1"; + wait for clk_period; + wea <= "0"; + + wait for clk_period * 10; + + wea <= "1"; + for i in 0 to 20 loop + dina <= conv_std_logic_vector (i, 9); + addra <= conv_std_logic_vector (i, 13); + wait for clk_period; + end loop; + wea <= "0"; + + wait for clk_period * 10; + + for i in 0 to 20 loop + addrb <= conv_std_logic_vector (i, 13); + wait for clk_period; + end loop; + + wait; + end process; + +END; diff --git a/src/tests/test_trace_pixgen.vhd b/src/tests/test_trace_pixgen.vhd new file mode 100644 index 0000000..921f623 --- /dev/null +++ b/src/tests/test_trace_pixgen.vhd @@ -0,0 +1,185 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:17:19 05/28/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trace_pixgen.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: trace_pixgen +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + + +ENTITY test_trace_pixgen IS +END test_trace_pixgen; + +ARCHITECTURE behavior OF test_trace_pixgen IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT trace_pixgen + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + segment : IN integer range 0 to 15; + segment_change : IN std_logic; + subsegment : IN integer range 0 to 3; + subsegment_change : IN std_logic; + line : IN integer range 0 to 15; + line_change : IN std_logic; + column : IN integer range 0 to 1279; + column_change : IN std_logic; + page_change : IN std_logic; + active_pixgen_source : IN PIXGEN_SOURCE_T; + doutb : IN std_logic_vector(8 downto 0); + addrb : OUT std_logic_vector(12 downto 0); + vout : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal segment : integer range 0 to 15 := 0; + signal segment_change : std_logic := '0'; + signal subsegment : integer range 0 to 3 := 0; + signal subsegment_change : std_logic := '0'; + signal line : integer range 0 to 15 := 0; + signal line_change : std_logic := '0'; + signal column : integer range 0 to 1279 := 0; + signal column_change : std_logic := '0'; + signal page_change : std_logic := '0'; + signal active_pixgen_source : PIXGEN_SOURCE_T := TRACE_PIXGEN_T; + signal doutb : std_logic_vector(8 downto 0) := (others => '0'); + + --Outputs + signal addrb : std_logic_vector(12 downto 0); + signal vout : std_logic_vector(7 downto 0); + + -- Clock period definitions + constant clk108_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: trace_pixgen PORT MAP ( + nrst => nrst, + clk108 => clk108, + segment => segment, + segment_change => segment_change, + subsegment => subsegment, + subsegment_change => subsegment_change, + line => line, + line_change => line_change, + column => column, + column_change => column_change, + page_change => page_change, + active_pixgen_source => active_pixgen_source, + doutb => doutb, + addrb => addrb, + vout => vout + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + wait for clk108_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + + wait for clk108_period*10; + + while true loop + for x_segment in 0 to 15 loop + for x_subsegment in 0 to 3 loop + for x_line in 0 to 15 loop + if x_segment = 14 or x_segment = 15 then + active_pixgen_source <= SETTINGS_PIXGEN_T; + else + if x_subsegment = 3 then + active_pixgen_source <= TIME_BASE_PIXGEN_T; + else + active_pixgen_source <= TRACE_PIXGEN_T; + end if; + end if; + for x_column in 0 to 1279 loop + column_change <= '1'; + segment <= x_segment; + subsegment <= x_subsegment; + line <= x_line; + column <= x_column; + if x_column = 0 then + line_change <= '1'; + if x_line = 0 then + subsegment_change <= '1'; + if x_subsegment = 0 then + segment_change <= '1'; + if x_segment = 0 then + page_change <= '1'; + else + page_change <= '0'; + end if; + else + segment_change <= '0'; + page_change <= '0'; + end if; + else + subsegment_change <= '0'; + segment_change <= '0'; + page_change <= '0'; + end if; + else + line_change <= '0'; + subsegment_change <= '0'; + segment_change <= '0'; + page_change <= '0'; + end if; + + wait for clk108_period; + + end loop; + column_change <= '0'; + active_pixgen_source <= BLANK_PIXGEN_T; + wait for clk108_period * 1000; + end loop; + end loop; + end loop; + wait for clk108_period * 10000; + end loop; + wait; + end process; + +END; diff --git a/src/tests/test_trigger.vhd b/src/tests/test_trigger.vhd new file mode 100644 index 0000000..ab1e62a --- /dev/null +++ b/src/tests/test_trigger.vhd @@ -0,0 +1,184 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:36:40 05/24/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trigger.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: trigger +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE work.types.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY test_trigger IS +END test_trigger; + +ARCHITECTURE behavior OF test_trigger IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT trigger + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + trigger_btn : IN std_logic; + trigger_event : IN TRIGGER_EVENT_T; + red_enable : IN std_logic; + green_enable : IN std_logic; + blue_enable : IN std_logic; + continue_after_reading : IN std_logic; + red_input : IN std_logic; + green_input : IN std_logic; + blue_input : IN std_logic; + overflow_indicator : IN std_logic; + red_output : OUT std_logic; + green_output : OUT std_logic; + blue_output : OUT std_logic; + is_reading_active : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '0'; + signal clk108 : std_logic := '0'; + signal trigger_btn : std_logic := '0'; + signal trigger_event : TRIGGER_EVENT_T := BUTTON_TRIGGER_T; + signal red_enable : std_logic := '0'; + signal green_enable : std_logic := '0'; + signal blue_enable : std_logic := '0'; + signal continue_after_reading : std_logic := '0'; + signal red_input : std_logic := '0'; + signal green_input : std_logic := '0'; + signal blue_input : std_logic := '0'; + signal overflow_indicator : std_logic := '0'; + + --Outputs + signal red_output : std_logic; + signal green_output : std_logic; + signal blue_output : std_logic; + signal is_reading_active : std_logic; + + -- Clock period definitions + constant clk108_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: trigger PORT MAP ( + nrst => nrst, + clk108 => clk108, + trigger_btn => trigger_btn, + trigger_event => trigger_event, + red_enable => red_enable, + green_enable => green_enable, + blue_enable => blue_enable, + continue_after_reading => continue_after_reading, + red_input => red_input, + green_input => green_input, + blue_input => blue_input, + overflow_indicator => overflow_indicator, + red_output => red_output, + green_output => green_output, + blue_output => blue_output, + is_reading_active => is_reading_active + ); + + -- Clock process definitions + clk108_process :process + begin + clk108 <= '0'; + wait for clk108_period/2; + clk108 <= '1'; + wait for clk108_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + nrst <= '0'; + wait for 100 ns; + nrst <= '1'; + + wait for clk108_period; + + + wait for clk108_period * 10; + trigger_btn <= '1'; + wait for clk108_period; + trigger_btn <= '0'; + + assert is_reading_active = '1' report "Reading should be active"; + + + red_enable <= '1'; + green_enable <= '0'; + blue_enable <= '1'; + red_input <= '1'; + green_input <= '1'; + blue_input <= '0'; + + wait for clk108_period; + assert red_output = '1' report "Red should be active"; + assert green_output = '0' report "Green should not be active"; + assert blue_output = '0' report "Blue should not be active"; + wait for clk108_period; + red_input <= '0'; + green_input <= '0'; + blue_input <= '0'; + + + wait for clk108_period * 10; + + continue_after_reading <= '0'; + overflow_indicator <= '1'; + wait for clk108_period; + assert is_reading_active = '0' report "Reading should not be active; issued an overflow"; + overflow_indicator <= '0'; + + wait for clk108_period * 10; + + trigger_event <= GREEN_TRIGGER_T; + green_input <= '1'; + wait for clk108_period; + green_input <= '0'; + wait for clk108_period; + assert is_reading_active = '1' report "Reading should be active; trigger on rising edge at green"; + + + wait for clk108_period * 10; + trigger_btn <= '1'; + wait for clk108_period; + trigger_btn <= '0'; + assert is_reading_active = '0' report "Reading should not be active; stopped it with button"; + + + wait; + end process; + +END; diff --git a/src/tests/test_types.vhd b/src/tests/test_types.vhd new file mode 100644 index 0000000..0d05029 --- /dev/null +++ b/src/tests/test_types.vhd @@ -0,0 +1,31 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE work.types.all; + +ENTITY test_types IS +END test_types; + +ARCHITECTURE behavior OF test_types IS + + signal tested_num : integer range 0 to 127; + signal tested_num2 : integer range 0 to 127; + signal tested_short_char : short_character; + +BEGIN + stim_proc: process + begin + for i in 0 to 127 loop + tested_num <= i; + tested_short_char <= character_conv_table (i); + wait for 1 ns; + tested_num2 <= short_character'pos (tested_short_char); + wait for 1 ns; + assert tested_num = tested_num2; + assert tested_short_char = short_character'val (i); + end loop; + wait; + end process; + +END; diff --git a/src/tests/test_vga_controller_1280_1024.vhd b/src/tests/test_vga_controller_1280_1024.vhd new file mode 100644 index 0000000..2fb98a0 --- /dev/null +++ b/src/tests/test_vga_controller_1280_1024.vhd @@ -0,0 +1,101 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:00:31 05/17/2011 +-- Design Name: +-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_vga_controller_1280_1024.vhd +-- Project Name: oscilloscope +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: vga_controller_1280_1024 +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.ALL; +use ieee.numeric_std.all; + + +ENTITY test_vga_controller_1280_1024 IS +END test_vga_controller_1280_1024; + +ARCHITECTURE behavior OF test_vga_controller_1280_1024 IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT vga_controller_1280_1024 + PORT( + nrst : IN std_logic; + clk108 : IN std_logic; + hsync : OUT std_logic; + vsync : OUT std_logic; + vblank : OUT std_logic; + line_change : OUT std_logic; + page_change : OUT std_logic; + column : out integer range 0 to 1279; + column_change : out std_logic + ); + END COMPONENT; + + + --Inputs + signal nrst : std_logic := '1'; + signal clk108 : std_logic := '0'; + + --Outputs + signal hsync : std_logic; + signal vsync : std_logic; + signal vblank : std_logic; + signal line_change : std_logic; + signal page_change : std_logic; + signal column : integer range 0 to 1279; + signal column_change : std_logic; + + + + signal clock_periods : std_logic_vector (31 downto 0) := (others => '0'); + + -- Clock period definitions + constant clk108_period : time := 9.25925926 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: vga_controller_1280_1024 PORT MAP ( + nrst => nrst, + clk108 => clk108, + hsync => hsync, + vsync => vsync, + vblank => vblank, + line_change => line_change, + page_change => page_change, + column => column, + column_change => column_change + ); + + -- Clock process definitions + clk108_process : process + begin + clk108 <= '1'; + wait for clk108_period/2; + clk108 <= '0'; + wait for clk108_period/2; + clock_periods <= clock_periods + 1; + end process; + +END; diff --git a/src/time_base_pixgen.vhd b/src/time_base_pixgen.vhd new file mode 100644 index 0000000..5d3865c --- /dev/null +++ b/src/time_base_pixgen.vhd @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 20:16:43 05/22/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + +entity time_base_pixgen is + port ( + nrst : in std_logic; + clk108 : in std_logic; + segment : in integer range 0 to 15; + segment_change : in std_logic; + subsegment : in integer range 0 to 3; + subsegment_change : in std_logic; + line : in integer range 0 to 15; + line_change : in std_logic; + column : in integer range 0 to 1279; + column_change : in std_logic; + page_change : in std_logic; + active_pixgen_source : in PIXGEN_SOURCE_T; + char : out short_character; + char_pixel : in std_logic; + vout : out std_logic_vector (7 downto 0) + ); +end time_base_pixgen; + +architecture behavioral of time_base_pixgen is + signal output : std_logic; +begin + char <= to_short_character (NUL); + process (clk108, nrst) is + begin + if nrst = '0' then + output <= '0'; + elsif rising_edge (clk108) then + if line = 2 or line = 3 or line = 4 or line = 11 or line = 12 or line = 13 then + if column mod 128 = 127 then + output <= '1'; + else + output <= '0'; + end if; + elsif line = 5 or line = 10 then + if column mod 64 = 63 then + output <= '1'; + else + output <= '0'; + end if; + elsif line = 6 or line = 7 or line = 8 or line = 9 then + if column mod 16 = 15 then + output <= '1'; + else + output <= '0'; + end if; + else + output <= '1'; + end if; + end if; + end process; + + process (clk108, nrst) is + begin + if nrst = '0' then + vout <= "00000000"; + elsif rising_edge (clk108) then + if output = '1' then + vout <= "11111111"; + else + vout <= "00000000"; + end if; + end if; + end process; +end behavioral; diff --git a/src/trace_pixgen.vhd b/src/trace_pixgen.vhd new file mode 100644 index 0000000..a744a99 --- /dev/null +++ b/src/trace_pixgen.vhd @@ -0,0 +1,162 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 20:16:43 05/22/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.types.all; + +entity trace_pixgen is + port ( + nrst : in std_logic; + clk108 : in std_logic; + segment : in integer range 0 to 15; + segment_change : in std_logic; + subsegment : in integer range 0 to 3; + subsegment_change : in std_logic; + line : in integer range 0 to 15; + line_change : in std_logic; + column : in integer range 0 to 1279; + column_change : in std_logic; + page_change : in std_logic; + active_pixgen_source : in PIXGEN_SOURCE_T; + currently_read_screen_segment : in natural range 0 to 13; + currently_read_screen_column : in natural range 0 to 1279; + time_resolution : in integer range 0 to 15; + is_reading_active : in std_logic; + doutb : in std_logic_vector (8 downto 0); + addrb : out std_logic_vector (12 downto 0); + vout : out std_logic_vector (7 downto 0) + ); +end trace_pixgen; + +architecture behavioral of trace_pixgen is + signal position_div_3 : integer range 0 to 5973; + signal position_mod_3 : integer range 0 to 2; + + signal delayed_active_pixgen_source : PIXGEN_SOURCE_T; + signal delayed_subsegment : integer range 0 to 3; + signal delayed_position_mod_3 : integer range 0 to 2; + signal delayed_line : integer range 0 to 15; + + + signal position_div_3_on_beginning_segment : integer range 0 to 5973; + signal position_mod_3_on_beginning_segment : integer range 0 to 2; + + + signal currently_inside_reading_zone : std_logic; + +begin + -- Computing current position + process (nrst, clk108, position_mod_3, position_div_3) is + variable incremented_position_div_3 : integer range 0 to 5973; + variable incremented_position_mod_3 : integer range 0 to 2; + begin + if position_mod_3 = 2 then + incremented_position_div_3 := position_div_3 + 1; + incremented_position_mod_3 := 0; + else + incremented_position_div_3 := position_div_3; + incremented_position_mod_3 := position_mod_3 + 1; + end if; + + + if nrst = '0' then + position_div_3 <= 0; + position_mod_3 <= 0; + currently_inside_reading_zone <= '0'; + elsif rising_edge (clk108) then + if currently_read_screen_segment = 0 and currently_read_screen_column = 0 then + currently_inside_reading_zone <= '0'; + else + if time_resolution >= 10 or is_reading_active = '0' then + if segment = currently_read_screen_segment and + column - currently_read_screen_column < 6 and + column - currently_read_screen_column >= 0 then + currently_inside_reading_zone <= '1'; + else + currently_inside_reading_zone <= '0'; + end if; + elsif time_resolution >= 7 then + if segment = currently_read_screen_segment then + currently_inside_reading_zone <= '1'; + else + currently_inside_reading_zone <= '0'; + end if; + else + currently_inside_reading_zone <= '0'; + end if; + end if; + if active_pixgen_source = TRACE_PIXGEN_T then + if page_change = '1' then + position_div_3 <= 0; + position_mod_3 <= 0; + position_div_3_on_beginning_segment <= 0; + position_mod_3_on_beginning_segment <= 0; + elsif segment_change = '1' then + position_div_3 <= incremented_position_div_3; + position_mod_3 <= incremented_position_mod_3; + position_div_3_on_beginning_segment <= incremented_position_div_3; + position_mod_3_on_beginning_segment <= incremented_position_mod_3; + elsif line_change = '1' then + position_div_3 <= position_div_3_on_beginning_segment; + position_mod_3 <= position_mod_3_on_beginning_segment; + else + position_div_3 <= incremented_position_div_3; + position_mod_3 <= incremented_position_mod_3; + end if; + end if; + end if; + end process; + + addrb <= std_logic_vector (to_unsigned (position_div_3, 13)); + + delayed_active_pixgen_source <= active_pixgen_source when rising_edge (clk108); + delayed_subsegment <= subsegment when rising_edge (clk108); + delayed_position_mod_3 <= position_mod_3 when rising_edge (clk108); + delayed_line <= line when rising_edge (clk108); + + + process (nrst, delayed_active_pixgen_source, delayed_subsegment, delayed_position_mod_3, delayed_line, currently_inside_reading_zone) is + begin + if nrst = '0' or delayed_active_pixgen_source /= TRACE_PIXGEN_T then + vout <= "00000000"; + else + if currently_inside_reading_zone = '1' then + vout <= "10010010"; + elsif delayed_subsegment = 0 then + -- red + if delayed_line = 15 then + vout <= "11100000"; + elsif doutb (3 * delayed_position_mod_3) = '1' then + vout <= "11100000"; + else + vout <= "00000000"; + end if; + elsif delayed_subsegment = 1 then + -- green + if delayed_line = 15 then + vout <= "00011100"; + elsif doutb (3 * delayed_position_mod_3 + 1) = '1' then + vout <= "00011100"; + else + vout <= "00000000"; + end if; + elsif delayed_subsegment = 2 then + -- blue + if delayed_line = 15 then + vout <= "00000011"; + elsif doutb (3 * delayed_position_mod_3 + 2) = '1' then + vout <= "00000011"; + else + vout <= "00000000"; + end if; + else + vout <= "00000000"; + end if; + end if; + end process; + +end behavioral; + diff --git a/src/trigger.vhd b/src/trigger.vhd new file mode 100644 index 0000000..842b44a --- /dev/null +++ b/src/trigger.vhd @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- Create Date: 19:12:14 05/24/2011 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use work.types.all; + +entity trigger is + port ( + -- Inputs + nrst : in std_logic; + clk108 : in std_logic; + trigger_btn : in std_logic; + trigger_event : in TRIGGER_EVENT_T; + red_enable : in std_logic; + green_enable : in std_logic; + blue_enable : in std_logic; + continue_after_reading : in std_logic; + red_input : in std_logic; + green_input : in std_logic; + blue_input : in std_logic; + overflow_indicator : in std_logic; + + -- Outputs + red_output : out std_logic; + green_output : out std_logic; + blue_output : out std_logic; + is_reading_active : out std_logic + ); +end trigger; + +architecture behavioral of trigger is + signal internal_is_reading_active : std_logic := '0'; + signal previous_trigger_btn : std_logic := '0'; + signal previous_red_input : std_logic := '0'; + signal previous_green_input : std_logic := '0'; + signal previous_blue_input : std_logic := '0'; + +begin + is_reading_active <= internal_is_reading_active; + + process (nrst, clk108) is + begin + if nrst = '0' then + red_output <= '0'; + green_output <= '0'; + blue_output <= '0'; + internal_is_reading_active <= '0'; + previous_trigger_btn <= '0'; + previous_red_input <= '0'; + previous_green_input <= '0'; + previous_blue_input <= '0'; + elsif rising_edge (clk108) then + red_output <= red_input and red_enable; + green_output <= green_input and green_enable; + blue_output <= blue_input and blue_enable; + + previous_trigger_btn <= trigger_btn; + previous_red_input <= red_input; + previous_green_input <= green_input; + previous_blue_input <= blue_input; + + if internal_is_reading_active = '0' then + -- reading is currently not active + + if trigger_event = BUTTON_TRIGGER_T and + previous_trigger_btn = '0' and + trigger_btn = '1' then + -- Rising edge on trigger button. + internal_is_reading_active <= '1'; + + elsif trigger_event = RED_TRIGGER_T and + previous_red_input = '0' and + red_input = '1' then + -- Rising edge on red input. + internal_is_reading_active <= '1'; + + elsif trigger_event = GREEN_TRIGGER_T and + previous_green_input = '0' and + green_input = '1' then + -- Rising edge on green input. + internal_is_reading_active <= '1'; + + elsif trigger_event = BLUE_TRIGGER_T and + previous_blue_input = '0' and + blue_input = '1' then + -- Rising edge on blue input. + internal_is_reading_active <= '1'; + + end if; + else + -- reading is currently active + + if previous_trigger_btn = '0' and trigger_btn = '1' then + internal_is_reading_active <= '0'; + elsif overflow_indicator = '1' and continue_after_reading = '0' then + internal_is_reading_active <= '0'; + end if; + + end if; + end if; + end process; + +end behavioral; + diff --git a/src/types.vhd b/src/types.vhd new file mode 100644 index 0000000..4577242 --- /dev/null +++ b/src/types.vhd @@ -0,0 +1,70 @@ + +package types is + + type PIXGEN_SOURCE_T is ( + TRACE_PIXGEN_T, + TIME_BASE_PIXGEN_T, + SETTINGS_PIXGEN_T, + BLANK_PIXGEN_T + ); + + type TRIGGER_EVENT_T is ( + RED_TRIGGER_T, + GREEN_TRIGGER_T, + BLUE_TRIGGER_T, + BUTTON_TRIGGER_T + ); + + + + -- This stupid thing is workaround a bug in ISE 13.1 XST synthesis tool + -- It does not understand character'val(...) statements. + type character_array_128 is array (0 to 127) of character; + constant character_conv_table : character_array_128 := + ( + NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, + SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, + RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', + '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', + '<', '=', '>', '?', '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', + 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', + 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', + 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', + 'x', 'y', 'z', '{', '|', '}', '~', DEL + ); + + -- short_character differs from character only by its range. + -- It has 128 first characters. + subtype short_character is character range character_conv_table (0) to character_conv_table (127); + + -- short_string differs from string by: + -- o it's built of short_character's + -- o it's indexed from 0 + type short_string is array (natural range <>) of short_character; + + function to_short_character ( c : character ) return short_character; + function to_short_string ( s : string ) return short_string; + +end types; + +package body types is + + function to_short_character ( c : character ) return short_character is + begin + return character_conv_table (character'pos (c) mod 128); + end function to_short_character; + + + function to_short_string ( s: string ) return short_string is + variable out_s : short_string (s'length - 1 downto 0); + begin + for i in s'length downto 1 loop + out_s (i - 1) := to_short_character (s (i)); + end loop; + return out_s; + end function to_short_string; + + + + +end types; diff --git a/src/vga_controller_1280_1024.vhd b/src/vga_controller_1280_1024.vhd new file mode 100644 index 0000000..0cf01da --- /dev/null +++ b/src/vga_controller_1280_1024.vhd @@ -0,0 +1,162 @@ +---------------------------------------------------------------------------------- +-- Author: Osowski Marcin +-- +-- Description: +-- o Entity generates impulses required for managing +-- vga port in 1280x1024@60hz mode +-- +-- o It requires 108 Mhz input clock +-- +-- o It generates vblank signal. Whenever it's active, +-- vga color output should be set to "00000000" (all black). +-- It indicates an off-the-screen position. +-- +-- o Sync pulses schema: +-- +-- timing diagram for the horizontal synch signal (HS) +-- 0 1328 1440 1680 (pixels) +-- -------------------------|______|------------------- +-- timing diagram for the vertical synch signal (VS) +-- 0 1025 1028 1066 (lines) +-- -----------------------------------|______|--------- +-- +-- +-- +-- o For "next entities" (video signal generators), it generates signals line_change +-- and page_change. They are set to '1' for one clock cycle just before +-- there's a change in (appropriately) current line or current page. +-- +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +entity vga_controller_1280_1024 is + port ( + nrst : in std_logic; + clk108 : in std_logic; + hsync : out std_logic; + vsync : out std_logic; + vblank : out std_logic; + line_change : out std_logic; + page_change : out std_logic; + column : out integer range 0 to 1279; + column_change : out std_logic + ); +end vga_controller_1280_1024; + +architecture behavioral of vga_controller_1280_1024 is + + + constant HFrontPorch : integer := 1280; + constant HSyncPulse : integer := 1328; + constant HBackPorch : integer := 1440; + constant HTotal : integer := 1688; + + constant VFrontPorch : integer := 1024; + constant VSyncPulse : integer := 1025; + constant VBackPorch : integer := 1028; + constant VTotal : integer := 1066; + + signal hcount: integer range 0 to 1687 := 0; + signal vcount: integer range 0 to 1065 := 0; + + signal next_hcount: integer range 0 to 1687; + signal next_vcount: integer range 0 to 1065; + + signal internal_column : integer range 0 to 1279; + signal next_column : integer range 0 to 1279; + signal next_column_change : std_logic; + +begin + + -- Generating next_hcount. + next_hcount <= hcount + 1 when hcount < (HTotal - 1) else 0; + + -- Generating next_vcount. + process (vcount, next_hcount) is + begin + if next_hcount = 0 then + if vcount < (VTotal - 1) then + next_vcount <= vcount + 1; + else + next_vcount <= 0; + end if; + else + next_vcount <= vcount; + end if; + end process; + + -- Generating next_column and next_column_change. + process (next_hcount, internal_column, next_column) is + begin + if (next_hcount >= 1280) then + next_column <= 1279; + else + next_column <= next_hcount; + end if; + + if next_column /= internal_column then + next_column_change <= '1'; + else + next_column_change <= '0'; + end if; + end process; + + column <= internal_column; + + + -- Generating sync pulses and line_change, page_change signals. + process (nrst, clk108) is + begin + if nrst = '0' then + line_change <= '0'; + page_change <= '0'; + hsync <= '0'; + vsync <= '0'; + vblank <= '0'; + internal_column <= 0; + column_change <= '0'; + elsif rising_edge (clk108) then + if vcount /= next_vcount then + line_change <= '1'; + else + line_change <= '0'; + end if; + if vcount /= next_vcount and next_vcount = 0 then + page_change <= '1'; + else + page_change <= '0'; + end if; + + hcount <= next_hcount; + if (next_hcount >= 1280) then + internal_column <= 1279; + else + internal_column <= next_hcount; + end if; + column_change <= next_column_change; + vcount <= next_vcount; + + if next_hcount < HFrontPorch and next_vcount < VFrontPorch then + vblank <= '0'; + else + vblank <= '1'; + end if; + + if next_hcount >= HSyncPulse and next_hcount < HBackPorch then + hsync <= '1'; + else + hsync <= '0'; + end if; + + if next_vcount >= VSyncPulse and next_vcount < VBackPorch then + vsync <= '1'; + else + vsync <= '0'; + end if; + end if; + end process; + +end architecture behavioral;