From 1a03ff2a723018988582b2427b7f2068250bf5ef Mon Sep 17 00:00:00 2001 From: Morten Borup Petersen Date: Sun, 31 Jul 2022 11:36:37 +0200 Subject: [PATCH] Fix broken link --- docs/cache_sim.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/cache_sim.md b/docs/cache_sim.md index b70805982..5b18768d7 100644 --- a/docs/cache_sim.md +++ b/docs/cache_sim.md @@ -91,7 +91,7 @@ The following example illustrates how different cache configurations may have an ### Example Program The example program allows us to specify some memory access pattern wherein adjusting this access pattern will have an impact on cache performance. -The example program is sketched out as a C program and compiled to RISC-V assembly using [Compiler Explorer](https://godbolt.org/) (for tips on how to convert compiler-explorer generated RISC-V assembly to assembly compatible with the Ripes assembler, refer to [this docs page](https://github.com/mortbopet/Ripes/docs/compiler_explorer.md)). +The example program is sketched out as a C program and compiled to RISC-V assembly using [Compiler Explorer](https://godbolt.org/) (for tips on how to convert compiler-explorer generated RISC-V assembly to assembly compatible with the Ripes assembler, refer to [this docs page](https://github.com/mortbopet/Ripes/blob/master/docs/compiler_explorer.md)). ```C++ unsigned stride = 4; unsigned accessesPerTurn = 128;