diff --git a/src/processorregistry.h b/src/processorregistry.h
index f940d8ccf..8f16dd91f 100644
--- a/src/processorregistry.h
+++ b/src/processorregistry.h
@@ -90,7 +90,7 @@ class ProcessorRegistry {
         desc = ProcessorDescription();
         desc.id = ProcessorID::RV5S_NO_HZ;
         desc.isa = ISAInfo<ISA::RV32IM>::instance();
-        desc.name = "5-Stage Processor wo/ hazard detection";
+        desc.name = "5-Stage Processor w/o hazard detection";
         desc.description = "A 5-Stage in-order processor with forwarding but no hazard detection/elimination.";
         desc.layouts = {
             {"Standard", ":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json", {0.08, 0.3, 0.53, 0.75, 0.88}},
@@ -102,7 +102,7 @@ class ProcessorRegistry {
         desc = ProcessorDescription();
         desc.id = ProcessorID::RV5S_NO_FW_HZ;
         desc.isa = ISAInfo<ISA::RV32IM>::instance();
-        desc.name = "5-Stage Processor wo/ forwarding or hazard detection";
+        desc.name = "5-Stage Processor w/o forwarding or hazard detection";
         desc.description = "A 5-Stage in-order processor with no forwarding or hazard detection/elimination.";
         desc.layouts = {{"Standard",
                          ":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json",
diff --git a/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json b/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json
index 790e228f0..53828a77d 100644
--- a/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json
+++ b/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json
@@ -23505,7 +23505,7 @@
             "Italic": false,
             "PtSize": 18,
             "Text": {
-                "str": "5-Stage RISC-V Processor  wo/ Forwarding or Hazard Detection"
+                "str": "5-Stage RISC-V Processor  w/o Forwarding or Hazard Detection"
             },
             "Pos": {
                 "x": 650.1103101784723,
@@ -23515,4 +23515,4 @@
         },
         "Indicators": []
     }
-}
\ No newline at end of file
+}
diff --git a/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json b/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json
index 376377ed8..8a7d055e3 100644
--- a/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json
+++ b/src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json
@@ -23158,7 +23158,7 @@
             "Italic": false,
             "PtSize": 15,
             "Text": {
-                "str": "5-Stage RISC-V Processor wo/ Forwarding or Hazard Detection          "
+                "str": "5-Stage RISC-V Processor w/o Forwarding or Hazard Detection          "
             },
             "Pos": {
                 "x": 575.339479795716,
diff --git a/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json b/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json
index 3b78a97f6..22ec315a7 100644
--- a/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json
+++ b/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json
@@ -26370,7 +26370,7 @@
             "Italic": false,
             "PtSize": 18,
             "Text": {
-                "str": "5-Stage RISC-V Processor wo/ Hazard Detection"
+                "str": "5-Stage RISC-V Processor w/o Hazard Detection"
             },
             "Pos": {
                 "x": 840.9834782481146,
diff --git a/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json b/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json
index c91b5f63c..0899c5e8c 100644
--- a/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json
+++ b/src/processors/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json
@@ -25792,7 +25792,7 @@
             "Italic": false,
             "PtSize": 18,
             "Text": {
-                "str": "5-Stage RISC-V Processor  wo/ Hazard Detection"
+                "str": "5-Stage RISC-V Processor  w/o Hazard Detection"
             },
             "Pos": {
                 "x": 593.9467924424445,
diff --git a/src/stagetablewidget.ui b/src/stagetablewidget.ui
index a9099acf3..566f8b884 100644
--- a/src/stagetablewidget.ui
+++ b/src/stagetablewidget.ui
@@ -47,7 +47,7 @@
        <item>
         <widget class="QLabel" name="label">
          <property name="text">
-          <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;&lt;span style=&quot; font-weight:600;&quot;&gt;Note: &lt;/span&gt;Stage information is &lt;span style=&quot; font-style:italic;&quot;&gt;not &lt;/span&gt;recorded while executing the processor via. the &amp;quot;Run&amp;quot; option.&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
+          <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;&lt;span style=&quot; font-weight:600;&quot;&gt;Note: &lt;/span&gt;Stage information is &lt;span style=&quot; font-style:italic;&quot;&gt;not &lt;/span&gt;recorded while executing the processor via the &amp;quot;Run&amp;quot; option.&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
          </property>
          <property name="textFormat">
           <enum>Qt::RichText</enum>