From 37c6daff037c7d3a1b8c4c0f6dea0864910765eb Mon Sep 17 00:00:00 2001
From: Morten Borup Petersen <morten_bp@live.dk>
Date: Thu, 29 Jul 2021 10:02:24 +0200
Subject: [PATCH] Add missing handling of MULW instruction in RV ALU

---
 src/processors/RISC-V/rv_alu.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/processors/RISC-V/rv_alu.h b/src/processors/RISC-V/rv_alu.h
index ab79aac97..aef0521d8 100644
--- a/src/processors/RISC-V/rv_alu.h
+++ b/src/processors/RISC-V/rv_alu.h
@@ -25,6 +25,8 @@ class ALU : public Component {
                     return op1.uValue() + op2.uValue();
                 case ALUOp::SUB:
                     return op1.uValue() - op2.uValue();
+                case ALUOp::MULW:
+                    return VT_U(signextend<32>(static_cast<int32_t>(op1.uValue()) * op2.uValue()));
                 case ALUOp::MUL:
                     return VT_U(op1.sValue() * op2.sValue());
                 case ALUOp::MULH: {