Misaligned data memory access

[edgardogho]

Hello. We use Ripes for a computer architecture class and we think it is great. One of lectures is on Traps/interrupts on RISC-V. Ripes does not support this (other than ecalls). We are considering collaborating with this, but it is more of a long term project. As short term (something we can work now) we would like to do 2 additions :

1. When an ecall has an invalid argument on A7 , right now it shows a popup, but the program continues running. This is a problem for us since we might be on an exam and a student puts an invalid value on A7 inside a loop and we can't stop the popups or stop the program. We will modify this so its no longer a popup but a message on the console and terminates the program.
2. When memory is accessed (either a Load or Store) right now Ripes support aligned or misaligned (unaligned) access. On some RISC-V microarchitectures this generates a trap (for instance on SiFive FE310 it generates a Trap) , while on some microarchitectures it works fine (like on the ESP32C3). We would like to add a checkbox on settings that says "Terminate program on misaligned memory access" and stop the program if this happens.
   Both for 1 and 2, we would print in the console the values for mepc, mtval, mcause so in the future if exceptions are supported this can be used to recover.. but right now terminating the programs is good enough for us.

Would this be something interesting enough to submit on a Pull Request? or maybe its not on the roadmap for Ripes to support traps.