How to mark systemVerilog file as library file

[desorya]

Hi there,

I wonder how to mark .sv files as library file in .core for VCS, which is as same as -v path/to/file in .f files list, and the VCS will show below format in the log:

Parsing library directory file: `PATH/TO/FILE`

I tried the logical_name: library but VCS still treat them as design file. Is there any way to specify?

Thank you!