fusesoc and ghdl fail to build when logical_name is used

[stdefeber]

I was making a core file for FuseSoc icm with ghdl for the neorv32.
Since the neorv32 makes use of the library called "neorv32" the core file required a "logical_name: neorv32".
As experiment I placed my test-bench in work cause the neorv32 will be used in a larger design.

ghdl comes back with:

ghdl:error: cannot find entity or configuration tb_neorv32

Hereby a recreated bash script from the FuseSoc build flow:

mkdir -p neorv32
mkdir -p work
ghdl -i --std=08 -P./neorv32 -P./work --work=neorv32 --workdir=./neorv32 ../rtl/core/neorv32_package.vhd ../rtl/core/neorv32_cpu_cp_crypto.vhd ../rtl/core/neorv32_xip.vhd ../rtl/core/neorv32_wdt.vhd ../rtl/core/neorv32_bootloader_image.vhd ../rtl/core/neorv32_twi.vhd ../rtl/core/neorv32_xbus.vhd ../rtl/core/neorv32_dmem.vhd ../rtl/core/neorv32_cpu_pmp.vhd ../rtl/core/neorv32_cpu_lsu.vhd ../rtl/core/neorv32_gpio.vhd ../rtl/core/neorv32_cpu_cp_fpu.vhd ../rtl/core/neorv32_cfs.vhd ../rtl/core/neorv32_slink.vhd ../rtl/core/neorv32_cpu_cp_cfu.vhd ../rtl/core/neorv32_gptmr.vhd ../rtl/core/neorv32_xirq.vhd ../rtl/core/neorv32_cpu_cp_cond.vhd ../rtl/core/neorv32_boot_rom.vhd ../rtl/core/neorv32_fifo.vhd ../rtl/core/neorv32_onewire.vhd ../rtl/core/neorv32_pwm.vhd ../rtl/core/neorv32_sysinfo.vhd ../rtl/core/neorv32_cpu_control.vhd ../rtl/core/neorv32_cpu_cp_muldiv.vhd ../rtl/core/neorv32_cpu_regfile.vhd ../rtl/core/neorv32_application_image.vhd ../rtl/core/neorv32_spi.vhd ../rtl/core/neorv32_trng.vhd ../rtl/core/neorv32_sdi.vhd ../rtl/core/neorv32_sys.vhd ../rtl/core/neorv32_mtime.vhd ../rtl/core/neorv32_cpu_decompressor.vhd ../rtl/core/neorv32_cache.vhd ../rtl/core/neorv32_uart.vhd ../rtl/core/neorv32_clockgate.vhd ../rtl/core/neorv32_cpu.vhd ../rtl/core/neorv32_debug_dtm.vhd ../rtl/core/neorv32_cpu_cp_bitmanip.vhd ../rtl/core/neorv32_cpu_cp_shifter.vhd ../rtl/core/neorv32_crc.vhd ../rtl/core/neorv32_imem.vhd ../rtl/core/neorv32_neoled.vhd ../rtl/core/neorv32_dma.vhd ../rtl/core/neorv32_debug_dm.vhd ../rtl/core/neorv32_cpu_alu.vhd ../rtl/core/neorv32_bus.vhd ../rtl/core/neorv32_top.vhd
ghdl -i --std=08 -P./neorv32 -P./work --work=work --workdir=./work ../sim/tb_neorv32.vhd
ghdl -m --std=08 -P./neorv32 -P./work  tb_neorv32

After some experiments I found that the last step was missing the "workdir" switch.

So the the last step should be:

ghdl -m --std=08 -P./neorv32 -P./work --workdir=./work tb_neorv32

[stdefeber]

I dove into it a bit further.

It looks like edalize is the culprit here.

The j2 Makefile template misses the workdir variable.

$(TOPLEVEL): $(VHDL_SOURCES) work-obj{{ standard }}.cf
	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

I guess by adding "library_options" in the ghdl.py self.render_template function call it can easily be solved.

self.render_template(
            "Makefile.j2",
            "Makefile",
            {
                "std": " ".join(stdarg),
                "toplevel": top_unit,
                "vhdl_sources": vhdl_sources,
                "standard": standard,
                "analyze_options": analyze_options,
                "run_options": " ".join(run_options),
                "make_libraries_directories": make_libraries_directories,
                "ghdlimport": ghdlimport,
                "top_libraries": top_libraries,
                "library_options":library_options
            },
        )

And to the Makefile template

STD = {{ std }}
TOPLEVEL = {{ toplevel }}
TOPLEVEL_LIBS = {{ top_libraries }}
ANALYZE_OPTIONS = {{ analyze_options }}
RUN_OPTIONS = {{ run_options }}
LIBRARY_OPTIONS= {{ library_options }}
VHDL_SOURCES = {{ vhdl_sources }}

all: work-obj{{ standard }}.cf

run: $(TOPLEVEL)
	$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)

$(TOPLEVEL): $(VHDL_SOURCES) work-obj{{ standard }}.cf
	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(LIBRARY_OPTIONS) $(TOPLEVEL)

$(TOPLEVEL).v: $(VHDL_SOURCES) work-obj{{ standard }}.cf
	$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

make_libraries_directories:
	@echo "Creating libraries directories"
{{ make_libraries_directories }}
work-obj{{ standard }}.cf: make_libraries_directories
{{ ghdlimport }}

[stdefeber]

I found a solution.

After dabbling around in Edalize and trying to fix the issue I noticed that in the test case for ghdl, test04, a library was prepended to the top-level file.
This does work for my case.

It seems to be an undocumented feature in Edalize or Fusesoc.

However it would be great that logical names work for 2 different sets of files in a core file would work.

      ........
      - deps/neorv32/rtl/core/neorv32_bus.vhd
      - deps/neorv32/rtl/core/neorv32_top.vhd
    file_type: vhdlSource-2008
    logical_name: neorv32
  tb:
    files:
      - deps/neorv32/sim/tb_neorv32.vhd
    file_type: vhdlSource-2008
    logical_name: work