Generate Vivado project + block diagram

[rafaelnp]

Hello everybody,

infos:

• code: https://gitlab.com/rafaelnp/uart_axi_fusesoc
• OS: Arch Linux 6.12.1-arch1-1
• FuseSoc: 2.4
• Vivado: 2024.2

I am trying to generate a simple project (original source here), and when running fusesoc run --target synth uart_axi I get the following error:

❯ fusesoc run --target synth uart_axi
INFO: Preparing ::uart_axi:0.1
INFO: Setting up project
INFO: Building
vivado -notrace -mode batch -source uart_axi_0.1.tcl

****** Vivado v2024.2 (64-bit)
  **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
  **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
  **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
  **** Start of session at: Tue Dec  3 10:49:58 2024
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

source uart_axi_0.1.tcl -notrace
WARNING: [Ipconfig 75-871] Could not load NoC clock tree from device
WARNING: [Ipconfig 75-570] Unable to create NoC or AIE Models.
INFO: [BD::TCL 103-2003] Currently there is no design <uart_axi> in project, so creating one...
Wrote  : </home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.srcs/sources_1/bd/uart_axi/uart_axi.bd> 
INFO: [BD::TCL 103-2004] Making design <uart_axi> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "uart_axi".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:smartconnect:1.0  .
INFO: [BD::TCL 103-2020] Checking if the following modules exist in the project's sources:  
uart axi_protocol  .
ERROR: [BD::TCL 103-2021] The following module(s) are not found in the project: uart axi_protocol
INFO: [BD::TCL 103-2022] Please add source files for the missing module(s) above.
WARNING: [BD::TCL 103-2023] Will not continue with creation of design due to the error(s) above.
INFO: [Common 17-206] Exiting Vivado at Tue Dec  3 10:50:02 2024...
vivado -notrace -mode batch -source uart_axi_0.1_synth.tcl uart_axi_0.1_run.tcl uart_axi_0.1.xpr

****** Vivado v2024.2 (64-bit)
  **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
  **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
  **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
  **** Start of session at: Tue Dec  3 10:50:10 2024
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

open_project uart_axi_0.1.xpr
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.gen/sources_1'.
Scanning sources...
Finished scanning sources
source uart_axi_0.1_synth.tcl -notrace
Wrote  : </home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.srcs/sources_1/bd/uart_axi/uart_axi.bd> 
Verilog Output written to : /home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.gen/sources_1/bd/uart_axi/synth/uart_axi.v
Verilog Output written to : /home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.gen/sources_1/bd/uart_axi/sim/uart_axi.v
Verilog Output written to : /home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.gen/sources_1/bd/uart_axi/hdl/uart_axi_wrapper.v
Exporting to file /home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.gen/sources_1/bd/uart_axi/hw_handoff/uart_axi.hwh
Generated Hardware Definition File /home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.gen/sources_1/bd/uart_axi/synth/uart_axi.hwdef
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Tue Dec  3 10:50:15 2024] Launched synth_1...
Run output will be captured here: /home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/uart_axi_0.1.runs/synth_1/runme.log
[Tue Dec  3 10:50:15 2024] Waiting for synth_1 to finish...

*** Running vivado
    with args -log uart_axi_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source uart_axi_top.tcl


****** Vivado v2024.2 (64-bit)
  **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
  **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
  **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
  **** Start of session at: Tue Dec  3 10:50:17 2024
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

source uart_axi_top.tcl -notrace
Command: synth_design -top uart_axi_top -part xc7a35tcpg236-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 1235238
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1974.988 ; gain = 418.734 ; free physical = 14199 ; free virtual = 164012
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'uart_axi_top' [/home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/src/uart_axi_0.1/src/uart_axi_top.vhd:18]
ERROR: [Synth 8-5826] no such design unit 'uart_axi_wrapper' in library 'work' [/home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/src/uart_axi_0.1/src/uart_axi_top.vhd:25]
ERROR: [Synth 8-285] failed synthesizing module 'uart_axi_top' [/home/user/src/uart_axi_fusesoc/build/uart_axi_0.1/synth-vivado/src/uart_axi_0.1/src/uart_axi_top.vhd:18]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2048.926 ; gain = 492.672 ; free physical = 14197 ; free virtual = 164011
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
7 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Tue Dec  3 10:50:25 2024...
[Tue Dec  3 10:50:29 2024] synth_1 finished
ERROR: [Vivado 12-13638] Failed runs(s) : 'synth_1'
wait_on_runs: Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1537.062 ; gain = 0.000 ; free physical = 15209 ; free virtual = 165023
ERROR: [Common 17-39] 'wait_on_runs' failed due to earlier errors.

    while executing
"wait_on_run synth_1"
    invoked from within
"if {$outdated || $progress != "100%"} {
    reset_runs synth_1
    launch_runs synth_1
    wait_on_run synth_1
}"
    (file "uart_axi_0.1_synth.tcl" line 4)
INFO: [Common 17-206] Exiting Vivado at Tue Dec  3 10:50:29 2024...
make: *** [Makefile:16: uart_axi_0.1.bit] Error 1
ERROR: Failed to build ::uart_axi:0.1 : '['make']' exited with an error: 2

Is it possible to specify the order the vhdl and tcl files are read, so the vhdl files are sourced before the block diagram and they can be properly found and the block diagram can be successfully generated?

[rafaelnp]

After comparing a hand written tcl script for the project generation and the one generate using fusesoc, it was observed that Vivado expects the block design tcl script to be in the same fileset (sources_1), so they can be found when generating the block design.

filesets:
  rtl:
    files:
      - src/uart_pkg.vhd  : {file_type: vhdlSource}
      - src/uart.vhd  : {file_type: vhdlSource}
      - src/protocol.vhd  : {file_type: vhdlSource}
      - src/uart_axi_top.vhd : {file_type: vhdlSource}
      - tcl/uart_axi_bd.tcl : { file_type: tclSource}

Afterwards another issue showed up: [filemgmt 56-587] Failed to resolve reference. Nothing was found in the project to match the name uart Try changing the compile order from manual to automatic. It was solved by adding the option source_mgmt_mode: All in the tools section:

    tools:
      vivado:
        part: xc7a35tcpg236-1
        source_mgmt_mode: All

The entire fusesoc core file solving both problems, for completeness, be can found below:

CAPI=2:
name: ::uart_axi:0.1
description: uart axi, for accessing axi bus from uart

filesets:
  rtl:
    # the block design tcl script must be add together with the rtl files,
    # otherwise Vivado does not find the vhdl files referenced in the block design
    files:
      - src/uart_pkg.vhd  : {file_type: vhdlSource}
      - src/uart.vhd  : {file_type: vhdlSource}
      - src/protocol.vhd  : {file_type: vhdlSource}
      - src/uart_axi_top.vhd : {file_type: vhdlSource}
      - tcl/uart_axi_bd.tcl : { file_type: tclSource}

  config:
    files:
      - tcl/config.tcl : { file_type: tclSource }

  basys3:
    files:
      - xdc/basys3_uart_axi.xdc
    file_type: xdc

targets:
  # Special FuseSoC targe
  default: &default
    filesets:
      - rtl
      - config
    toplevel:
      - uart_axi_top

  # The "synth" target synthesizes the design. (It could have any name.)
  synth:
    <<: *default
    description: Synthesize the design for a basys3 FPGA board
    default_tool: vivado
    filesets_append:
      - basys3
    tools:
      vivado:
        part: xc7a35tcpg236-1
        # needed for using block design
        # https://github.com/olofk/edalize/blob/21ef0a3682b4b7c359e2d1422ec9fb205cf8a9b0/edalize/vivado.py
        source_mgmt_mode: All

I hope it may be useful to other FuseSoc users.