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Hi
I am simulation the openwifi fpga code in vivado
and need little info about data structure of test vector
Stored in tx-intrf.mem file and other two file also.
How these stored data is feeded to 64 bit interface of top tx module? I mean 64 bit interface of bram_din port?
Regards
J S Hyanki
The text was updated successfully, but these errors were encountered:
Hi
I am simulation the openwifi fpga code in vivado
and need little info about data structure of test vector
Stored in tx-intrf.mem file and other two file also.
How these stored data is feeded to 64 bit interface of top tx module? I mean 64 bit interface of bram_din port?
Regards
J S Hyanki
The text was updated successfully, but these errors were encountered: