Merge pull request #150 from robots/same5trace

add support for sam 5x mcu trace

Support/gdbtrace.init

@@ -20,6 +20,7 @@ IMXRT;
 
 SAM5X;
   enableSAMD5XSWD    : Enable SWO on SAM5X output pin on SAM5X
+  enableSAMD5XTRACE  : Enable TRACE on SAM5x pins
 
 NRF;
   enableNRF52TRACE : Start TRACE on NRF52 (not nrf52833 or nrf52840) pins
@@ -88,6 +89,7 @@ set $CPU_TM4C=5
 set $CPU_S32K344=6
 set $CPU_IMXRT117X=7
 set $CPU_KINETIS=8
+set $CPU_SAMD5x=9
 
 # ====================================================================
 set $CDBBASE=0xE000EDF0
@@ -923,7 +925,6 @@ end
 document enableSAMD5XSWD
 enableSAMD5XSWD Configure output pin on SAM5X for SWO use.
 end
-
 # ====================================================================
 define enableEFR32MG12SWO
   #set language c
@@ -1488,7 +1489,88 @@ document enableLPC176xTRACE
 enableLPC176xTRACE Enable TRACE on LPC176x pins.
   <Width>   : Number of bits wide (1,2 or 4 only)
 end
+# ====================================================================
+define enableSAMD5XTRACE
+  #set language c
+
+  set $bits=4
+  set $drive=1
+
+  if $argc >= 1
+    set $bits = $arg0
+  end
+    if (($bits<1) || ($bits==3) || ($bits>4))
+    help enableSAMD5XTRACE
+  end
+
+  if $argc >= 2
+    set $drive = $arg1
+  end
+
+  if ($drive > 1)
+    help enableSAMD5XTRACE
+  end
+
+  set $bits = $bits-1
+  set $CPU=$CPU_SAMD5x
+
+  # Enable peripheral channel clock on GCLK#0
+  # GCLK->PHCTRL[47] = GCLK_PCHCTRL_GEN(0)
+  set *(unsigned char *)0x40001D3C = 0
+  # GCLK->PHCTRL[47] |= GCLK_PCHCTRL_CHEN
+  set *(unsigned char *)0x40001D3C |= 0x40
+
+  # Setup PC28 - pmux 7
+  set *(unsigned char *)(0x41008000+0x80*2+0x30+28/2) &= ~0x0f
+  set *(unsigned char *)(0x41008000+0x80*2+0x30+28/2) |= 0x07
+  set *(unsigned char *)(0x41008000+0x80*2+0x40+28) = (($drive) << 6) | 1
 
+  # Setup PC27 - pmux 7
+  set *(unsigned char *)(0x41008000+0x80*2+0x30+27/2) &= ~0xf0
+  set *(unsigned char *)(0x41008000+0x80*2+0x30+27/2) |= 0x70
+  set *(unsigned char *)(0x41008000+0x80*2+0x40+27) = (($drive) << 6) | 1
+
+  if ($bits>0)
+    # Setup PC26 - pmux 7
+    set *(unsigned char *)(0x41008000+0x80*2+0x30+26/2) &= ~0x0f
+    set *(unsigned char *)(0x41008000+0x80*2+0x30+26/2) |= 0x07
+    set *(unsigned char *)(0x41008000+0x80*2+0x40+26) = (($drive) << 6) | 1
+  end
+
+  if ($bits>1)
+    # Setup PC25 - pmux 7
+    set *(unsigned char *)(0x41008000+0x80*2+0x30+25/2) &= ~0xf0
+    set *(unsigned char *)(0x41008000+0x80*2+0x30+25/2) |= 0x70
+    set *(unsigned char *)(0x41008000+0x80*2+0x40+25) = (($drive) << 6) | 1
+
+    # Setup PC24 - pmux 7
+    set *(unsigned char *)(0x41008000+0x80*2+0x30+24/2) &= ~0x0f
+    set *(unsigned char *)(0x41008000+0x80*2+0x30+24/2) |= 0x07
+    set *(unsigned char *)(0x41008000+0x80*2+0x40+24) = (($drive) << 6) | 1
+  end
+
+  # Set number of bits in DBGMCU_CR
+  set *0xE0042004 &= ~(3<<6)
+
+  if ($bits<3)
+     set *0xE0042004 |= ((($bits+1)<<6) | (1<<5))
+  else
+     set *0xE0042004 |= ((3<<6) | (1<<5))
+  end
+
+  # Enable Trace TRCENA (DCB DEMCR)
+  set *($CDBBASE+0xC)=(1<<24)
+
+  # Finally start the trace output
+  _doTRACE
+
+  #set language auto
+end
+document enableSAMD5XTRACE
+enableSAMD5XTRACE <Width> <Drive>: Enable TRACE on SAM5x pins
+  <Width>   : Number of bits wide (1,2 or 4 only)
+  <Drive>   : Drive strength (0=normal, 1=strong)
+end
 # ====================================================================
 define dwtPOSTCNT
   #set language c