From 2f395b176bee1c769c80f060a4345fda965bb04b Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Wed, 28 Sep 2022 14:57:56 +0200 Subject: [PATCH] Release v0.38.0 --- CHANGELOG.md | 17 ++++++++++++++--- README.md | 2 ++ VERSION | 2 +- axi.core | 2 +- 4 files changed, 18 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 17d1a1791..90cce6ae5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,11 +8,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased ### Added -- Add `axi_dumper` and `axi_dumper_interpret` script to dump log from an AXI bus for debugging purposes. + +### Changed + +### Fixed + + +## 0.38.0 - 2022-09-28 + +### Added +- Add `axi_dumper` and `axi_dumper_interpret` script to dump log from an AXI bus for debugging + purposes. - Add FuseSoC and Vivado XSIM limited test to CI - `assign.svh`: Add macros to assign flat buses using the Vivado naming style. - `axi_lfsr` and `axi_lite_lfsr`: Add AXI4 and AXI4 Lite LFSR Subordinate devices. -- `axi_xp`: Crosspoint with homomorphous slave and master ports. +- `axi_xp`: Add crosspoint with homomorphous slave and master ports. ### Changed - Improve compatibility with FuseSoC @@ -20,7 +30,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Performance improvements to `axi_to_mem` - Use `scripts/update_authors` to update authors, slight manual fixes performed. -### Fixed +`v0.38.0` is fully **backward-compatible** to `v0.36.0` and `v0.37.0`. ## 0.37.0 - 2022-08-30 @@ -55,6 +65,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. `v0.37.0` is fully **backward-compatible** to `v0.36.0`. + ## 0.36.0 - 2022-07-07 ### Added diff --git a/README.md b/README.md index ed678dfba..85cf211f1 100644 --- a/README.md +++ b/README.md @@ -59,6 +59,7 @@ In addition to the documents linked in the following table, we are setting up [d | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv) | AXI4 to AXI4-Lite protocol converter. | | | [`axi_to_mem`](src/axi_to_mem.sv) | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. | | | [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) | +| [`axi_xp`](src/axi_xp.sv) | AXI Crosspoint (XP) with homomorphous slave and master ports. | | ### Simulation-Only Modules @@ -68,6 +69,7 @@ In addition to the modules above, which are available in synthesis and simulatio |------------------------------------------------------|--------------------------------------------------------------------------------------------------------| | [`axi_chan_logger`](src/axi_test.sv) | Logs the transactions of an AXI4(+ATOPs) port to files. | | [`axi_driver`](src/axi_test.sv) | Low-level driver for AXI4(+ATOPs) that can send and receive individual beats on any channel. | +| [`axi_dumper`](src/axi_dumper.sv) | Dumps log to file to be interpreted by `axi_dumper_interpret` script for debugging purposes. | | [`axi_lite_driver`](src/axi_test.sv) | Low-level driver for AXI4-Lite that can send and receive individual beats on any channel. | | [`axi_lite_rand_master`](src/axi_test.sv) | AXI4-Lite master component that issues random transactions within user-defined constraints. | | [`axi_lite_rand_slave`](src/axi_test.sv) | AXI4-Lite slave component that responds to transactions with constrainable random delays and data. | diff --git a/VERSION b/VERSION index 0f1a7dfc7..ca75280b0 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.37.0 +0.38.0 diff --git a/axi.core b/axi.core index 64c8ea524..cc4e98609 100644 --- a/axi.core +++ b/axi.core @@ -1,6 +1,6 @@ CAPI=2: -name : pulp-platform.org::axi:0.37.0 +name : pulp-platform.org::axi:0.38.0 filesets: rtl: