From 10d815c34b877277ddb5b46bfc45876e482c9d12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20R=C3=B6nninger?= Date: Mon, 29 Jun 2020 13:28:53 +0200 Subject: [PATCH] axi_demux: Remove W select FIFO, add counter and register --- CHANGELOG.md | 5 +++++ src/axi_demux.sv | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ae12b1c2c..97402a3be 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -323,6 +323,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - `axi_test::rand_axi_lite_slave` and `axi_test::rand_axi_lite_master`: Change type of address and data width parameters (`AW` and `DW`) from `int` to `int unsigned`. Same rationale as for `AXI_BUS` (et al.) above. +- `axi_demux`: Remove FIFO between AW and W channel, is now a register plus counter. + Prevents AWs to be emmitted downstream to a different master port as long as Ws + are still in flight to another. This prevents deadlock, if there is stalling + downstream. + ### Fixed - `axi_demux`: Break combinatorial simulation loop. diff --git a/src/axi_demux.sv b/src/axi_demux.sv index 184e9b23c..9e05406da 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -817,7 +817,6 @@ module axi_demux_intf #( parameter int unsigned MAX_TRANS = 32'd8, parameter int unsigned AXI_LOOK_BITS = 32'd3, parameter bit UNIQUE_IDS = 1'b0, - parameter bit FALL_THROUGH = 1'b0, parameter bit SPILL_AW = 1'b1, parameter bit SPILL_W = 1'b0, parameter bit SPILL_B = 1'b0,