diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv
index 2d50281de..ebcce76a4 100644
--- a/src/axi_id_remap.sv
+++ b/src/axi_id_remap.sv
@@ -285,13 +285,21 @@ module axi_id_remap #(
             aw_id_d = wr_push_oup_id;
           end
         end
-        priority casez ({mst_req_o.ar_valid, mst_resp_i.ar_ready,
-                         mst_req_o.aw_valid, mst_resp_i.aw_ready})
-          4'b1010: state_d = HoldAx;
-          4'b10??: state_d = HoldAR;
-          4'b??10: state_d = HoldAW;
-          default: state_d = Ready;
-        endcase
+        if ({mst_req_o.ar_valid, mst_resp_i.ar_ready,
+             mst_req_o.aw_valid, mst_resp_i.aw_ready} == 4'b1010) begin
+          state_d = HoldAx;
+        end else if ({mst_req_o.ar_valid, mst_resp_i.ar_ready} == 2'b10) begin
+          state_d = HoldAR;
+        end else if ({mst_req_o.aw_valid, mst_resp_i.aw_ready} == 2'b10) begin
+          state_d = HoldAW;
+        end else state_d = Ready;
+        // priority casez ({mst_req_o.ar_valid, mst_resp_i.ar_ready,
+        //                  mst_req_o.aw_valid, mst_resp_i.aw_ready})
+        //   4'b1010: state_d = HoldAx;
+        //   4'b10??: state_d = HoldAR;
+        //   4'b??10: state_d = HoldAW;
+        //   default: state_d = Ready;
+        // endcase
 
         if (mst_req_o.ar_valid && mst_resp_i.ar_ready) begin
           ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle.