From 1dfae098bccdad358dac2c87a9f65305d6bafb46 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 16 May 2023 18:26:23 +0200 Subject: [PATCH] Correctly split r/w in axi_to_mem_* for atops --- src/axi_to_mem_banked.sv | 2 +- src/axi_to_mem_interleaved.sv | 43 ++++++++++++++++++----------------- src/axi_to_mem_split.sv | 30 ++++++++++++++++-------- 3 files changed, 43 insertions(+), 32 deletions(-) diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv index cc7c6198d..548339f37 100644 --- a/src/axi_to_mem_banked.sv +++ b/src/axi_to_mem_banked.sv @@ -150,7 +150,7 @@ module axi_to_mem_banked #( .NoMstPorts ( 32'd2 ), .MaxTrans ( MemLatency+2 ), // allow multiple Ax vectors to not starve W channel .AxiLookBits ( 32'd1 ), // select is fixed, do not need it - .UniqueIds ( 1'b0 ), + .UniqueIds ( 1'b1 ), // Can be set as ports are statically selected -> reduces HW .SpillAw ( 1'b1 ), .SpillW ( 1'b1 ), .SpillB ( 1'b1 ), diff --git a/src/axi_to_mem_interleaved.sv b/src/axi_to_mem_interleaved.sv index a744c1ec0..fb7e8570e 100644 --- a/src/axi_to_mem_interleaved.sv +++ b/src/axi_to_mem_interleaved.sv @@ -47,6 +47,8 @@ module axi_to_mem_interleaved #( input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, + /// Testmode enable + input logic test_i, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, /// AXI4+ATOP slave port, request input. @@ -94,27 +96,26 @@ module axi_to_mem_interleaved #( mem_data_t [NumBanks-1:0] r_mem_rdata, w_mem_rdata; // split AXI bus in read and write - always_comb begin : proc_axi_rw_split - axi_resp_o.r = r_axi_resp.r; - axi_resp_o.r_valid = r_axi_resp.r_valid; - axi_resp_o.ar_ready = r_axi_resp.ar_ready; - axi_resp_o.b = w_axi_resp.b; - axi_resp_o.b_valid = w_axi_resp.b_valid; - axi_resp_o.w_ready = w_axi_resp.w_ready; - axi_resp_o.aw_ready = w_axi_resp.aw_ready; - - w_axi_req = '0; - w_axi_req.aw = axi_req_i.aw; - w_axi_req.aw_valid = axi_req_i.aw_valid; - w_axi_req.w = axi_req_i.w; - w_axi_req.w_valid = axi_req_i.w_valid; - w_axi_req.b_ready = axi_req_i.b_ready; - - r_axi_req = '0; - r_axi_req.ar = axi_req_i.ar; - r_axi_req.ar_valid = axi_req_i.ar_valid; - r_axi_req.r_ready = axi_req_i.r_ready; - end + axi_demux_simple #( + .AxiIdWidth ( IdWidth ), + .AtopSupport ( 1'b1 ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NoMstPorts ( 2 ), + .MaxTrans ( BufDepth ), + .AxiLookBits ( 1 ), // select is fixed, do not need it + .UniqueIds ( 1'b1 ) // Can be set as ports are statically selected -> reduces HW + ) i_split_read_write ( + .clk_i, + .rst_ni, + .test_i, + .slv_req_i ( axi_req_i ), + .slv_ar_select_i ( 1'b0 ), + .slv_aw_select_i ( 1'b1 ), + .slv_resp_o ( axi_resp_o ), + .mst_reqs_o ( {w_axi_req, r_axi_req} ), + .mst_resps_i ( {w_axi_resp, r_axi_resp} ) + ); axi_to_mem #( .axi_req_t ( axi_req_t ), diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index 107d3fe75..1d86cc3eb 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -49,6 +49,8 @@ module axi_to_mem_split #( input logic clk_i, /// Asynchronous reset, active low. input logic rst_ni, + /// Testmode enable + input logic test_i, /// The unit is busy handling an AXI4+ATOP request. output logic busy_o, /// AXI4+ATOP slave port, request input. @@ -81,18 +83,26 @@ module axi_to_mem_split #( logic read_busy, write_busy; - axi_rw_split #( - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ) - ) i_axi_rw_split ( + // split AXI bus in read and write + axi_demux_simple #( + .AxiIdWidth ( IdWidth ), + .AtopSupport ( 1'b1 ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NoMstPorts ( 2 ), + .MaxTrans ( BufDepth ), + .AxiLookBits ( 1 ), // select is fixed, do not need it + .UniqueIds ( 1'b1 ) // Can be set as ports are statically selected -> reduces HW + ) i_split_read_write ( .clk_i, .rst_ni, - .slv_req_i ( axi_req_i ), - .slv_resp_o ( axi_resp_o ), - .mst_read_req_o ( axi_read_req ), - .mst_read_resp_i ( axi_read_resp ), - .mst_write_req_o ( axi_write_req ), - .mst_write_resp_i ( axi_write_resp ) + .test_i, + .slv_req_i ( axi_req_i ), + .slv_ar_select_i ( 1'b0 ), + .slv_aw_select_i ( 1'b1 ), + .slv_resp_o ( axi_resp_o ), + .mst_reqs_o ( {axi_write_req, axi_read_req} ), + .mst_resps_i ( {axi_write_resp, axi_read_resp} ) ); assign busy_o = read_busy || write_busy;