diff --git a/.ci/Memora.yml b/.ci/Memora.yml index deda96773..c8fd967de 100644 --- a/.ci/Memora.yml +++ b/.ci/Memora.yml @@ -294,6 +294,7 @@ artifacts: - src/axi_intf.sv - src/axi_test.sv - src/axi_demux.sv + - src/axi_to_detailed_mem.sv - src/axi_to_mem.sv - src/axi_to_mem_banked.sv - test/tb_axi_to_mem_banked.sv diff --git a/.github/workflows/doc.yml b/.github/workflows/doc.yml index 0f50b87e5..2996e519b 100644 --- a/.github/workflows/doc.yml +++ b/.github/workflows/doc.yml @@ -60,8 +60,9 @@ jobs: - name: Deploy documentation uses: JamesIves/github-pages-deploy-action@v4 if: > - github.event_name == 'push' - || github.event.pull_request.head.repo.full_name == github.repository + (github.event_name == 'push' + || github.event.pull_request.head.repo.full_name == github.repository) && + github.ref == 'refs/heads/master' with: token: ${{ secrets.GH_PAGES }} branch: gh-pages # The branch the action should deploy to. diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml index 560eaedbb..96456f43e 100644 --- a/.github/workflows/gitlab-ci.yml +++ b/.github/workflows/gitlab-ci.yml @@ -4,10 +4,6 @@ on: branches-ignore: - gh-pages # deployment target branch (this workflow should not exist on that branch anyway) - v** # such branch names conflict with tags - pull_request: - branches-ignore: - - gh-pages # deployment target branch (this workflow should not exist on that branch anyway) - - v** # such branch names conflict with tags workflow_dispatch: jobs: diff --git a/Bender.yml b/Bender.yml index 8f16f74cb..d5cc6d008 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ package: - "Florian Zaruba " dependencies: - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.27.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 } diff --git a/CHANGELOG.md b/CHANGELOG.md index 328a8e818..d3b0caf4b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased +### Fixed +- `axi_to_detailed_mem`: Ensure proper propagation or `err` and `exokay` signals. + ## 0.39.0 - 2023-07-20 ### Added diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv index 691a1f5c8..8f5c11d21 100644 --- a/src/axi_to_detailed_mem.sv +++ b/src/axi_to_detailed_mem.sv @@ -122,6 +122,7 @@ module axi_to_detailed_mem #( addr_t addr; axi_pkg::atop_t atop; logic lock; + axi_strb_t strb; axi_id_t id; logic last; axi_pkg::qos_t qos; @@ -133,7 +134,13 @@ module axi_to_detailed_mem #( axi_pkg::region_t region; } meta_t; - axi_data_t mem_rdata, + typedef struct packed { + axi_data_t data; + logic [NumBanks-1:0] err; + logic [NumBanks-1:0] exokay; + } mem_rsp_t; + + mem_rsp_t mem_rdata, m2s_resp; axi_pkg::len_t r_cnt_d, r_cnt_q, w_cnt_d, w_cnt_q; @@ -188,6 +195,7 @@ module axi_to_detailed_mem #( addr: addr_t'(axi_pkg::aligned_addr(axi_req_i.ar.addr, axi_req_i.ar.size)), atop: '0, lock: axi_req_i.ar.lock, + strb: '0, id: axi_req_i.ar.id, last: (axi_req_i.ar.len == '0), qos: axi_req_i.ar.qos, @@ -224,6 +232,7 @@ module axi_to_detailed_mem #( wr_meta.addr = wr_meta_q.addr + axi_pkg::num_bytes(wr_meta_q.size); if (axi_req_i.w_valid) begin wr_valid = 1'b1; + wr_meta.strb = axi_req_i.w.strb; if (wr_ready) begin axi_resp_o.w_ready = 1'b1; w_cnt_d--; @@ -236,6 +245,7 @@ module axi_to_detailed_mem #( addr: addr_t'(axi_pkg::aligned_addr(axi_req_i.aw.addr, axi_req_i.aw.size)), atop: axi_req_i.aw.atop, lock: axi_req_i.aw.lock, + strb: axi_req_i.w.strb, id: axi_req_i.aw.id, last: (axi_req_i.aw.len == '0), qos: axi_req_i.aw.qos, @@ -384,7 +394,7 @@ module axi_to_detailed_mem #( // Interface memory as stream. stream_to_mem #( .mem_req_t ( mem_req_t ), - .mem_resp_t ( axi_data_t ), + .mem_resp_t ( mem_rsp_t ), .BufDepth ( BufDepth ) ) i_stream_to_mem ( .clk_i, @@ -438,15 +448,25 @@ module axi_to_detailed_mem #( assign mem_region_o[i] = banked_req_atop[i].region; end + logic [NumBanks-1:0][1:0] tmp_ersp; + logic [NumBanks-1:0][1:0] bank_ersp; + for (genvar i = 0; i < NumBanks; i++) begin + assign mem_rdata.err[i] = tmp_ersp[i][0]; + assign mem_rdata.exokay[i] = tmp_ersp[i][1]; + assign bank_ersp[i][0] = mem_err_i[i]; + assign bank_ersp[i][1] = mem_exokay_i[i]; + end + // Split single memory request to desired number of banks. - mem_to_banks #( - .AddrWidth ( AddrWidth ), - .DataWidth ( DataWidth ), - .NumBanks ( NumBanks ), - .HideStrb ( HideStrb ), - .MaxTrans ( BufDepth ), - .FifoDepth ( OutFifoDepth ), - .AtopWidth ( $bits(tmp_atop_t) ) + mem_to_banks_detailed #( + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .RUserWidth ( 2 ), + .NumBanks ( NumBanks ), + .HideStrb ( HideStrb ), + .MaxTrans ( BufDepth ), + .FifoDepth ( OutFifoDepth ), + .WUserWidth ( $bits(tmp_atop_t) ) ) i_mem_to_banks ( .clk_i, .rst_ni, @@ -455,19 +475,21 @@ module axi_to_detailed_mem #( .addr_i ( mem_req.addr ), .wdata_i ( mem_req.wdata ), .strb_i ( mem_req.strb ), - .atop_i ( mem_req_atop ), + .wuser_i ( mem_req_atop ), .we_i ( mem_req.we ), .rvalid_o ( mem_rvalid ), - .rdata_o ( mem_rdata ), + .rdata_o ( mem_rdata.data ), + .ruser_o ( tmp_ersp ), .bank_req_o ( mem_req_o ), .bank_gnt_i ( mem_gnt_i ), .bank_addr_o ( mem_addr_o ), .bank_wdata_o ( mem_wdata_o ), .bank_strb_o ( mem_strb_o ), - .bank_atop_o ( banked_req_atop ), + .bank_wuser_o ( banked_req_atop ), .bank_we_o ( mem_we_o ), .bank_rvalid_i ( mem_rvalid_i ), - .bank_rdata_i ( mem_rdata_i ) + .bank_rdata_i ( mem_rdata_i ), + .bank_ruser_i ( bank_ersp ) ); // Join memory read data and meta data stream. @@ -496,19 +518,63 @@ module axi_to_detailed_mem #( .ready_i ({axi_req_i.b_ready, axi_req_i.r_ready }) ); + localparam NumBytesPerBank = DataWidth/NumBanks/8; + + logic [NumBanks-1:0] meta_buf_bank_strb, meta_buf_size_enable; + logic resp_b_err, resp_b_exokay, resp_r_err, resp_r_exokay; + + // Collect `err` and `exokay` from all banks + // To ensure correct propagation, `err` is grouped with `OR` and `exokay` is grouped with `AND`. + for (genvar i = 0; i < NumBanks; i++) begin + // Set active write banks based on strobe + assign meta_buf_bank_strb[i] = |meta_buf.strb[i*NumBytesPerBank +: NumBytesPerBank]; + // Set active read banks based on size and address offset: (bank.end > addr) && (bank.start < addr+size) + assign meta_buf_size_enable[i] = ((i*NumBytesPerBank + NumBytesPerBank) > (meta_buf.addr % DataWidth/8)) && + ((i*NumBytesPerBank) < ((meta_buf.addr % DataWidth/8) + 1<