diff --git a/.github/workflows/doc.yml b/.github/workflows/doc.yml index d598aeb3b..0f50b87e5 100644 --- a/.github/workflows/doc.yml +++ b/.github/workflows/doc.yml @@ -17,38 +17,20 @@ jobs: runs-on: ubuntu-latest # will fail) steps: - name: Checkout - uses: actions/checkout@v2 + uses: actions/checkout@v3 with: persist-credentials: false - - name: Cache cargo registry - uses: actions/cache@v1 + - name: Install Bender + uses: pulp-platform/pulp-actions/bender-install@v2 with: - path: ~/.cargo/registry - key: ubuntu-latest-cargo-registry-${{ hashFiles('.github/workflows/doc.yml') }} + version: 0.27.2 - - name: Cache cargo index - uses: actions/cache@v1 - with: - path: ~/.cargo/git - key: ubuntu-latest-cargo-index-${{ hashFiles('.github/workflows/doc.yml') }} - - - name: Cache cargo binaries - uses: actions/cache@v1 - with: - path: ~/.cargo/bin - key: ubuntu-latest-cargo-binaries-${{ hashFiles('.github/workflows/doc.yml') }} - - - name: Install Bender and Morty + - name: Install Morty run: | - rustup update stable --no-self-update && rustup default stable - if ! $(which bender); then - cargo install bender --version 0.23.1 - fi - if ! $(which morty); then - cargo install --git https://github.com/zarubaf/morty --rev 4855119c1378d45d9ac35cfa525725d2786e68f3 - fi - shell: bash + sudo mkdir -p /tools/morty && sudo chmod 777 /tools/morty + cd /tools/morty && curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/morty/init -sSf | bash -s -- 0.9.0 + echo "PATH=/tools/morty:$PATH" >> ${GITHUB_ENV} - name: Build documentation run: | @@ -76,14 +58,14 @@ jobs: echo "DOC_TARGET=$DOC_TARGET" >> $GITHUB_ENV - name: Deploy documentation - uses: JamesIves/github-pages-deploy-action@releases/v3 + uses: JamesIves/github-pages-deploy-action@v4 if: > github.event_name == 'push' || github.event.pull_request.head.repo.full_name == github.repository with: - ACCESS_TOKEN: ${{ secrets.ACCESS_TOKEN }} - BRANCH: gh-pages # The branch the action should deploy to. - FOLDER: docs # The folder the action should deploy. - TARGET_FOLDER: ${{ env.DOC_TARGET }} - CLEAN: true # remove files from `TARGET_FOLDER` that are not in `FOLDER` + token: ${{ secrets.GH_PAGES }} + branch: gh-pages # The branch the action should deploy to. + folder: docs # The folder the action should deploy. + target-folder: ${{ env.DOC_TARGET }} + clean: true # remove files from `TARGET_FOLDER` that are not in `FOLDER` # (`rsync --delete`) diff --git a/Bender.yml b/Bender.yml index 3c4a29be1..8f16f74cb 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,10 +7,12 @@ package: - "Matheus Cavalcante " - "Tim Fischer " - "Noah Huetter " + - "Cyril Koenig " - "Andreas Kurth " - "Stefan Mach " - "Samuel Riedel " - "Wolfgang Rönninger " + - "Paul Scheffler " - "Fabian Schuiki " - "Luca Valente " - "Nils Wistoff " diff --git a/CHANGELOG.md b/CHANGELOG.md index c2bfa2743..ab8b06b78 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,30 +8,62 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased ### Added -- Add `axi_chan_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type -- Add `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used - to compare two AXI buses on an FPGA. -- Add `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream. -- Add `axi_rw_join` and `axi_rw_split` to split/join AXI buses. -- Add `#_width` functions returning the width of the AXI channels. -- Add `axi_lite_dw_converter`: Convert the data width of AXI4-Lite transactions. Emmits the - appropriate amount of downstream transactions to perform the whole requested access. - +- Synthesizable IPs: + - `axi_bus_compare` and `axi_slave_compare`; two synthesizable verification IPs meant to be used + to compare two AXI buses on an FPGA. + - `axi_lite_from_mem` and `axi_from_mem` acting like SRAMs making AXI4 requests downstream. + - `axi_lite_dw_converter`: Convert the data width of AXI4-Lite transactions. Emits the + appropriate amount of downstream transactions to perform the whole requested access. + - `axi_rw_join` and `axi_rw_split` to split/join the read and write channels of an AXI bus. +- `CT`-macros allowing to instantiate AXI structs with custom channel type names. +- `axi_pkg': Add documentation to `xbar_cfg_t`. +- Testbench IPs: + - `axi_chan_compare.sv`: Non-synthesizable module comparing two AXI channels of the same type + - Add `axi_file_master` to `axi_test`, allowing file-based AXI verification approaches. + - Add `#_width` functions to `axi_test` returning the width of the AXI channels. ### Changed -- `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter. This prevents - AWs from being issued to one master port while Ws from another burst are ongoing to another - master port. This is required to prevents deadlocks due to circular waits downstream. -- `axi_xbar`: Add parameter `PipelineStages` to `axi_pkg::xbar_cfg_t`. This adds `axi_multicuts` - in the crossed connections in the xbar between the demuxes and muxes. -- `axi_pkg`: Add documentation to `xbar_cfg_t`. -- Move `mem_to_banks` to `common_cells`. -- Update `common_cells` from version `v1.26.0` to `v1.27.0`. +- Synthesizable IPs: + - `axi_demux`: Replace FIFO between AW and W channel by a register plus a counter. This prevents + AWs from being issued to one master port while Ws from another burst are ongoing to another + master port. This is required to prevents deadlocks due to circular waits downstream. Removes + `FallThrough` parameter from `axi_demux`. + - Split the `axi_demux` logic and timing decoupling. A new module called `axi_demux_simple` contains + the core logic. + - `axi_dw_downsizer` uses `axi_pkg::RESP_EXOKAY` as a default value. + - Simplify the `casez` in `axi_id_remap`. + - Add optional explicit mapping to the `axi_id_serialize` module. + - Expand `axi_to_mem` to `axi_to_detailed_mem` exposing all of AXI's side-signals; namely `id`, `user`, + `cache`, `prot`, `qos`, `region`, `atop`. Add possibility to inject `err` and `exokay`. + - `axi_xbar`: Add parameter `PipelineStages` to `axi_pkg::xbar_cfg_t`. This adds `axi_multicuts` + in the crossed connections in the `xbar` between the *demuxes* and *muxes*. Improve inline + documentation. + - Move `mem_to_banks` to `common_cells`. +- `axi_pkg`: Improve for better compatibility with *Vivado*. +- `axi_test: + - `axi_lite_rand_slave`: `R` response field is now randomized. + - Remove excessive prints from random master and slave. + - Properly size-align the address. - `axi_pkg`: Define `localparams` to define AXI type widths. -- `axi_test:axi_rand_lite_slave`: R response field is now random. +- Update `common_cells` from version `v1.26.0` to `v1.27.0`. +- Tooling: + - Use `pulp-platform/pulp-actions/gitlab-ci@v2` in the GitHub CI to communicate with the internal CI. + - Bump `DC Shell version` from `2019.12` to `2022.03` + - No longer check *ModelSim* versions `10.7e` and `2021.3`, add `2022.3`. + - More thorough verification runs for the `xbar`. + - Start transitioning from shell script to Makefile to run simulations. +- Use `scripts/update_authors` to update authors, slight manual fixes performed. ### Fixed +- `axi_to_mem_banked`: Reduce hardware by properly setting `UniqueIds`. +- `axi_to_mem_interleaved` and `axi_to_mem_split` properly instantiates a demultiplexer now. + Adds `test_i` port for DFT. +### Breaking Changes +There are breaking changes between `v0.38.0` and `v0.39.0`: +- `axi_demux`: `FallThrough` parameter was removed. +- `axi_xbar`: `axi_pkg::xbar_cfg_t` added `PipelineStages` parameter. +- `axi_to_mem_interleaved` and `axi_to_mem_split`: Added `test_i` input port. ## 0.38.0 - 2022-09-28 diff --git a/README.md b/README.md index 734154136..962185172 100644 --- a/README.md +++ b/README.md @@ -26,6 +26,7 @@ In addition to the documents linked in the following table, we are setting up [d | [`axi_cdc`](src/axi_cdc.sv) | AXI clock domain crossing based on a Gray FIFO implementation. | | | [`axi_cut`](src/axi_cut.sv) | Breaks all combinatorial paths between its input and output. | | | [`axi_delayer`](src/axi_delayer.sv) | Synthesizable module which can (randomly) delays AXI channels. | | +| [`axi_demux_simple`](src/axi_demux_simple.sv) | Demux without spill registers. | [Doc](doc/axi_demux.md) | | [`axi_demux`](src/axi_demux.sv) | Demultiplexes an AXI bus from one slave port to multiple master ports. | [Doc](doc/axi_demux.md) | | [`axi_dw_converter`](src/axi_dw_converter.sv) | A data width converter between AXI interfaces of any data width. | | | [`axi_dw_downsizer`](src/axi_dw_downsizer.sv) | A data width converter between a wide AXI master and a narrower AXI slave. | | @@ -59,6 +60,7 @@ In addition to the documents linked in the following table, we are setting up [d | [`axi_rw_join`](src/axi_rw_join.sv) | Joins a read and a write slave into one single read / write master. | | | [`axi_rw_split`](src/axi_rw_split.sv) | Splits a single read / write slave into one read and one write master. | | | [`axi_serializer`](src/axi_serializer.sv) | Serializes transactions with different IDs to the same ID. | | +| [`axi_slave_compare`](src/axi_slave_compare.sv) | Compares two slave devices. | | | [`axi_throttle`](src/axi_throttle.sv) | Limits the maximum number of outstanding transfers sent to the downstream logic. | | | [`axi_test`](src/axi_test.sv) | A set of testbench utilities for AXI interfaces. | | | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv) | AXI4 to AXI4-Lite protocol converter. | | @@ -85,6 +87,7 @@ In addition to the modules above, which are available in synthesis and simulatio | [`axi_chan_logger`](src/axi_test.sv) | Logs the transactions of an AXI4(+ATOPs) port to files. | | [`axi_driver`](src/axi_test.sv) | Low-level driver for AXI4(+ATOPs) that can send and receive individual beats on any channel. | | [`axi_dumper`](src/axi_dumper.sv) | Dumps log to file to be interpreted by `axi_dumper_interpret` script for debugging purposes. | +| [`axi_file_master`](src/axi_test.sv) | AXI4 master for file-based testbenches | | [`axi_lite_driver`](src/axi_test.sv) | Low-level driver for AXI4-Lite that can send and receive individual beats on any channel. | | [`axi_lite_rand_master`](src/axi_test.sv) | AXI4-Lite master component that issues random transactions within user-defined constraints. | | [`axi_lite_rand_slave`](src/axi_test.sv) | AXI4-Lite slave component that responds to transactions with constrainable random delays and data. | diff --git a/VERSION b/VERSION index ca75280b0..4ef2eb086 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.38.0 +0.39.0 diff --git a/axi.core b/axi.core index e75ed636f..d3bf2f735 100644 --- a/axi.core +++ b/axi.core @@ -1,6 +1,6 @@ CAPI=2: -name : pulp-platform.org::axi:0.38.0 +name : pulp-platform.org::axi:0.39.0 filesets: rtl: @@ -22,7 +22,7 @@ filesets: - src/axi_cdc_src.sv - src/axi_cut.sv - src/axi_delayer.sv - - src/axi_demux.sv + - src/axi_demux_simple.sv - src/axi_dw_downsizer.sv - src/axi_dw_upsizer.sv - src/axi_fifo.sv @@ -31,6 +31,7 @@ filesets: - src/axi_isolate.sv - src/axi_join.sv - src/axi_lite_demux.sv + - src/axi_lite_dw_converter.sv - src/axi_lite_from_mem.sv - src/axi_lite_join.sv - src/axi_lite_lfsr.sv @@ -46,9 +47,10 @@ filesets: - src/axi_serializer.sv - src/axi_slave_compare.sv - src/axi_throttle.sv - - src/axi_to_mem.sv + - src/axi_to_detailed_mem.sv # Level 3 - src/axi_cdc.sv + - src/axi_demux.sv - src/axi_err_slv.sv - src/axi_dw_converter.sv - src/axi_from_mem.sv @@ -56,13 +58,14 @@ filesets: - src/axi_lfsr.sv - src/axi_multicut.sv - src/axi_to_axi_lite.sv - - src/axi_to_mem_banked.sv - - src/axi_to_mem_interleaved.sv - - src/axi_to_mem_split.sv + - src/axi_to_mem.sv # Level 4 - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - src/axi_xbar.sv + - src/axi_to_mem_banked.sv + - src/axi_to_mem_interleaved.sv + - src/axi_to_mem_split.sv - src/axi_chan_compare.sv - src/axi_dumper.sv - src/axi_sim_mem.sv @@ -87,6 +90,7 @@ filesets: - test/tb_axi_fifo.sv - test/tb_axi_isolate.sv - test/tb_axi_iw_converter.sv + - test/tb_axi_lite_dw_converter.sv - test/tb_axi_lite_mailbox.sv - test/tb_axi_lite_regs.sv - test/tb_axi_lite_to_apb.sv diff --git a/include/axi/typedef.svh b/include/axi/typedef.svh index 5eec91171..648c3fed7 100644 --- a/include/axi/typedef.svh +++ b/include/axi/typedef.svh @@ -11,6 +11,7 @@ // // Authors: // - Andreas Kurth +// - Thomas Benz // - Florian Zaruba // - Wolfgang Roenninger diff --git a/scripts/run_verilator.sh b/scripts/run_verilator.sh index ef21af120..dd9be3c0b 100755 --- a/scripts/run_verilator.sh +++ b/scripts/run_verilator.sh @@ -14,6 +14,7 @@ # - Fabian Schuiki # - Florian Zaruba # - Andreas Kurth +# - Thomas Benz set -e ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index b9656ddf6..9812c5ed5 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -13,6 +13,7 @@ # Authors: # - Andreas Kurth # - Fabian Schuiki +# - Wolfgang Roenninger set -euo pipefail ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) diff --git a/scripts/update_authors b/scripts/update_authors index 674bad51b..79fcc24eb 100755 --- a/scripts/update_authors +++ b/scripts/update_authors @@ -19,6 +19,7 @@ declare -A hide=( \ # Map each author name to an email address. declare -A emails=( \ ["Andreas Kurth"]="akurth@iis.ee.ethz.ch" \ + ["Cyril Koenig"]="cykoenig@iis.ee.ethz.ch" \ ["Fabian Schuiki"]="fschuiki@iis.ee.ethz.ch" \ ["Florian Zaruba"]="zarubaf@iis.ee.ethz.ch" \ ["Matheus Cavalcante"]="matheusd@iis.ee.ethz.ch" \ @@ -30,6 +31,8 @@ declare -A emails=( \ ["Luca Valente"]="luca.valente@unibo.it" \ ["Noah Huetter"]="huettern@ethz.ch" \ ["Nils Wistoff"]="nwistoff@iis.ee.ethz.ch" \ + ["Nicole Narr"]="narrn@ethz.ch" \ + ["Paul Scheffler"]="paulsc@iis.ee.ethz.ch" \ ["Tim Fischer"]="fischeti@iis.ee.ethz.ch" \ ) diff --git a/src/axi_chan_compare.sv b/src/axi_chan_compare.sv index 59c99179c..e2339aedf 100644 --- a/src/axi_chan_compare.sv +++ b/src/axi_chan_compare.sv @@ -9,9 +9,9 @@ // specific language governing permissions and limitations under the License. // // Authors: -// - Thomas Benz +// - Thomas Benz // - Paul Scheffler -// - Tim Fischer +// - Tim Fischer /// Non-synthesizable module comparing two AXI channels of the same type module axi_chan_compare #( diff --git a/src/axi_demux.sv b/src/axi_demux.sv index a5f8389ad..899d83521 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -9,7 +9,9 @@ // specific language governing permissions and limitations under the License. // // Authors: +// - Michael Rogenmoser // - Wolfgang Roenninger +// - Thomas Benz // - Andreas Kurth `include "common_cells/assertions.svh" diff --git a/src/axi_demux_simple.sv b/src/axi_demux_simple.sv index f77514c4f..1c11f794a 100644 --- a/src/axi_demux_simple.sv +++ b/src/axi_demux_simple.sv @@ -10,6 +10,8 @@ // // Authors: // - Wolfgang Roenninger +// - Michael Rogenmoser +// - Thomas Benz // - Andreas Kurth `include "common_cells/assertions.svh" diff --git a/src/axi_from_mem.sv b/src/axi_from_mem.sv index 23ed2d3af..466a384e3 100644 --- a/src/axi_from_mem.sv +++ b/src/axi_from_mem.sv @@ -10,7 +10,7 @@ // // Authors: // - Christopher Reinwardt -// - Nicole Narr `include "axi/typedef.svh" diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv index b032c7766..9a787dd25 100644 --- a/src/axi_id_serialize.sv +++ b/src/axi_id_serialize.sv @@ -11,6 +11,7 @@ // // Authors: // - Andreas Kurth +// - Paul Scheffler `include "axi/assign.svh" `include "axi/typedef.svh" diff --git a/src/axi_lite_dw_converter.sv b/src/axi_lite_dw_converter.sv index f70940674..d8055481f 100644 --- a/src/axi_lite_dw_converter.sv +++ b/src/axi_lite_dw_converter.sv @@ -9,7 +9,7 @@ // specific language governing permissions and limitations under the License. // Authors: -// - Wolfgang Rönninger +// - Wolfgang Roenninger /// # AXI4-Lite data width downsize module. /// diff --git a/src/axi_lite_from_mem.sv b/src/axi_lite_from_mem.sv index 6b5446c6b..e13793b37 100644 --- a/src/axi_lite_from_mem.sv +++ b/src/axi_lite_from_mem.sv @@ -10,6 +10,7 @@ // // Authors: // - Wolfgang Roenninger +// - Nicole Narr /// Protocol adapter which translates memory requests to the AXI4-Lite protocol. /// diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv index 11c0f8ba7..dd60c451e 100644 --- a/src/axi_pkg.sv +++ b/src/axi_pkg.sv @@ -12,8 +12,10 @@ // Authors: // - Andreas Kurth // - Florian Zaruba +// - Thomas Benz // - Wolfgang Roenninger // - Fabian Schuiki +// - Cyril Koenig // - Matheus Cavalcante //! AXI Package diff --git a/src/axi_test.sv b/src/axi_test.sv index 6fd789415..ea621d91e 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -13,6 +13,7 @@ // - Andreas Kurth // - Wolfgang Roenninger // - Fabian Schuiki +// - Thomas Benz // - Matheus Cavalcante diff --git a/src/axi_to_detailed_mem.sv b/src/axi_to_detailed_mem.sv index 3e6cfdcab..691a1f5c8 100644 --- a/src/axi_to_detailed_mem.sv +++ b/src/axi_to_detailed_mem.sv @@ -10,6 +10,7 @@ // Authors: // - Michael Rogenmoser +// - Thomas Benz `include "common_cells/registers.svh" /// AXI4+ATOP slave module which translates AXI bursts into a memory stream. diff --git a/src/axi_to_mem.sv b/src/axi_to_mem.sv index e935e69ff..37992d449 100644 --- a/src/axi_to_mem.sv +++ b/src/axi_to_mem.sv @@ -10,6 +10,7 @@ // Authors: // - Michael Rogenmoser +// - Thomas Benz `include "common_cells/registers.svh" /// AXI4+ATOP slave module which translates AXI bursts into a memory stream. diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv index 1d86cc3eb..28ce40831 100644 --- a/src/axi_to_mem_split.sv +++ b/src/axi_to_mem_split.sv @@ -10,6 +10,7 @@ // // Authors: // - Michael Rogenmoser +// - Thomas Benz `include "axi/assign.svh" /// AXI4+ATOP to memory-protocol interconnect. Completely separates the read and write channel to diff --git a/src_files.yml b/src_files.yml index 7c3743e41..16cc1ce00 100644 --- a/src_files.yml +++ b/src_files.yml @@ -21,7 +21,7 @@ axi: - src/axi_cdc_src.sv - src/axi_cut.sv - src/axi_delayer.sv - - src/axi_demux.sv + - src/axi_demux_simple.sv - src/axi_dw_downsizer.sv - src/axi_dw_upsizer.sv - src/axi_fifo.sv @@ -30,6 +30,7 @@ axi: - src/axi_isolate.sv - src/axi_join.sv - src/axi_lite_demux.sv + - src/axi_lite_dw_converter.sv - src/axi_lite_from_mem.sv - src/axi_lite_join.sv - src/axi_lite_lfsr.sv @@ -45,23 +46,25 @@ axi: - src/axi_serializer.sv - src/axi_slave_compare.sv - src/axi_throttle.sv - - src/axi_to_mem.sv + - src/axi_to_detailed_mem.sv # Level 3 - src/axi_cdc.sv + - src/axi_demux.sv - src/axi_err_slv.sv - - src/axi_from_mem.sv - src/axi_dw_converter.sv + - src/axi_from_mem.sv - src/axi_id_serialize.sv - src/axi_lfsr.sv - src/axi_multicut.sv - src/axi_to_axi_lite.sv - - src/axi_to_mem_banked.sv - - src/axi_to_mem_interleaved.sv - - src/axi_to_mem_split.sv + - src/axi_to_mem.sv # Level 4 - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - src/axi_xbar.sv + - src/axi_to_mem_banked.sv + - src/axi_to_mem_interleaved.sv + - src/axi_to_mem_split.sv # Level 5 - src/axi_xp.sv diff --git a/test/tb_axi_lite_dw_converter.sv b/test/tb_axi_lite_dw_converter.sv index 65319b0ad..e376cb1d6 100644 --- a/test/tb_axi_lite_dw_converter.sv +++ b/test/tb_axi_lite_dw_converter.sv @@ -8,7 +8,9 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Author: Wolfgang Roenninger +// Authors: +// - Wolfgang Roenninger +// - Michael Rogenmoser `include "axi/typedef.svh" diff --git a/test/tb_axi_slave_compare.sv b/test/tb_axi_slave_compare.sv index 45809e5d2..2fa47bdc7 100644 --- a/test/tb_axi_slave_compare.sv +++ b/test/tb_axi_slave_compare.sv @@ -2,7 +2,9 @@ // SPDX-License-Identifier: SHL-0.51 // // Authors: +// - Andreas Kurth // - Thomas Benz +// - Michael Rogenmoser `include "axi/assign.svh" `include "axi/typedef.svh"